JPS6337988B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention receives orthogonally multiplexed multiple quadrature amplitude modulation (hereinafter referred to as QAM) signals via a transmission line, samples them, and converts them into analog-digital (hereinafter referred to as QAM) signals.
It is abbreviated as AD. ) transform, filtering operation, discrete Fourier transform (hereinafter abbreviated as DFT) operation, etc. to demodulate a plurality of source baseband (hereinafter abbreviated as baseband) signals. Regarding phase/frequency control circuits.

The orthogonal multiplex transmission method, in which multiple QAM signals are orthogonally multiplexed and transmitted, and each baseband signal is demodulated on the receiving side, enables highly efficient data transmission.Moreover, by introducing DFT into the digital signal processing process, transmission and reception are possible. It is already known that the device is considerably simplified. (See, for example, 1978 Patent Application No. 19364 and 1978 Patent Application No. 19366.)
However, conventionally, there has been no known method for demodulating carrier phase control on the receiving side of an orthogonal multiplex transmission system that has good frequency tracking characteristics and is simple.

In view of this point, the present invention provides a pilot phase/frequency control circuit in a digital processing receiving apparatus for orthogonal multiplexed signals, especially when a pilot is inserted into a predetermined channel on the transmitting side for transmission.

This will be explained in detail below using the drawings.

Figure 1 is a diagram showing the spectrum arrangement of transmission signals in the orthogonal multiplex transmission system, where 1 is the frequency ₁ .
2 is the second QAM signal modulated with a complex carrier with frequency ₂ , 3 is the complex carrier with frequency _N-1 (however, N≧3 here). 4 is a pilot signal having a frequency of _N. However, according to the principle of orthogonal multiplex transmission system _{, k+1} − _k = _B (however, 1≦
k≦N-1, and _B is the baud rate of each baseband signal. ) It is assumed that a relationship has been established. On the receiving side, each QAM signal is demodulated from the signal having the spectral arrangement shown in Figure 1 to obtain a complex baseband signal.In this demodulation process, N modulation carriers are generally Requires demodulation carrier. However, if demodulation processing on the receiving side is performed by digital signal processing using DFT, the phase of the sampling clock is simply controlled using the phase information of the complex baseband signal obtained by demodulating the pilot signal. It is possible to equivalently control all demodulation carriers.

Now, if the received signal is y(t), y(t) is expressed as follows.

y(t)=2Re{ _N 〓 ⁿ⁼¹ x _o (t)e ^-j2 〓 ^fnt } …(1) where x _k (t) is a complex baseband signal modulating a modulation carrier with frequency _k . be.

y(t) is the frequency _s (where _s = M _B )
The output sampled with the sampling clock Y(z)
shall be. However, z=e ^j2 〓 ^f/fs . At this time, the k-th demodulated complex baseband signal β _k (z) is expressed as β _k (z)=Y(e ^−j2 〓 ^fk/fs ·z)·G(z) (2). However, 1≦k≦N, and G(z)
is a low-pass filter with an effective band of _B /2 on one side. Here, Y(z) and G(z) are demultiplexed as follows.
That is, In this case, equation (2) is The sequence of sample values of β _k (z) every T/2 seconds (T=1/ _B ) _β˜k (z ^M/2 ) is given by the following equation.

Here, if we use the relationships _k = f ₁ + (k-1) f _B and f _s = Mf _B , we get The signal processing expressed by equation (7) is as follows:
As described in No. 19366, this is realized using a preprocessing circuit, a DFT processing circuit, a polyphase circuit, etc.
According to this method, the multiplication coefficient e ^j2 〓 ^(k-1)l/M in the DFT processing circuit does not depend on the sampling frequency _s , and the frequency offset term e ^j2 〓 ^f1/fs is also predetermined on the transmitting side. It is determined by the ratio of ₁ and _B (e ^j2 〓 ^f1/fB ) ^1/M is read-only memory (hereinafter abbreviated as ROM).
It would be better to store it in . Therefore, all demodulation carriers ₁ , ₂ , ..., _N are generated from the sampling clock of frequency _s .

Here, the phase shift between the k-th modulation carrier and the k-th demodulation carrier is defined as θ _k (t), and this is regarded as the phase shift of the modulation carrier with respect to the demodulation carrier. In this case, equation (1) is expressed as y(t)=2Re{ _N 〓 ⁿ⁼¹ x _o (t)e ^-j2 〓 ^fnt+j 〓 ^n(t) }...(8). Here, since the pilot signal of frequency _N is inserted into the Nth channel as described above, x _N (t)=1. Therefore, the demodulated output of the Nth channel can be obtained from equations (6) and (8) as follows. (The band-limiting effect of filter G(z) is also taken into consideration).

Therefore, the imaginary part of the demodulated complex output β~ _N (z ^M/2 ) is expressed by the following equation.

Figure 2 shows the spectrum of In {β~ _o (z ^M/2 )} expressed by equation (10), and 5 is the spectrum of I _n {β~ o (z M/2)} expressed by equation (10).
The emission line spectrum obtained as the average of the terms, 6 is the spectrum broadening due to phase noise, 7 and 8 are (10)
This is the interference from adjacent channels expressed by the second term of the equation. As is clear from Figure 2, 9 in Figure 2
A low-pass filter with a pass characteristic as shown by
The signal γ _N (z ^M/2 ) obtained as the output by passing I _n {β~ _N (z ^M/2 )} is obtained by taking only the first term of equation (10), and is expressed by the following equation. expressed.

However, φ _N (t)=I _n {e ^j 〓 ^N(t) }. φ _N (t)
of
If Φ _N (z) is the z-transformed sample value sequence sampled every T _s seconds, then from equations (11) and (4), γ _N (z ^M/2 ) becomes Φ _N ( It can be seen that the series is obtained by extracting sample values every T/2 seconds after passing G(z) through the filter G(z). Here, G(z) is a low-pass filter, and the band of Φ _N (z) is usually G(z)
In the end, γ _N (z ^M/2 ) becomes Φ _N
It can be seen that the sample value series is obtained by extracting sample values every T/2 seconds from (z). That is, Therefore, a sample value sequence of sin θ _N (t) corresponding to the phase error θ _N (t) can be obtained from the sample value sequence γ _N (z ^M/2 ).

By the way, as is clear from the signal processing process described above, θ _N (t) follows the phase shift θ _s (t) from the normal phase of the sampling clock, and θ _N (t) = (f ₁ /f _s +N-1/M) θ _s (t)…(13
), the sample value of θ _N (t) is θ _s
It is proportional to the sample value of (t). Therefore, γ _N
A voltage controlled oscillator with an oscillation frequency _s is controlled by the sample value of sinθ _N (t) obtained from (z ^M/2 ),
If the output is used as a sampling clock, a phase-controlled sampling clock can be obtained, and therefore the phase of all demodulation carriers can be equivalently controlled.

However, although this method has an extremely simple circuit configuration, in an equivalent phase-locked loop consisting of a voltage-controlled oscillator → sampling circuit → digital demodulator → phase difference detection circuit → voltage-controlled oscillator, it is especially difficult to use the digital demodulator. The frequency tracking characteristics of the system are poor due to the large delay. For example, if an unstable voltage controlled oscillator is used in this system, there is a possibility that the phase-locked loop will not pull in properly due to the delay included in the system, resulting in periodic oscillation frequency fluctuations. In order to improve such deterioration of frequency tracking characteristics due to delay, it is necessary to detect not only phase difference information but also frequency difference information from the output of the digital demodulator and control the voltage controlled oscillator using both of these pieces of information. In the present invention, the control signal is obtained from the imaginary part of the demodulated complex output corresponding to the channel in which the pilot is inserted in advance, but another method is to obtain the control signal from the real part and the imaginary part of the demodulated complex output. There are other possible methods. However, in this case, the circuit becomes complicated. It is also possible to obtain it using only the real part, but in this case the phase error θ _N
Sample value series cosθ _N (t) obtained according to (t)
The stable point of θ _N (t) is no longer 0, and a steady phase error occurs. Therefore, a means for correcting this steady phase error is required, which makes the circuit complicated.

Therefore, the method of obtaining the control signal only from the imaginary part of the demodulated complex output as in the present invention is the simplest in terms of circuit scale.

The first object of the present invention is to provide a novel pilot phase/frequency control system based on the above principle that does not require a phase comparator circuit, a frequency multiplier circuit, etc. required in a normal phase-locked circuit, and has good frequency tracking characteristics of the system. The purpose is to provide circuits.

FIG. 3 is a block diagram showing a first specific embodiment of the pilot phase/frequency control circuit in the digital processing receiver for orthogonal multiplexed signals according to the present invention, and 10 is a block diagram of the digital processing receiver for orthogonal multiplexed signals. input terminal, 11 is a sampling circuit, 12
is an AD converter, 13 is a digital arithmetic processing unit, 1
8 is a low-pass filter, 19 is a frequency difference detection circuit,
20 is a synthesis circuit, and 21 is a voltage controlled oscillator.
The portion surrounded by the broken line 16 is a conventionally known processing section, and the other portions are the pilot phase/frequency control circuit according to the present invention. In FIG. 3, a signal received at an input terminal 10 is sampled by a sampling circuit 11 using a sampling clock of frequency _s , and digitally encoded by an AD converter 12. Further, this digitally encoded signal undergoes the demodulation process as described above in the digital arithmetic processing section 13, and output terminals 14 and 15 receive β~ ₁ (z ^M/2 ), β~ ₂ expressed by equation (7). (z ^M/2 ) is output. On the other hand, the output terminal 17 outputs β~ _N (z ^M/2 ) containing the complex pilot signal given by equation (9), and the imaginary part obtained from it passes through the low-pass filter 18 and is expressed by equation (12). It is converted into a sample value series γ _N (z ^{M/2 ) expressed as γ N (z M/2} ). The frequency difference detection circuit 19 has a built-in ROM, which is addressed by the sample value series γ _N (z ^M/2 ) to detect and output a temporal change in the phase signal. The synthesis circuit 20 synthesizes the output of the low-pass filter 18 and the output of the frequency difference detection circuit 19 using an adding means or the like, and controls the voltage controlled oscillator with the output. Through this control, the sampling circuit 11 receives the phase-controlled sampling clock from the voltage controlled oscillator 2.
Supplied from 1.

The above explanation is based on controlling the voltage controlled oscillator using the sample value series of sinθ _N (t) according to the phase error θ _N (t) as expressed by equation (12) and the frequency difference information obtained from the sample value series. By using the output as a sampling clock, phase control is achieved. That is, at some sample time
The sample value of the phase error at mTs is sin(θ+
m・△ωTs) (where Ts is the sampling period, m
Let be a positive integer, θ the steady phase error, and Δω the time variation of the phase error. ), the amount of change in phase error in the sampling period is expressed by the following equation.

sin(θ+m・△ωTs) −sin[θ+(m−1)△ω・Ts] ≒△ω・Ts・cosθ (where △ω≪θ≪1) Therefore, phase difference information and frequency difference information (upper A good control circuit can be realized by detecting the voltage-controlled oscillator (corresponding to Δω in the equation), controlling the voltage-controlled oscillator, and using its output as the sampling clock.

FIG. 5 shows phase difference information input to the combining circuit 20 with respect to the phase difference θ _N (t) generated in the imaginary part of the complex signal obtained from the output terminal 17 of FIG. Reference numeral 22 in FIG. 5 indicates the case where the imaginary part of the complex signal obtained from the output terminal 17 is inputted to the low-pass filter 18, and the output thereof is inputted as it is to the synthesis circuit 20, and the phase difference θ _N ( The phase difference information input to the combining circuit 20 with respect to t) is represented by a sine wave. However, the imaginary part of the output terminal 17 is input to the low-pass filter 18, and the output is once passed through a phase difference detection circuit having characteristics of an inverse trigonometric function as shown in FIG. When inputting the phase difference information to the circuit 20, as shown in FIG. 5, the output fluctuation of the input phase difference information becomes large. Therefore, the frequency range in which the voltage controlled oscillator 21 can oscillate is expanded.

The second object of the present invention is to provide a novel system based on the above principle, which does not require a phase comparator circuit, a frequency multiplier circuit, etc. required for a normal phase-locked circuit, has good frequency tracking characteristics, and has a large dynamic range. The object of the present invention is to provide a pilot phase/frequency control circuit.

FIG. 6 is a block diagram showing a second specific embodiment of the pilot phase/frequency control circuit in the digital processing receiver for orthogonal multiplexed signals according to the present invention, and 30 is a block diagram of the digital processing receiver for orthogonal multiplexed signals. input terminal, 31 is a sampling circuit, 32
is an AD converter, 33 is a digital arithmetic processing unit, 3
8 is a low-pass filter, 39 is a phase difference detection circuit, 4
0 is a frequency difference detection circuit, 41 is a synthesis circuit, and 42 is a voltage controlled oscillator. The portion surrounded by the broken line 36 is a conventionally known processing section, and the other portions are the pilot phase/frequency control circuit according to the present invention. In FIG. 6, a signal received at an input terminal 30 is sampled by a sampling circuit 31 using a sampling clock of frequency _s , and digitally encoded by an AD converter 32. Furthermore, this digitally encoded signal undergoes the demodulation process as described above in the digital arithmetic processing section 33, and output terminals 34 and 35 receive signals β ₁ ~(z ^M/2 ), β ₂ ~ as expressed by equations (7). ( ^zM/2 )
is output. On the other hand, the output terminal 37 contains the demodulated complex pilot signal given by equation (9) _.
(z ^M/2 ) is output, and the imaginary part obtained therefrom passes through the low-pass filter 38 and is converted into a sample value sequence γ _N (z ^M/2 ) expressed by equation (12). The phase difference detection circuit 39 detects the phase amount from the sample value series γ _N (z ^M/2 ). Further, the frequency difference detection circuit 40 detects a temporal change in the phase signal obtained by the phase difference detection circuit 39. The synthesis circuit 41 synthesizes the output of the phase difference detection circuit 39 and the output of the frequency difference detection circuit 40 using adding means or the like, and controls the voltage controlled oscillator with the output. Through this control, a phase-controlled sampling clock is supplied from the voltage controlled oscillator 42 to the sampling circuit 31.

FIG. 7 shows a phase difference detection circuit indicated by 39 in FIG. 6, a frequency difference detection circuit indicated by 40, and 4.
FIG. 1 is a circuit diagram showing a specific example of implementation of a control signal generating section configured by a combining circuit shown in FIG. In FIG. 7, a ROM designated by 51 receives digitally encoded γ _N input to an input terminal 50.
(z ^M/2 ) and outputs a digitally encoded phase difference signal θ _N (z ^M/2 ). This phase difference signal θ _N (z ^M/2 ) is input to the subtracter 53 at the same time that it is delayed by z ^−M/2 , that is, T/2 seconds, in a register 52 . In addition, the output signal z ^-M/2 θ _N (z ^M/2 ) of the register 52 is also input to the subtracter 53 and the output of the subtracter 53 is [θ _N
(z ^M/2 )−z ^−M/2 θ _N (z ^M/2 )] is obtained. That is, a signal corresponding to the temporal phase change is obtained at the output of the subtracter 53. Further, the adder 54 adds and synthesizes the phase difference signal obtained by the ROM 51 and the signal corresponding to the amount of phase change obtained by the subtracter 53. A digital-to-analog (hereinafter abbreviated as DA) converter 55 outputs an analog value corresponding to the composite signal obtained in this way to a terminal 5.
Output to 6. In addition, 39, 40, 41 in Figure 7
The blocks surrounded by broken lines correspond to the functional blocks with the same numbers in FIG. 6, respectively. From the above explanation, the input/output transfer function of the control signal generator shown in FIG. 7 is expressed as (2-z ^-M/2 ). A control signal generator having a transfer function (1-1/2z ^-M/2 ) proportional to this transfer function can also be realized as shown in FIG. That is, in FIG. 8, it is indicated by 61.
The ROM is addressed by γ _N (z ^M/2 ) input to the input terminal 60 and outputs a phase difference signal θ _N (z ^M/2 ). The thus obtained θ _N (z ^M/2 ) is input to the subtracter 63 on the one hand, and is multiplied by 1/2 using a 1-bit shift connection on the other hand, and then subjected to a delay of T/2 seconds in the register 62. The other input terminal of the attenuator 63 is reached. A digitally encoded signal (1-1/2z ^-M/2 )θ _N (z ^M/2 ) is obtained as the output of the subtracter 63, and by passing this through the DA converter 64, the output terminal 65 The desired analog control signal can be obtained.

Now, in both the implementation examples shown in FIGS. 7 and 8, a control signal for a voltage controlled oscillator is obtained by linearly combining a signal corresponding to a phase difference and a signal corresponding to a frequency difference. It is also possible. FIG. 9 is a circuit diagram showing a specific implementation example of a control signal generating section using such nonlinear combination. In FIG. 9, a ROM indicated by 71 receives a digitally encoded phase difference signal θ _N that is addressed by γ _N (z ^M/2 ) input to an input terminal 70.
Output (z ^M/2 ). This phase difference signal θ _N (z ^M/2 ) is
The signal is delayed by T/2 seconds at the register 72 and then reaches the attenuator 73, whereupon it is input to the attenuator 73 and selector 75. The signal (1-z ^-M/2 )・θ _N (z ^M/2 ) obtained as the output of the attenuator 73 is
It is input to the ROM 74 and selector 75.
The ROM 74 receives input frequency difference information (1-
z ^{- M/2} ) θ _N (z ^M/2 ), it is determined whether the absolute value thereof is larger or smaller than a predetermined value, and the determination result is output to the terminal 77. Depending on the determination result, the selector 75 selects frequency difference information (1-z ^{-M/2) if the absolute value of (1-z -M/2} )θ _N (z ^{M /2} ) is greater than or equal to a predetermined value.
Select θ _N (z ^M/2 ), and if the absolute value of (1-z ^{- M/2} )・θ _N (z ^M/2 ) is less than the predetermined value, phase difference information θ _N (z ^M/2 )
Select. Furthermore, the output of the selector 75 is converted into an analog value by a DA converter 76 and output terminal 78
leading to.

The pilot phase and
In a second specific embodiment of the frequency control circuit, the oscillation frequency of the voltage controlled oscillator is controlled by a composite signal of phase difference information and frequency difference information. Instead of obtaining a control signal using a composite signal of phase difference information and frequency difference information, the oscillation frequency of the voltage controlled oscillator is controlled using frequency difference information, and more local phase control is achieved using phase difference information. By performing the following steps, a pilot phase/frequency control circuit with excellent frequency tracking characteristics and phase acquisition characteristics can be obtained. That is, it is now assumed that the frequency of the sampling clock is controlled by the frequency difference information, and the steady phase shift of the sampling clock at this time is θ _s (therefore, θ _s is independent of time). At this time, the phase shift θ _k (where 1≦k≦N) between the k-th modulation carrier and the k-th demodulation carrier is θ _k = (f ₁ /f) corresponding to equation (13). _s + k-1/M) θ _s (14) Since the following relationship holds true, from the detected phase difference information θ _N , θ _k = f ₁ /f _s + (k-1)/M/f ₁ /f _s + (N-1)
/M·θ _N (15) θ _k is obtained as follows. Furthermore, by using the complex quantity Γ _k = e ^-j 〓 ^k (16) calculated using this θ _k , the phase error of the k-th demodulated complex baseband signal β ~ _k (z ^M/2 ) can be compensated. can do.
In other words, by the same process as in finding equation (9), β~ _k (z ^M/2 ) = [k-th channel main signal] + [interference signal from (k+1)th channel] + [(k-1)th channel main signal] + [(k-1)th channel main signal] ) Interference signal from the channel] However, [K-th channel main signal] [Interference signal from the (k+1)th channel] [Interference signal from the (k-1)th channel] By multiplying β~ _k (z ^M/2 ) given by Γ _k defined by equation (16), the phase error e ^j 〓 ^k included in the k-th channel main signal can be removed. . Note that the operation of calculating Γ _k (where 1≦k≦N) from θ _N can be easily realized using a ROM or the like.

A third object of the present invention is to provide a pilot phase/frequency control circuit for a digital processing receiver for orthogonal multiplexed signals, which is based on the above principle and has good frequency tracking characteristics and phase acquisition characteristics.

FIG. 10 is a block diagram showing a third specific embodiment of the pilot phase/frequency control circuit in the digital processing receiver for orthogonal multiplexed signals according to the present invention. In FIG. 10, the received signal input to the input terminal 80 is processed by the sampling circuit 81 to determine the frequency
sampled by the sampling clock of _s , and the AD converter 8
The data is digitally encoded at step 2. Further, this digitally encoded signal undergoes demodulation processing in a digital arithmetic processing section 83, and output terminals 85, 86, and 87 receive β~ ₁ (zM ^/2 ), β~ ₂ (zM/2), and β~2 ( ^zM/2 ), respectively. β～
_N
(z ^M/2 ) is output. The demodulated complex baseband signals β~ ₁ (zM ^/2 ), β~ ₂ (zM ^/2 ),...
, β~
_N (z ^M/2 ) is multiplied by phase difference correction signals Γ ₁ , Γ ₂ , ..., Γ _N by multipliers 88, 89, 90, etc., and output terminals 91, 92, 93 receive the steady phase error. A removed demodulated complex baseband signal is obtained. Furthermore, among the demodulated complex baseband signals thus obtained, the Nth demodulated complex baseband signal corresponding to the pilot channel obtained from the output end 93 has its imaginary part passed through a low-pass filter 95 to remove unnecessary components. Ru. The phase difference detection circuit 96 detects the corresponding phase difference from the output of the low-pass filter 95, and transmits the output to the frequency difference detection circuit 98.
and is input to the phase difference correction signal generation circuit 97.
The phase difference correction signal generation circuit 97 receives input θ _N from (14),
Γ ₁ , Γ ₂ , ..., Γ _N are generated according to equation (15). Further, the frequency difference detection circuit 98 detects a change in phase information given as an input, and controls the oscillation frequency of the voltage controlled oscillator 99 with its output. Phase difference correction signal generation circuit 97 and frequency difference detection circuit 9
These processes of 8 can be easily realized using ROM. On the other hand, the voltage controlled oscillator 99 supplies the sampling clock subjected to frequency control to the sampling circuit 81. In FIG. 10, a portion surrounded by a broken line 84 is a conventionally known processing section.

In the above, the phase difference was detected from the output of the low-pass filter using the phase difference detection circuit, and the output was supplied to the frequency difference detection circuit and the phase difference correction signal generation circuit. ROM used for difference detection circuit and phase difference correction signal generation circuit
If the characteristic of the inverse trigonometric function is also included in the phase difference detection circuit, the phase difference detection circuit can be omitted.

A fourth object of the present invention is to provide a pilot phase/frequency control circuit in a digital processing receiver for orthogonal multiplexed signals, which has good frequency tracking characteristics and phase acquisition characteristics based on the above-mentioned principle, and which can be realized with a simple circuit scale. It is about providing.

FIG. 11 is a block diagram showing a fourth specific embodiment of the pilot phase/frequency control circuit in the digital processing receiver for orthogonal multiplexed signals according to the present invention. In FIG. 11, the input terminal 100
The received signal inputted to the sampling circuit 101 is sampled by a sampling clock of frequency _s , and is digitally encoded by an AD converter 102. Further, this digitally encoded signal undergoes demodulation processing in a digital arithmetic processing section 103 and is outputted at an output terminal 105,
106 and 107 have β~ ₁ (z ^M/2 ) and β~ ₂ (z ^M
/2 )
and β~ _N (z ^M/2 ) are output. The demodulated complex baseband signals β~ ₁ (z ^M/2 ), β~ ₂ thus obtained
(z ^M/2 ), ..., β~ _N (z ^M/2 ) are multipliers 108, 10
9 and 110 etc., the phase difference correction signals Γ ₁ , Γ ₂ ,
..., Γ _N are respectively multiplied, and the output terminals 111, 112,
At 113, a demodulated complex baseband signal with stationary phase errors removed is obtained. Furthermore, among the demodulated complex baseband signals obtained in this way, the output terminal 1
The imaginary part of the Nth demodulated complex baseband signal corresponding to the pilot channel obtained from 13 is passed through a low-pass filter 115 to remove unnecessary components. The demodulated complex baseband signal from which unnecessary components have been removed is supplied to a frequency difference detection circuit 117 and a phase difference correction signal generation circuit 116.

The phase difference correction signal generation circuit 116 generates Γ ₁ , Γ ₂ , . . . , Γ _N from the input sin θ _N. Further, the frequency difference detection circuit 117 detects a time change amount of the phase information given as an input, and controls the oscillation frequency of the voltage controlled oscillator 118 with its output. These processes are realized using ROM. On the other hand, the voltage controlled oscillator 118 supplies the sampling clock subjected to frequency control in this manner to the sampling circuit 101. In addition, in FIG. 11, a portion surrounded by a broken line 104 is a conventionally known processing section.

As explained above, according to the present invention, a pilot phase/frequency control circuit for a digital processing receiving device for orthogonal multiplexed signals that exhibits good tracking characteristics even if there is a delay in the digital arithmetic processing section, etc. can be obtained. The practical value is extremely large.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the spectrum arrangement of transmission signals in the orthogonal multiplex transmission system, where 1 is the frequency ₁ .
2 is the second QAM signal modulated with a complex carrier of frequency ₂ , 3 is the ( _N-1 )th QAM signal modulated with a complex carrier of frequency N-1. QAM signal 4 is a pilot signal with frequency _N. FIG. 2 is a diagram showing the spectrum of the demodulated pilot signal and the imaginary part of the interference component. FIG. 3 is a block diagram showing a first specific embodiment of the pilot phase/frequency control circuit in the digital processing receiver for orthogonal multiplexed signals according to the present invention, and the portion surrounded by 16 broken lines is the sampling circuit. 11. A conventionally known digital processing unit consisting of an AD converter 12, a digital arithmetic processing unit 13, etc.; 18;
is a low-pass filter, 19 is a frequency difference detection circuit, 2
0 is a synthesis circuit, and 21 is a voltage controlled oscillator. FIG. 4 is a diagram showing the characteristics of inverse trigonometric functions. FIG. 5 shows the phase difference information signal input to the synthesis circuit for the phase error θ _N (t) in the demodulated pilot signal, and 22 indicates the case where the output of the low-pass filter is directly input to the synthesis circuit. 23 indicates the case where the output of the low-pass filter is input to the phase difference detection circuit, the phase difference is detected, and the output is supplied to the synthesis circuit. FIG. 6 is a block diagram showing a second specific embodiment of the pilot phase/frequency control circuit in the digital processing receiver for orthogonal multiplexed signals according to the present invention. A conventionally known digital processing unit consisting of a conversion circuit 31, an AD converter 32, a digital arithmetic processing unit 33, etc.
38 is a low-pass filter, 39 is a phase difference detection circuit,
40 is a frequency difference detection circuit, 41 is a synthesis circuit, 42
is a voltage controlled oscillator. FIG. 7 shows the phase difference detection circuit indicated by 39 in FIG. 6, the frequency difference detection circuit indicated by 40, and 41.
51 is a circuit diagram showing a specific implementation example of a control signal generation section configured with a synthesis circuit shown in FIG.
is ROM, 52 is a register, 53 is a subtracter, 54
is an adder, and 55 is a DA converter. FIG. 8 is a circuit diagram showing another specific implementation example of the control signal oscillator similar to that in FIG.
ROM, 62 is a register, 63 is a subtracter, 64 is
It is a DA converter. FIG. 9 is a circuit diagram showing yet another specific implementation example of the control signal oscillator similar to FIG. 7,
71 is a ROM, 72 is a register, 73 is a subtracter,
74 is a ROM, 75 is a selector, and 76 is a DA converter. FIG. 10 is a block diagram showing a third specific embodiment of the pilot phase/frequency control circuit in the digital processing receiver for orthogonal multiplexed signals according to the present invention, and the portion surrounded by the broken line 84 is a block diagram of the conventional circuit. 88, 89 and 90 are multipliers, 95 is a low-pass filter, 96 is a phase difference detection circuit, 97 is a phase difference correction signal generation circuit, 98 is a frequency difference detection circuit, and 99 is a voltage controlled oscillator. be. FIG. 11 is a block diagram showing a fourth specific embodiment of the pilot phase/frequency control circuit in the digital processing receiving apparatus for orthogonal multiplexed signals according to the present invention, and the portion surrounded by the broken line 104 is the conventional circuit. processing units, 108, 109 and 110
is a multiplier, 115 is a low-pass filter, 116 is a phase difference correction signal generator, 117 is a frequency difference detection circuit, and 118 is a voltage controlled oscillator.

Claims (1)

[Claims] 1. A plurality of orthogonally multiplexed orthogonal amplitude modulated signals are received via a transmission line, and a plurality of source basebands are obtained by sampling, analog-to-digital conversion, filtering operations, discrete Fourier transform operations, etc. A digital processing receiving device for orthogonal multiplexed signals that demodulates a signal includes a low-pass filter that removes unnecessary frequency components from the imaginary part of the demodulated complex output corresponding to a channel in which a pilot is inserted in advance on the transmitting side; A frequency difference detection circuit that detects a temporal change in the phase error of the pilot frequency using the output of a low-pass filter, and a synthesis method that combines the output of the low-pass filter and the output of the frequency difference detection circuit. A pilot phase/frequency control circuit in a digital processing receiving device for orthogonal multiplexed signals, which comprises a circuit and a voltage controlled oscillator whose oscillation frequency is controlled by the output of the synthesis circuit, and uses the output of the voltage controlled oscillator as a sampling clock. . 2 Orthogonal multiplexing, which receives multiple orthogonally multiplexed amplitude modulated signals via a transmission line and demodulates multiple source baseband signals by sampling, analog-to-digital conversion, filtering, discrete Fourier transform, etc. A digital signal processing receiving device includes a low-pass filter for removing unnecessary frequency components from the imaginary part of a demodulated complex output corresponding to a channel into which a pilot is inserted in advance on the transmitting side; a phase difference detection circuit that detects a phase error in a pilot frequency using an output; a frequency difference detection circuit that detects a temporal change in the output of the phase difference detection circuit; and an output of the phase difference detection circuit and the frequency difference. a synthesis circuit that synthesizes the outputs of the detection circuit;
A pilot phase/frequency control circuit in a digital processing receiver for orthogonal multiplexed signals, comprising a voltage controlled oscillator whose oscillation frequency is controlled by the output of the synthesis circuit, and using the output of the voltage controlled oscillator as a sampling clock. 3 Orthogonal multiplexing, which receives multiple orthogonally multiplexed amplitude modulated signals via a transmission path and demodulates multiple source baseband signals by sampling, analog-to-digital conversion, filtering, discrete Fourier transform, etc. A group of multipliers that remove stationary phase errors by multiplying each of a plurality of demodulated complex outputs obtained in parallel in a digital signal processing type receiving device by a phase difference correction signal, and a channel in which a pilot is inserted in advance on the transmitting side. A low-pass filter removes unnecessary frequency components from the imaginary part of the complex output from which the phase error has been removed from the demodulated complex output corresponding to the demodulated complex output, and the phase error of the pilot frequency is detected using the output of the low-pass filter. a phase difference detection circuit that generates the phase difference correction signal according to an output of the phase difference detection circuit; and a frequency difference detection circuit that detects a temporal change in the output of the phase difference detection circuit. A pilot phase/frequency control circuit in a digital processing receiving device for orthogonal multiplexed signals, which comprises a detection circuit and a voltage controlled oscillator whose oscillation frequency is controlled by the output of the frequency difference detection circuit, and which samples and clocks the output of the voltage controlled oscillator. . 4 Orthogonal multiplexing, which receives multiple orthogonally multiplexed amplitude modulated signals via a transmission path and demodulates multiple source baseband signals by sampling, analog-to-digital conversion, filtering, discrete Fourier transform, etc. A signal digital processing receiver includes a group of multipliers that remove stationary phase errors by multiplying each of a plurality of demodulated complex outputs obtained in parallel by a phase difference correction signal, and a group of multipliers that remove stationary phase errors by multiplying each of a plurality of demodulated complex outputs obtained in parallel. a low-pass filter for removing unnecessary frequency components from the imaginary part of the complex output from which the phase error has been removed from the demodulated complex output corresponding to the channel; a phase difference correction signal generation circuit that generates a phase difference correction signal; a frequency difference detection circuit that detects a temporal change in a phase error of a pilot frequency using the output of the low-pass filter;
A pilot phase frequency control circuit in a digital processing receiver for orthogonal multiplexed signals, comprising a voltage controlled oscillator whose oscillation frequency is controlled by the output of the frequency difference detection circuit, and which samples and clocks the output of the voltage controlled oscillator.