JPS6341076B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a display control device.

In recent years, technological advances in electronic devices such as electronic desktop calculators and microcomputers have been remarkable, and they are now widely used. Accordingly, display devices are playing an extremely important role as inexpensive and affordable output devices for consumer use, and LEDs (light emitting diodes), fluorescent display tubes, and the like are widely used.

In cases where the number of digits of characters to be displayed is large, a dynamic drive method is adopted in which segments of the display element are time-divided and display signals are sequentially applied. Display processing methods for this dynamic drive system include a software control method and a dedicated hardware method. As a software control method, the display is controlled by a general-purpose microcomputer that is not equipped with dedicated hardware. In this case, a general-purpose port is used for digit signals and segment signals, and the digit signals and segment signals are controlled periodically. The disadvantage of this method is that because it is a dynamic drive system, it is necessary to set the display cycle to approximately 200 Hz or more and to make the display duty as large as possible, which creates major restrictions on program creation.

For example, in the case of a 10-digit dynamic display, the display period for one digit is 0.5 ms (when the display cycle is 200 Hz), and for a microcontroller with an instruction cycle of 20 μs, the display period is 25 ms.
There is only a command period, and there is a problem in that one-digit display processing and other data processing (such as key scan) must be executed during this period. In addition, in the case of complex data processing, there is no time to control the display and it is difficult to program, so the display processing is interrupted and the entire time is devoted to data processing. For this reason, there is a drawback that the display remains off for a long time when complex data processing is executed.

In order to minimize this drawback, it is necessary to significantly increase the instruction cycle of the microcomputer. However, there is a proportional relationship between operating frequency and power consumption, and increasing the operating frequency results in an increase in power consumption. For this reason, low power consumption type microcomputers employ the following method of performing display processing using dedicated hardware. The conventional dedicated hardware method is to store display data in a memory, read it out from the memory and display it in synchronization with the display cycle using dedicated hardware.

Next, an example of a circuit for obtaining a display signal using dedicated hardware will be described with reference to FIG.

The data processing device 100 controls a read/write control circuit (hereinafter referred to as an R/W circuit) 103 via a data line and an R/W control signal 98. Memories 101 and 102 are connected to each other by a switch circuit 106, and have a structure that can be considered as a substantially integrated unit. These two memories are connected to the R/W circuit 103 by data lines 110-1 to 110-3. The address of the memory 101 is specified by the address circuit 104, but the address of the memory 102 is specified by the switching circuit 1.
05, the address signal 113 is synchronized with the address line 111 or the display synchronization signal 114. Turning on the display of the display control signal 99;
This is a signal that controls turning off the light; a high level turns the display off, and a low level turns the display on. In the erased state, the switch circuit 106 is closed when the control signal 99 takes a high level, and the memory 101 and the memory 102 are assumed to be equivalent, and the read/write is controlled by the R/W circuit 103. Address designation is carried out from address line 111 from address circuit 104 by control signal 99 input to switching circuit 105.
It is carried out by. In this off state, display data can be written into the memory 102 by the data processing device 100. Next, when the lighting state is turned on, the control signal 99 becomes low level, the synchronization signal generation circuit 107 sequentially supplies the display synchronization signal 114 to the display device 108, and the memory 101 and the memory 102 write and read the common line to the switch circuit 106. The memory 102 operates completely independently from the memory 101 and the R/W circuit 103. memory 10 at the same time
2 is specified by the display address signal 11 synchronized with the display synchronization signal 114 by the switching circuit 105.
3, the contents of the memory 102 are periodically read out, resulting in a display output 115, and the display device 108 is driven by the display drive circuit 109. In this way, this display control device periodically reads and displays the display data written in the memory 102 independently of the data processing device, and as in the software method, the data processing device periodically outputs a digit signal. The advantage is that there is no need to control segment signals.

However, with this conventional method, the memory 1
Since the memory 102 and the memory 102 are separated, the memory 102 cannot be used by the data processing device. This has a major drawback, for example, if the number of bits of the memory 102 is determined so that it can display 4 to 16 digits, and it is used for 4-digit display, the memory corresponding to 12-digit display will be completely wasted.

Furthermore, since the memory 101 and the memory 102 are separated, there is also a drawback that display data (especially in the case of indicators) in the memory 102 cannot be used as processing data.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display control device that eliminates the drawbacks of the conventional display memory, such as the inability to use the display memory efficiently and the inability to use display data as arithmetic processing data.

The display control device according to the present invention is capable of reading and writing data from the data processing device, the synchronization signal generation circuit, the display drive circuit, and at least part of the storage device using an addressing signal from the data processing device, and the synchronization signal generation circuit A storage device configured with a multi-output storage circuit that can be read out independently of reading and writing of the data processing device by an addressing signal from the data processing device, reads display data from the multi-output storage circuit independently of the data processing device, It is characterized by being derived from a display body driving circuit.

According to the present invention, at least the four types of devices described above, including a storage device for storing data, a data processing device for processing the data, a display driving device for driving a display, and a display synchronization signal generation device for generating a display synchronization signal, are used. In an integrated circuit configured on a single substrate, data can be read and written by an addressing signal from the data processing device, and data can be read and written by the data processing device by an addressing signal from the synchronization signal generation circuit. A multi-output storage device that can be read asynchronously constitutes at least a part of the storage device, and reads and writes data from the storage device in response to the addressing signal from the data processing device, and simultaneously reads and writes data from the storage device. A display that reads data from the multi-output storage device constituting a part of the storage device using the display synchronization signal from the display synchronization signal generation device, asynchronously with the reading and writing of the processing device, and leads it to the display driving device. A control device is obtained.

An embodiment of the present invention will be described with reference to FIG.

Memory 201 is read/write (R/W)
It is a memory circuit (RAM) that is addressed by an address line 212 under the control of a circuit 203 and an address circuit 204, and in which data can be written and read through a data line 210. The memory 202 is connected to the address line 211 under the control of the R/W circuit 203 and the address circuit 204 independently of the display address signal 213 synchronized with the display synchronization signal generation circuit 207.
address line 2 under the control of the R/W circuit 203 and the address circuit 204 by the display address signal 213 while simultaneously writing and reading data through the data line 210.
It is possible to read data through the data line 215 independently of the access from 11, that is, the control by the R/W circuit 203 and address circuit 204 and the control by the display synchronization signal generation circuit 207 are two very independent controls. It is a memory circuit that can be controlled simultaneously from the system. In controlling the R/W circuit 203 and the address circuit 204, the memories 201 and 20 are connected by address lines 212 and 211.
2 can be accessed equally and independently of the display address signal 213, so the display can be performed while the arithmetic processing performed under the control of the R/W circuit 203 and the address circuit 204 is executed using the memories 201 and 202 equally. Display processing under the control of the synchronization signal generation circuit 207 can be performed simultaneously using the memory 202.

FIG. 3 shows an example of the configuration of one bit of the memory 202 used in the embodiment shown in FIG. 301,
Reference numeral 302 constitutes a flip-flop by cross-connecting the input and output of an inverter. 303,
304, 305 are transistors, 306, 307
Address lines 308, 309, and 310 are data lines. Transistors 303 and 304 are for address selection, and address input line 30 is controlled by R/W circuit 203 and address circuit 204.
7. This address input line 307
corresponds to the address line 211. The cell write/read common lines 309 and 310 are the data line 2.
Corresponds to 10. The transistor 305 is for address selection and is controlled by an address input line 306 controlled by a display synchronization signal generation circuit, and data is read out to a read common line 308. Address input line 306 corresponds to address line 213, and read common line 308 corresponds to read-only data line 215, respectively. What must be noted here is that the inverters 301 and 302 and the transistor 305 must be designed so that the contents of the latch are not destroyed when the transistor 305 turns on and outputs to the data line 308.

As described above, in the present invention, the memory 202 in which display data is written has a structure in which writing and reading from the data processing device side and reading from the display control side can be performed independently.

Therefore, in the past, the display memory only stored display data and could not be used on the data processing side, but in the present invention, the memory 202 can be used not only to store display data but also to store processed data. For example, when displaying 4 digits on a 4- to 16-digit display control device, conventionally the remaining 12 digits were not used, but in the present invention, the remaining 12 digits are used to store processing data. Since the data processing device can continue writing independently of display, memory usage efficiency is greatly improved. Furthermore, there is an advantage that the data processing device can read display data (particularly indicators) without erasing the display.

As explained above, the present invention can provide an epoch-making display control device that has significantly improved memory usage efficiency compared to the prior art.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a conventional display control circuit.
FIG. 2 is a block diagram showing a display and control device according to an embodiment of the present invention, and FIG. 3 is a circuit diagram showing the structure of a memory section of the embodiment of FIG. 99...Display control signal, 98...R/W control signal,
100...Data processing device, 101, 102, 20
1...RAM, 202...Storage device according to the present invention, 1
03,203...R/W circuit, 104,204...Address circuit, 105...Switching circuit, 106...Switch circuit, 107,207...Synchronizing signal generation circuit, 1
08,208...Display body, 109,209...Display body drive circuit, 110-1,110-2,110-
3,210-1,210-2,215...data line, 111,112,116,211,212...
Address line, 113, 213... Display address signal, 114, 214... Display synchronization signal, 215... Read-only data bus, 301, 302... Inverter, 303, 304, 305... Transistor,
306, 307...Address line, 308, 309,
310...Data line.

Claims (1)

[Claims] 1. In a display control device comprising a storage means for storing data, a data processing means for processing the data, a display driving means for driving a display, and a display synchronization signal generation means for generating a display synchronization signal. , at least a part of said storage means being formed by a multi-output storage means having a first address input and a first output, a second address input and a second output, and said first address input and second output of said multi-output storage means. The and second address inputs receive an addressing signal from the data processing means and an addressing signal from the synchronization signal generation circuit, respectively, and are read out in parallel by the data processing means and the synchronization signal generation circuit. made possible,
At the same time as the data is read from the storage means by the addressing signal from the data processing means, the data is read from the display synchronization signal generation means from the multi-output storage means in parallel with the reading by the data processing means. A display control device characterized in that data is read out using a display synchronization signal and is output to a display driving device.