JPH0128419B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data aggregation device that reads or writes data to a memory cassette for aggregating registered transaction data.

[Prior Art] For example, there is an electronic cash register for registering product sales data in which a memory cassette is provided in a removable manner and transaction data registered in the memory cassette is aggregated. A plurality of electronic cash registers with this configuration are installed in the store, and when the day's registration work is finished, for example, the memory cassettes are collected from each cash register, and the memory cassettes are installed in the store's office, for example. The memory cassettes are loaded into a data aggregation device and the data accumulated in each memory cassette is aggregated.

Conventionally, such data aggregation devices have one receptacle, which is the loading section for the memory cassette.
Data aggregation from the memory cassette loaded in the receptacle is controlled by a microcomputer by controlling an interface provided in the receptacle.

In this way, the conventional data aggregation device had only one receptacle, so in order to aggregate the data in the memory cassettes collected from each cache register, memory cassettes had to be loaded one by one into the receptacles alternately. The problem was that the work was troublesome and the work efficiency was low.

Therefore, a plurality of receptacles are provided in the data aggregation device, and an interface is provided corresponding to each receptacle.The collected memory cassettes are loaded into each receptacle and electrically connected to the interface, and a microcomputer is used to connect each interface. It is conceivable to sequentially control the memory cassettes and aggregate data from each memory cassette. In this case, if it is impossible to know from the outside which memory cassette's data is currently being aggregated while data aggregation control is in progress, there is a risk that the memory cassette whose data is being aggregated may be accidentally removed from the receptacle. Therefore, it is necessary to provide a display element corresponding to each receptacle, and to notify that data collection is in progress by driving the display element corresponding to the receptacle loaded with the memory cassette being data collection. To that end, the 8th
As shown in the figure, each receptacle 81a, 81b
An interface 83 provided in the memory cassettes 82a and 82b is electrically coupled to the
Apart from a, 83b, each display element 84a, 84b
Output ports 86a, 86b for outputting drive signals to driver circuits 85a, 85b are prepared, and these output ports 86a, 86b and interfaces 83a, 83b are connected via a bus line 87.
Connect to CPU88. For the CPU 88, a program for controlling the interfaces 83a, 83b and the output ports 86a, 86b had to be configured as follows. That is, when accessing the memory cassette 82a, the display element 84a corresponding to the receptacle 81a loaded with the memory cassette 82a is
drive. When accessing the memory cassette 82b, the display element 84b corresponding to the receptacle 81b loaded with the memory cassette 82b is driven.

[Problems to be Solved by the Invention] As described above, when a display element is provided corresponding to each receptacle and each display element is to be controlled by a CPU, an output port dedicated to each display element must be provided. must be prepared, and
There was a problem in that the CPU had to incorporate special program data to control this output port, making the configuration complicated.

Therefore, the present invention provides a plurality of receptacles and a display element corresponding to each receptacle, so that data can be totaled by loading a plurality of memory cassettes at the same time, and the memory cassette during data collection can be driven by the display element. Each display element is selectively operated using a signal for specifying a memory cassette from which data is to be read or written, and an output port dedicated to the display element and a signal for controlling this output port The present invention aims to provide a data aggregation device that can simplify the configuration by eliminating the need for special program data.

[Means for Solving the Problems] As shown in FIG. 9, the data aggregation device of the present invention includes memory cassettes 91a and 91b that are electrically and detachably coupled to a memory cassette receiving portion of the device main body. interface 92a, 92
a plurality of receptacles 93a, each having a
93b, and each receptacle 9
Display elements 94a and 94b correspond to 3a and 93b.
A match signal is sent to the interfaces 92a and 92b of each of the receptacles 93a and 93b when a preset unique code and the code of the address signal inputted from the CPU 95 via the address bus line 96 match. Coincidence detection circuits 97a and 97b that output, and this coincidence detection circuit 97
Designation signal output terminals 98a and 98b output a memory cassette designation signal that designates the memory cassette electrically coupled to the interface in response to a match signal from a and 97b.
and each display element 94a,
Driver circuits 99a and 99b are respectively provided for the display elements 94a and 94b to output memory cassette designation signals from designation signal output terminals 98a and 98b provided at interfaces 92a and 92b of receptacles 93a and 93b corresponding to the display elements 94a and 94b, respectively. The above driver circuits 99a, 99b according to
Accordingly, the display elements 94a and 94b are operated.

[Function] In the data aggregation device with such a configuration,
The memory cassettes 91a, 91b collected from each electronic cash register are inserted into each receptacle 93a,
93b and interfaces 92a, 92
electrically coupled with b. In this state, the coincidence detection circuit 97 of each interface 92a, 92b
The code of the address signal is input from the CPU 95 to the a and 97b via the address bus line 96. A match detection circuit 97a whose code is equal to a preset unique code,
A match signal is output only from 97b. Then, in response to this coincidence signal, the coincidence detection circuit 97
an interface 92 provided with a and 97b;
A memory cassette designation signal is output from designation signal output terminals 98a and 98b of interfaces 92a and 92b, designating access to memory cassettes 91a and 91b electrically coupled to the interfaces 92a and 92b, and reading or writing data. It is done. Further, in response to the memory cassette designation signal, the driver circuits 99a and 99b select the display elements 94 corresponding to the receptacles 93a and 93b loaded with the memory cassettes 91a and 91b.
a and 94b are driven, and the memory cassette 91
It is notified that data is being read or written to a and 91b.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a perspective view of an electronic cash register 1, and FIG. 2 is a store data processor (hereinafter referred to as a data aggregation device) according to the present invention.
FIG. 2 is a perspective view of the SDP.

First, a predetermined number of memory cassettes 3 are loaded into the receptacles of the memory cassette receiving section 20 of the SDP 2, and by operating various keys on the keyboard 21, a unique register number is preset in each memory cassette 3. With,
Tax table, Price Lutsk Atup (hereinafter PLU)
(abbreviated as ), data, and common data such as date are written sequentially. In other words, this memory cassette 3 contains a conventional electronic cache register random access memory (hereinafter abbreviated as RAM).
At least some of the information stored within is stored.

The memory cassette 3 in which predetermined data has been stored in this way is loaded into the memory cassette receptacle 11 of the electronic cash register 1 whose programmed register number matches, and the memory cassette 3 on the keyboard 12 is loaded into the electronic cash register 1. When you perform registration tasks by operating the keys,
The registration data at this time is recorded in the memory cassette 3.

The memory cassette 3 in which the registration data has been recorded is removed from the electronic cash register 1 at the end of the day, for example, and stored in the SDP 2.
The SDP 2 aggregates all registered data of a predetermined number of memory cassettes 3 to obtain the total sales of all electronic cash registers. At this time, since each memory cassette 3 has its own unique register number preset, the SDP2
It is possible to easily recognize which register the registered data was sold at. In addition, in Figure 1, 13
and 22 in FIG. 2 are display sections.

Figure 3 shows the memory cassette receiving section 20 of SDP2.
FIG. This memory cassette receiving section 20
is provided with 16 receptacles _20-1 to _20-16 , each having an interface to which the memory cassette 3 is electrically and detachably coupled, and each receptacle _{20-1 to} 20-2.
Light emitting diodes _23-1 to _23-16 as display elements are provided above _0-16 , respectively.
Also, next to each of the receptacles _20-1 to _20-16 are 16 storage receptacles _20-17 to 2 for storing unused memory cassettes.
_0-32 are provided.

FIG. 5 shows an electronic circuit section 200 of the SDP 2 and 16 memory cassettes _3-1 to _3-16 detachably connected to the electronic circuit section 200.
The electronic circuit section 200 includes a central processing unit (hereinafter abbreviated as CPU) 201, a read-only memory (hereinafter abbreviated as ROM) 202, a RAM 203, and the CPU 201 and each memory cassette 3-1 to _3-3 .
- ₁₆ interfaces 204 to 219 for electrically connecting with each other.
Further, the CPU 201 is a keyboard drive circuit 2.
20 to the keyboard circuit 221;
It is coupled to a display circuit 223 via a display drive circuit 222 and to a dot printer 225 via a printer drive circuit 224.

FIG. 6 shows the interface 204 shown in FIG.
FIG. 2 is a circuit configuration diagram showing details of the circuit configuration. Of course, the circuit configurations of the other interfaces 205-219 are similar to that shown in FIG. 6, except that the coincidence detection circuit _204-1 is configured to have a unique code.

Coincidence detection circuit 2 of this interface 204
_04-1 compares a 4-bit unique code that is preset by turning on and off four switches, for example, and the code of the address signal input from the CPU 201 via the address bus line. When the two match, a match signal is output from, for example, an output terminal "8", and the input terminal T of the flip-flop circuit _204-2 is connected to the output terminal "8". Then, with the coincidence signal being supplied to this input terminal T, the CPU 2
When a signal is applied to the input terminal D of this flip-flop circuit _204-2 from 01 through the data bus line, this flip-flop circuit 204
_-2 supplies an output signal to AND gates _204-3 and _204-4 and transistor _204-5 to open these AND gates _204-3 and _204-4 , and this transistor _204-5
This will maintain continuity. This will cause the CPU
The read and write signals sent from 201 via the read and write lines pass through AND gates _204-3 and _204-4 .

On the other hand, a control terminal C of a driver circuit _226-1 shown in FIG. ₄ is connected to a chip energizing terminal (designated signal output terminal) _204-9 , which is the output terminal of the transistor 204-5. This driver circuit _226-1 includes a light emitting diode 23 corresponding to the receptacle _20-1 in which the interface 204 is provided between the +V power supply and ground.
₋₁ is connected in series. Note that the reset terminal R of flip-flop _204-2 is
A reset line from CPU 201 is connected.

The decoder _204-6 generates an output signal from the output terminal "0", "1", "2" or "3" according to the information signal sent from the CPU 201 via the data bus line, and outputs the output signal from the output terminal "0", "1", "2" or "3". interface 2
Memory cassette _3-1 electrically coupled to 04
Select the memory chip. Further, addressing of this memory cassette _3-1 is performed by a plurality of addressing lines each including an inverter _204-7 having a buffer function, and data transfer between this memory cassette _3-1 and the CPU 201 is bidirectional. Inverter 2 exhibiting buffer function in
This is implemented via multiple data bus lines, including _04-8 .

FIG. 7 is a circuit diagram of the memory cassette 3.
This memory cassette 3 is inserted into the receptacle 2 provided in the memory cassette receiving section 20 of the SDP 2, for example.
_0-1 , the circuitry of this memory cassette 3 will be coupled to the interface 204 shown in FIG. That is, this memory cassette 3 has four RAMs 301, 302, 30.
3,304 RAMs are built-in, and each RAM30
A plurality of addressing lines 305 for specifying addresses 1 to 304 are each coupled to an addressing line with an inverter _204-7 of the interface 204, and each of the RAMs 301 to
A plurality of data lines 306 to 304 each connect to an inverter 204 of interface 204.
- coupled to the data bus line with ₈ . Furthermore, four chip selection lines 307 for selecting these RAMs 301 to 304 are coupled to output terminals "0", "1", "2" and "3" of the decoder _204-6 of the interface 204. . Further, the read line 308 and write line 309 for these RAMs 301 to 304 are connected to the AND gate 20 of the interface 204, respectively.
_4-3 and _204-4 .

This memory cassette 3 is the interface 20.
When combined with 4, RAM 301 to 304
Reading and writing of data to and from the memory cassette 3 is performed by an external power source (not shown) via the power line of the interface 204 and the power lines 310 and 311 of the memory cassette 3. At this time, the stored contents of the RAMs 301 to 304 are held by the internal power supply E. And each RAM
A photocoupler 314 consisting of a photodiode 312 and a phototransistor 313 is used to energize elements 301-304. That is, this memory cassette 3 is connected to the interface 2.
When the transistor 204-5 is turned on by the Q output of the flip-flop _204-2 at the interface 204, a current flows between _the collector and emitter of the transistor _204-5 and through the photodiode 312. 312 emits light. As a result, the phototransistor 313 becomes conductive, and each RAM 30
1 to 304 are connected to an external power source. That is,
Coincidence detection circuit 204- of interface 204
_1. The flip-flop _204-2 and the transistor _204-5 form a circuit for generating a memory cassette designation signal for designating access to the memory cassette _3-1 loaded in the interface 204, and the chip activation terminal _204-9 functions as an output terminal for a memory cassette designation signal. and,
Such a circuit is connected to each interface 204-2.
This circuit of one of the interfaces is operated by a memory cassette selection command sent from the CPU 201 via the address bus line, and the chip energizing terminal 204-
₉ , a memory cassette designation signal is outputted to the memory cassette connected to the interface.

Furthermore, as mentioned above, interface 2
In 04, the chip energizing terminal _204-9 , which functions as the output terminal for the memory cassette designation signal, is +V.
It is coupled to a control terminal C of a driver circuit _226-1 that forms a series circuit with the light emitting diode _23-1 between the power supply and ground. Then, when a memory cassette designation signal is output from the chip energizing terminal _204-9 , the driver circuit _226-1 is driven, and the light emitting diode _23-1 is repeatedly driven to +V at a constant cycle.
It is connected to a power source to make it blink.
The driver circuits for blinking the light emitting diodes are also provided in the other interfaces 205 to 219, respectively, and cause the corresponding light emitting diodes _23-2 to _23-16 to blink.

In this way, the light emitting diodes 23- as display elements are arranged above each receptacle _20-1 to _20-16 of the memory cassette receiving section 20.
₁ to _23-16 , when data is read or written to the memory cassette loaded in the corresponding receptacle, the chip energizing terminal 204- of the interface provided in the corresponding receptacle is activated.
The flashing operation is performed by the memory cassette designation signal output from ₉ . In other words, light emitting diode 2
By blinking one of the light emitting diodes among _3-1 to _23-16 , data is read or written to the memory cassette loaded in the receptacle corresponding to the light emitting diode. You can know that. The blinking operation of the light emitting diodes _23-1 to _23-16 is originally performed from each memory cassette _3-1 to _3-16 to 1.
Since this is done using a memory cassette designation signal used to select and access one memory cassette, the light emitting diodes 23-1 to _23-1 are connected to the CPU 201 in addition to the interfaces 204-219.
3- There is no need to provide a dedicated output port to output drive signals to the ₁₆ driver circuits, and special program data can be set to control this output port and operate each display element. This is no longer necessary, and the configuration can be simplified.

In the above embodiments, a light emitting diode was used as the display element, but it is needless to say that the present invention is not limited to this.

[Effects of the Invention] As detailed above, according to the present invention, each display element provided corresponding to a plurality of receptacles into which memory cassettes are loaded can be controlled by a dedicated output port and this output port. It can be operated selectively according to the selective reading and writing operations of each memory cassette without using program data to operate each display element, making the configuration easy and improving the efficiency of data aggregation work. We can provide a data aggregation device to obtain data.

[Brief explanation of drawings]

1 to 7 are views showing one embodiment of the present invention, in which FIG. 1 is a perspective view of an electronic cash register, and FIG. 2 is a store data processor (SDP) according to the present invention. The perspective view of Figure 3 is
Figure 4 shows the memory cassette receiving section of the SDP, Figure 4 shows the light emitting diode drive circuit, Figure 5 shows the
FIG. 6 is a detailed circuit diagram of the interface circuit, FIG. 7 is a circuit diagram of a memory cassette, FIG. 8 is a block diagram showing the conventional configuration, and FIG. 9 is a block diagram of the present invention. FIG. 2 is a block diagram showing the configuration. 2...Store data processor (SDP), 3
...Memory cassette, 20...Memory cassette receiving section, _20-1 to _20-16 ...Receptacle, _23-1
~ _23-16 ...Light emitting diode (display element), 20
1...Central processing unit (CPU), 204-219
...interface, _204-1 ...coincidence detection circuit,
_204-2 ...Flip-flop, _204-5 ...Transistor, _204-9 ...Chip energizing terminal (designated signal output terminal), _226-1 ...Driver circuit.

Claims (1)

[Claims] 1 A plurality of receptacles provided in the memory cassette receiving portion of the device main body, each having an interface to which a memory cassette is electrically and detachably coupled, and a plurality of receptacles provided in the memory cassette receiving portion corresponding to each receptacle. The display element is provided at the interface of each of the receptacles, and outputs a match signal when a preset unique code matches the code of the address signal input from the CPU via the address bus line. a coincidence detection circuit, and a memory cassette provided at each interface of each of the receptacles and designating for accessing a memory cassette electrically coupled to the corresponding interface in response to a coincidence signal from the corresponding coincidence detection circuit; In response to a memory cassette designation signal from a designation signal output terminal that outputs a designation signal and a designation signal output terminal provided for each of the display elements and provided at the interface of the receptacle corresponding to the display element, A data aggregation device comprising a driver circuit that operates the display element.