JPS6351414B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital filter, and more particularly, it sequentially reads numerical table outputs from an accumulator using vectors corresponding to each bit of a sample value, and accumulates the values. This invention relates to a digital filter that obtains a filter output by calculation.

According to theory, in general, in a digital filter, when the input sequence is a discrete signal (sample value) x(nT) obtained by sampling a continuous signal x(t) at an interval of T (seconds), the output The series y(nT) is: y(nT)= _k 〓 ^k=0 a _k x {(n-k)T}+ _L 〓 ^l=1 b _l y{(n-l)T} ...(1) It is obtained from a constant coefficient linear difference equation, and is also a sample value. Equation (1) represents a cyclic digital filter when at least one b _l is not zero, and represents an acyclic digital filter when all b _l are zero. For convenience, equation (1) is expressed as y _o = _k 〓 ^k=0 a _k x _ok + _L 〓 ^l=1 b _l y _ol ……(2). However, x _ok △ =x{(n-k)T} (k=0, 1, ..., K), y _ol △ =y{(n-l)
T} (l=0, 1, ..., L). Furthermore, equation (2) can be formally expressed as Y= _N - ₁ 〓 ⁱ⁼⁰ α _i Z _i ...(3). However, Y=y _o , α _i is a _k or
b _l and Z _i represent x _ok or y _ol , respectively.

If the expression (3) is used as is, N multiplications and (N-1) additions must be performed to obtain the filter output Y at one sampling point.
When handled digitally, since these multiplications and additions are binary operations, it takes time to obtain the output value Y, and the circuit configuration becomes very complex because a multiplier must be provided.

One of the features of digital filters is that so-called time division multiplexing is possible, in which one piece of hardware can equivalently operate as a plurality (R) of filters. In order to operate as R filters, the multiplication and addition must be completed within the time T/R, but in reality, the multiplicity R cannot be increased because the calculation time is long. Also, a simple substance (R=
Even when used as a filter in 1), the sampling period T cannot be made small due to the long computation time, so the frequency that can be handled cannot be made high.

For this reason, there are several known methods to obtain the filter output value of equation (3) without using a binary multiplier. Peled, A. and Liu, B.: “A new
“hardware realization of digital filters”
IEEE Trans. Acoust., Speech & Signal
Process., ASSP-22, 6, p. 456 (1974) and Alain Croisier et al.'s Digital Filter (Special Publication No. 30972/1983). These are explained below.

First, we will discuss the first one (IEEE Trans.ASSP-22). The sample value Z _i in Equation (3) is expressed as a binary number when handled digitally, but since it can take both positive and negative numbers (it can take both positive and negative numbers), it can be expressed as a binary number that includes positive and negative numbers. It is represented by the complement code of That is, Z _i is a two's complement code sample value. Using this representation method, the size of Z _i whose data word length is expressed in M bits is as follows (to simplify the explanation, we will consider only integers, but the following explanation will of course be based on decimal numbers). (applicable as well).

Z _i =−Z ^M _i 2 ^M-1 + _M-1 〓 ^j=1 Z ^j _i 2 ^j-1 ...(4) However, Z ^j _i is 0 or 1. From equation (4), we can see that when Z ^M _i is 0, Z _i is a positive number, and when Z ^M _i is 1, Z _i is a negative number, so Z ^M _i is a bit that represents polarity. I understand.

Substituting equation (4) into equation (3), Y= _N-1 〓 ⁱ⁼⁰ α _i (−Z ^M _i 2 ^M-1 + _M-1 〓 ^j=0 Z ^j _i 2 ^j-1 ) =− 2 ^M-1 _N-1 〓 ⁱ⁼⁰ α _i Z ^M _i + _M-1 〓 ^j=0 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i Z ^j _i ...(5), so the number If we define table output ^j and function as ^j △ = (Z ^j ₀ , Z ^j ₁ , ..., Z ^j _N-1 )△ == _N-1 〓 ⁱ⁼⁰ α _i Z ^j _i ...(6) , Equation (5) is Y=-(Z ^M ₀ , Z ^M ₁ , ..., Z ^M _N-1 )2 ^M-1 + _M-1 〓 ^j=0 (Z ^j ₀ , Z ^j ₁ , ... , Z ^j _N-1 ) 2 ^j-1 = − ^M 2 ^M-1 + _N-1 〓 ^{i=0 j} 2 ^j-1 ……(7).

The function of equation (6) is the N variables Z ^j ₀ , Z ^j ₁ ,...
..., Z ^j _N-1 can take on 2 ^N values depending on whether each of them is 0 or 1. Therefore, ^j in equation (6) is N variables.
A set of Z ^j ₀ , Z ^j ₁ , ..., Z ^j _N-1 , that is, an N-dimensional vector (Z ^j ₀ , Z ^j ₁ , ..., Z ^j _N-1 ) as an address value, 2 ^N read-only memory ROM or random access memory in which the value of is stored
It can be extracted from storage devices such as RAM. Therefore, the operation of sequentially shifting and adding ^j extracted in this way from equation (7) is repeated (M-1) times, and at the Mth time, the filter output Y is obtained by shifting and subtracting the extracted ^M. Understand what is required. A configuration based on this method is shown in FIG. In Figure 1, N=5 in equation (3), α _i =a _i (i=0, 1,
2), α ₃ = b ₁ and α ₄ = b ₂ , and Z _i =x _o-1 (i=
0, 1, 2), Z ₃ = y _o-1 , Z ₄ = y _o-2 and Y = y _o
y _o = a ₀ x _o + a ₁ x _o-1 + a ₂ x _o-2 + b ₁ y _o-1 + b ₂ y _o-2
...(8) shows the configuration of a second-order cyclic digital filter. At this time, the function ^j and from equation (6) ^{are j} = (x ^j _o , x ^j _o-1 , x ^j _o-2 , y ^j _o-1 , y ^j _o-2 ) = a ₀ x ^j
_o +a ₁ x ^j _o-1 +a ₂ x ^j _o-2 +b ₁ y ^j _o-1 +b ₂ y ^j _o-2 ...(9), and the filter output y _o is y _o = from equation (7). − ^M 2 ^M-1 + _M-1 〓 ^{j=0 j} 2 ^j-1 ……(10).

In Figure 1, SR1 to SR3 are serial type shift registers, PSR is a parallel input-serial output type shift register, R1 and R2 are registers, and MEM1
is a storage device such as ROM or RAM, ADS is an adder capable of subtraction, and ACC1 consists of ADS and R2, and the output line of R2 is shifted by one bit toward the lower bit and connected to one input of ADS, that is, R2 The lower bit of ADS is an accumulator connected to the lower first bit of ADS, and is configured as shown in the figure. In the figure, each bit of the sample value _xo is sequentially applied to the shift register SR1 in series starting from the least significant bit.

At the same time, each bit of x _o-1 is sequentially moved from the least significant bit to shift register SR1 to SR2, and each bit of x _o-2 is sequentially output from SR2. Each bit of x _o , x _o-1 and x _o-2 is applied sequentially to storage device MEM1.

Similarly, each bit of y _o-1 stored in shift register PSR in parallel is sequentially stored in shift register SR.
3, and each bit of y _o-2 comes out sequentially from SR3.

Each bit of y _o-1 and y _o-2 is sequentially applied to storage device MEM1. Therefore, the storage device MEM1 is provided with 5-bit information x ^j _o , x ^j _o-1 , x ^j _o-2 , y ^j _o-1 , y ^j _o-2 .

As shown in Figure 1, the storage device MEM1 is
It has 32 memory locations with bits as address values,
In each of them, the value pre-calculated by equation (9) is stored as data in a B-bit two's complement code.

Therefore, ^j can be extracted by the given five-dimensional vector (x ^j _o , x ^j _o-1 , x ^j _o-2 , y ^j _o-1 , y ^j _o-2 ), which is stored in register R1. is accumulated in Next, the output of register R1 is given to adder ADS in accumulator ACC1, and the partial sum Ψ ^j = _j-1 〓 ^{i=1 j} 2 ^j-1 (before adder ADS) stored in register R2 is (this operation is called shift addition).

Next, new vectors (x ^j+1 _o , x ^j+1 _o-1 , x ^j+1 _o-2 , y ^j+1 _o-1 , y ^j+1 _o-2 ) are given to the storage device MEM1. and the corresponding ^j+1 is extracted.

This again passes through register R1 to adder ADS
Then, the partial sum _j stored in register R2 〓 ^{j=1 j}
2 is shifted and added to ^j-1 .

This operation is repeated (M-1) times, and at the Mth time, the partial sum _M-1 〓 ^j= obtained by performing (M-1) shifts and 1) times shift addition stored in register R2 ^{1 j} 2 ^j-1 shifted by 1 bit is extracted from the storage device MEM1 by the vector (x ^M _o , x ^M _o-1 , x ^M _o-2 , y ^M _o-1 , y ^M _o-2 ). By subtracting ^M from the adder ADS through the register R1, Y _o in equation (10) can be obtained.

Although this example has a simpler circuit configuration and faster calculation time than the method using a binary multiplier described above, the circuit configuration and control are still complex because the adder must also be capable of subtraction. It has the disadvantage of being.

For this reason, the second conventional example (Special Publication No. 53-30972)
We will explain how to obtain the filter output using only addition.

The sample value Z _i is expressed as a binary number in the form Z _i = _M 〓 ^j=1 Z ^j _i 2 ^j-1 (11). However, Z ^j _i is 0
or 1.

Substituting equation (11) into equation (3), Y= _N-1 〓 ⁱ⁼⁰ α _iM 〓 ^j=1 Z ^j _i 2 ^j-1 = _M 〓 ^j=1 2 ^j-1 _N-1 〓 ^{j= 0} α _i Z ^j _i ...(12) Therefore, if the function ^j and are defined by equation (6), equation (12) becomes Y= _M 〓 ^j=1 (Z ^j ₀ , Z ^j ₁ , ..., Z ^j _o-1 ) 2 ^j-1 = _M 〓 ^{j=1 j} 2 ^j-1 ...(13), which includes only addition and does not include subtraction. Therefore, equation (13) shows that the filter output Y can be obtained by sequentially shifting and adding the extracted ^j value M times.

In this example, since there is no need to include subtraction in the adder, the circuit configuration and control are also simplified. However, in order for this example to operate as a filter, (I) As is clear from equation (11), Z _i must be non-negative (positive or zero) (restrictions are imposed on the signals that can be used) ( ) In the case of an acyclic filter, Z _i is only the input sample value, so it is sufficient if the input sample value is non-negative, but in the case of a cyclic filter, Z _i includes not only the input sample value but also the output sample value. from
The only requirement is that Z _i must be non-negative and Y must also be non-negative, that is, α _i must be such that the impulse response is non-negative; in other cases, the filter operation is impossible. Therefore, this example is applicable only in extremely limited cases. Further, a desirable requirement for a practical filter is that the digital signal (sample value) is a signal that can take on both positive and negative numbers (both positive and negative signs) similarly to analog signals. Filtering only positive signals also increases the overflow of the filter output.

The object of the present invention is to improve the drawbacks of the above-mentioned prior art, and to be usable for signals of both positive and negative signs.
Another object of the present invention is to provide a digital filter that performs only addition operations.

The most basic feature of the present invention is that the first term representing subtraction on the right side of the second equation of equation (5) is the variable Z ^M ₀ , Z ^M ₁ ,
..., by focusing on the fact that it is a function of Z ^M _N-1 , converting the first term into a constant, storing the constant in the storage device, and drawing it out, the filter output Y can be calculated using only addition. This is what I asked for. The present invention will be explained in detail below.

Since the sample value Z _i is a signal with both positive and negative signs, it can be expressed using the two's complement code mentioned above. From equation (4), Z _i = −Z ^M _i 2 ^M-1 + _M-1 〓 ^j=1 Z ^j _i 2 ^{j -1} ...(4). As mentioned above, substituting equation (4) into equation (3) yields equation
(5) is derived.

Y=−2 ^M-1 _N-1 〓 ⁱ⁼⁰ α _i Z ^M _i + _M-1 〓 ^j=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i Z ^j _i ……(5) By the way, What should be noted is that Z ^M _j + ^j _i =1 (14) holds true. However, ^j _i is Z ^j _i
represents the negation of That is, when Z ^j _i =0, ^j _i =1
and when Z ^j _i =1, ^j _i =0.

According to equation (14), Z ^j _i =1− ^j _i , so substitute it into the second term of equation (5) and get _M-1 〓 ^j=1 2 ^j-1 = 1/2 ( _M-1 〓 Using the relationship ^j=1 2 ^j-1 −1), Y=−2 ^M-1 _N-1 〓 ⁱ⁼⁰ α _i Z ^M _i + _M-1 〓 ⁱ⁼¹ 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i (1− ^j _i )=1/2 ( _M 〓 ^j=1 2 ^j-1 −1) _M 〓 ^j=0 α _i − _N-1 〓 ⁱ⁼⁰ 2 ^ji _N-1 〓 ^{i =0} α _i ^j _i =−1/2 _N-1 〓 ⁱ⁼⁰ α _i + _M 〓 ^j=0 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i (1/2− ^j _i ) ……( 15) becomes. However, it is defined as Z ^M _i △ = ^M _i ……(16). Equation (16) shows that the polarity bit of Z _i expressed in two's complement code is formally regarded as inverted Z ^M _i .

Therefore, the function ^j _I , ₁ and the definition ⁰ _I are respectively ^j _I △ = ₁ ( ^j ₀ ^j ₁ , ... ^j _N-1 ) _N-1 〓 ⁱ⁼⁰ △ = α _i (1/2 − ^j _i )
...(17) ⁰ _I △ = - _N-1 〓 ⁱ⁼⁰ α _i =2 ₁ (1, 1, ..., 1) ...(18) Then, equation (15) becomes Y= ⁰ _I 2 ^-1 + _M 〓 ^{j=1=0 j} _I 2 ^j-1 = _M 〓 ^{j=0 j} _I 2 ^j-1 ……(19).

Furthermore, equation (19) is Y=[ ^M _I + [ ^M-1 _I +...+[ ^j _I +...+2 ^-2 { ²
_I + ( ^I ₁ + ⁰ _I 2 ^-1 ) 2 ^-1 }2 ^-1 ……〕2 ^-1 ……〕2 ^-1 〕2 ^M
-1 ……(20) is also expressed. Here, the partial sum Ψ ^j is Ψ ^j △ Ψ ^j △ = ^j _I + [ ^j-1 _I +……+{ ² _I + ( ¹ ₁ + ⁰ _I 2 ^-1 )2
^-1 }2 ^-1 ...]2 ^-1 ...(21) If we define Ψ ^j = ^j _I +Ψ ^j-1 2 ^-1 ...(22) holds. However, Ψ ⁰ △ = ⁰ _I.

From equation (21), equation (20) can be expressed as Y=Ψ ^M 2 ^M-1 (23).

In addition, instead of equation (14), using the identity Z ^M _i + ^M _i =1 ...(14') and substituting Z ^M _i =1−Z ^M _i into equation (5), equation (15) is obtained. is Y=−1/2 _N-1 〓 ⁱ⁼⁰ α _i + _M 〓 ^j=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i (Z ^j _i −1/2) ……(15′) Changes to However, it is defined as Z ^M _i △ = ^M _i ……(16′). At this time, ^j ₁ △ = ₁ ( ^j ₀ , ^j ₁ , ..., ^j _N-1 ) _N-1 〓 ⁱ⁼⁰ △ = α _i (Z ^j _i −1/2) ...(17) ⁰ _I △ = − _N-1 〓 ⁱ⁼⁰ α _i =2 ₁ (1, 1, ..., 1) ...(18) Then, equation (16') and equation (15') are respectively ^M _i △ = ^M _i =Z ^M _i ……(16) Y= ⁰ _I 2 ^-1 + _M 〓 ^{j=1 j} _I 2 ^j-1 = _M 〓 ^{j=1 j} _I 2 ^j-1 ……(19), and the above are exactly the same as equations (16) and (19). Therefore, in this case as well, the first and second embodiments described below are the same.

The present invention provides formulas (16), (17) {(17′)}, (18),
(19) or equations (16), (17) {(17′)}, (18),
Based on the calculation principles of (22) and (23), the following structure is the gist.

That is, the sample value _i in which all bits except the polarity bit of the M-bit two's complement code sample value Z _i have been inverted = ^M _i ^M-1 _i ... ² _i ¹ _i is divided into N pieces (
i=
0, 1, ..., N-1) and generate an N-dimensional vector ( ^j ₀ , ^j ₁ ..., ^j _N-1 ). Equipped with a storage device that stores the value of ₁ , first generates an N-dimensional vector (1, 1, ..., 1), and then outputs the vector (1, 1, ..., 1) from the storage device as an address value. Pull out ₁ (1, 1, ..., 1) (= ⁰ ₁ /2) and add it to the shift adder (accumulator). Next, an N-dimensional vector ( ^j ₀ , ^j ₁ , ..., ^j _N-1 ) is obtained from the storage device.
As the address value, ¹ _I is extracted and added to the unshifted ⁰ _I /2 in the accumulator. Furthermore, ² ₁ is extracted from the storage device using the vector ( ² ₀ , ² ₁ , . . . , ² _N-1 ) as an address value, and the accumulator shifts and adds it to the previous accumulation result. This behavior is represented by a vector ( ^M ₀ ,
Z ^M ₁ , . . . , ^M _N-1 ), the filter output Y according to equation (19) or equation (23) is obtained.

In other words, it is possible to realize a device configuration that obtains the filter output Y for the original sample value Z _i of both positive and negative signs by performing only addition operations.

Next, the present invention will be specifically described with reference to embodiments shown in the drawings. It should be noted that both the embodiments shown in FIGS. 2 and 3 are configured for the second-order cyclic digital filter expressed by equation (8), as in the case of FIG. 1 for simplicity and comparison. It is something.

At this time, the functions ^j _I and ₁ are ^j ₁ = ₁ (jo, ^j _{o -1} , ^j _o-2 , ^j _o- 1, ^j _o-2 ) = a ₀ ⁽ 1/2- ^j _o )+a ₁ (1/2− ^j _o-1 )+a ₁ (
1/2- ^j _o-2 ) + b ₁ (1/2- ^j _o-1 ) + b ₂ (1/2
− ^j _o-2 )……(24), and the constant ⁰ ₁ is ⁰ ₁ = −(a ₀ +a ₁ +a ₂ +b ₁ +b ₂ )=2 ₁ (1, 1, 1
, 1, 1)...(25). Equation (19) and Equation (23) are equivalent, so for convenience of explanation of operation, Equation (23) is used to calculate the filter output.
y _o becomes y _o = Ψ ^M 2 ^M-1 ...(26).

The first embodiment will be explained with reference to FIG.

In Figure 2, EOR1 and EOR2 are exclusive OR, SR1 to SR3 are serial shift registers,
PSR is a parallel input-serial output type shift register.
OR1 to OR5 are logical sums, MEM2 is a storage device such as ROM or RAM, R1 register, PPR is a shift register with parallel input and parallel output, AD is an adder, and ACC2 is an accumulator consisting of AD and PPR. It is configured as shown. In FIG. 2, each bit of the sample value _xo is first applied to EOR1 in series starting from the least significant bit. here
EOR1 sets the signal _LM to high level, inverts all bits except the polarity bit, and supplies it as _o to the shift register SR1. At the same time, each bit of the input sample value _o-2 delayed by one sample time is sequentially moved from shift register SR1 to SR2, and from SR2, each bit of the input sample value _o-2 delayed by two sample times is sequentially transferred. come out.
Each bit of x _o , _o-1 and _o-2 is sequentially applied to the storage device MEM2 through logical sums OR1 to OR3. Similarly, from shift register PSR, 1
Each bit of the output sample value y _o-1 delayed by the sample time is sent out in series, and the EOR is applied as before.
At 2, all bits except the polarity bit are inverted and applied as _o-1 to shift register SR3. Each bit of the output sample value _o-2 delayed by two sample times is sequentially output from SR3. _o-1
Each bit of and _o-2 is sequentially ORed
4 and OR5 to storage device MEM2. Therefore, the storage device ^MEM2 is provided with 5-bit information ^jo , _{jo -1} , ^jo _-2 , ^jo _-1 , ^jo _-2 . As shown in FIG. 2, the storage device MEM2 has 32 storage locations with the above 5 bits as address values, and each of them has a value of ₁ calculated in advance by equation (24) as data in the B bits. It is stored in two's complement code. Therefore, first, the signal
Set H ₀ to high level, generate a 5-dimensional vector (1, 1, 1, 1, 1) from the logical sums OR1 to OR5, and use the vector (1, 1, 1, 1, 1) as an address value to store the storage device MEM2. from ₁ (1, 1, 1,
1, 1) (= ⁰ ₁ /2) is drawn out and register R1
is accumulated in The output of register R1 is an accumulator
It is applied to the adder AD in the ACC2, and is added to the contents (zero) of the shift register PPR which has been set to the initial state, and the addition result ⁰ ₁ /2 is stored in the shift register PPR as an initial accumulation value. Next, _the five- _dimensional vector ( ¹ _o , ¹ _o-1 , ¹ _o-2 , ¹ _o-1 ,
¹ _o-2 )
¹ ₁ is taken out from the storage device MEM2 as an address value and applied to the adder AD through the register R1. ¹ ₁ in the adder AD is a shift register that makes the signal L ₁ low and does not shift.
It is added to the contents of PPR (initial value ⁰ ₁ /2), and the partial sum Ψ ¹ is stored in the shift register PPR. Furthermore, the vector obtained in the same way as above ( ² _o ,
x ² _o-1 , ² _o-2 , ² _o-1 , ² _o-2 ) is taken out from storage device MEM2 as address value and ² ₁ is stored in register R1.
The partial sum Ψ 1 is added to the contents of the shift register PPR (Ψ ¹ 2 ^-1 ) shifted by 1 bit from the previous partial sum Ψ ¹ , and the resulting partial sum Ψ ² is stored in the shift register PPR. be done. This behavior is expressed as a vector ( ^M-1 _o , ^M-1 _o-1 , ^M-1 _o-2 , ^M-1 _o
-1 ,
y ^M-1 _o-2 ), we obtain the partial sum Ψ ^M-1 , and finally we obtain the vector whose components are the uninverted polarity bits themselves ( ^M _o , ^M _o-1 , ^j _o-2 , ^M _{o -1} , ^M _o-2 )
By performing the above operation for Ψ ^M , that is, the filter output value y _o of equation (26) is obtained.

Next, a second embodiment will be explained with reference to FIG.

Figure 3 is almost the same as Figure 2, but the difference is that the shift register PPR in Figure 2 is replaced with a register R2 instead of the accumulator ACC2, and the An accumulator ACC3 connected in the same way as the accumulator ACC1 shown in the figure is provided, and a signal switching circuit MPX connected thereto is further provided. Note that the output line of the storage device MEM2 is shifted by one bit and connected to one input of MPX.

Regarding the operation in FIG. 3, only the points different from those in FIG. 2 will be explained. Initial value of accumulation
⁰ ₁ /2 is stored in the shift register PPR through the adder AD in FIG.
In the figure, by setting the signal _H0 to high level, the register R is directly passed through the signal switching circuit MPX.
By storing in 2, the addition is reduced by one.

In the second embodiment, it is also possible to provide a separate storage device for storing the initial values ⁰ _{to 1} .
In addition, the signal switching circuit can also be configured to replace register R2 with a parallel input-parallel output type shift register.
A configuration in which one input of MPX is connected to the output of register R1 is also possible.

In the first and second embodiments, the order of the components of the five-dimensional vector used as the address value to the storage device may be arbitrary. Accordingly, the contents of the storage device are made to correspond.

Also, 5-bit information ^j _o , ^j _o-1 , ^j _o-2 , ^j _o-1
,
Of course, other means for generating y ^j _o-2 and the vector (1, 1, 1, 1, 1), operations for obtaining constant values (initial values), and configurations of the accumulator are conceivable. A configuration in which the register R1 is omitted is also possible.

Furthermore, the address value is a five-dimensional vector ( ^j _o ,
x ^j _o-1 , ^j _o-2 , ^j _o-1 , ^j _o-2 ),
Generally 5 bits of information ^j _o , ^j _o-1 , ^j _o-2 , ^j _o-1
,
Function of y ^j _o-2 ( ^j _o , ^j _o-1 , ^j _o-2 , ^j _o-1 , ^j _o-2
It can also be determined as an address value determined by
Accordingly, the contents of the storage device are made to correspond.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a conventional digital filter using a subtractable adder, FIG. 2 is a diagram showing an embodiment of the present invention having a configuration that can be compared with the conventional example in FIG. The figure shows another embodiment of the invention. ADS: subtractable adder, AD: adder,
MEM1, MEM2: Storage device, SR1~SR3:
Serial type shift register, PSR: Parallel input - Serial output type shift register, PPR: Parallel input -
Serial output type shift register, R1, R2: Register, EOR1, EOR2: Exclusive OR, OR1~
OR5: Logical sum, MPX: Signal switching circuit, ACC1
~ACC3: Indicates an accumulator.

Claims (1)

[Claims] 1. Filter the M-bit binary code sample value Z _i containing N positive and negative values successively arriving, Y= _N-1 〓 ⁱ⁼⁰ α _i Z _i (where Z _i = −Z ^M _i 2 ^M-1 + _M-1 〓 ^j=1 Z ^j _i 2 ^j-1 ) receiving the binary code sample value at a digital filter outputting a filter output Y expressed by the function; Inverting means for selectively inverting bits other than bits indicating polarity; Vector generating means for sequentially outputting N bit information corresponding to each bit of the N inverted binary code sample values; Coefficient α _i and the N bits; A storage device that stores a function φ ( ^j ₀ , ^j ₁ , ..., ^j _N-1 ) = ^j = _N-1 〓 ⁱ⁼⁰ α _i (Z ^j _i -1/2) determined by bit information; Receive the output ^j of the storage device and, prior to the arrival of the N-bit information, Ψ ⁰ = (1, 1, ..., 1), at j = 1, Ψ ¹ = ¹ +Ψ ⁰ , then Ψ ^j = ^j +Ψ ^j- an accumulator that calculates ¹ 2 ^-1 ; generates a predetermined advice before the arrival of the N bit;
A digital filter comprising: address generating means for generating an address storing a function corresponding to bit information.