JPS642245B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital filter, and more particularly, it sequentially reads numerical table outputs from an accumulator using vectors corresponding to each bit of a sample value, and accumulates the values. This invention relates to a digital filter that obtains a filter output by calculation.

According to theory, in general, in a digital filter, when the input sequence is a discrete signal (sample value) x(nT) obtained by sampling a continuous signal x(t) at an interval of T (seconds), The output series y(nT) is y(nT)= _K 〓 ^K=0 a _k x{(n-k)T}+ _L 〓 ^l=1 b _l y{(n-l)T}...(1) It is determined from a constant coefficient linear difference equation and is also a sample value.

Equation (1) represents a cyclic digital filter when at least one b _l is non-zero, and all b _l
When is zero, it represents an acyclic digital filter. For convenience, equation (1) is written as y _o = _K 〓 ^K=1 a _k x _ok + _L 〓 ^l=1 b _l y _ol (2).

However, x _ok △ = x {(n-k)T} (k=0, 1,
..., K), y _ol △ = y {(n-l)T} (l = 0, 1,
..., L). Furthermore, equation (2) can be formally expressed as Y= _N-1 〓 ⁱ⁼⁰ α _i Z _i (3). However, Y=y _o , α _i is a _k or
b _l and Z _i represent x _ok or y _ol , respectively.

If the expression (3) is used as is, N multiplications and (N-1) additions must be performed to obtain the filter output Y at one sampling point.

When handling digitally, since these multiplications and additions are binary operations, it takes time to obtain the output Y, and the circuit configuration becomes very complicated because a multiplier must be provided.

One of the features of digital filters is that one piece of hardware can equivalently operate as a plurality of (R) filters, that is, so-called time division multiplexing is possible. In order to operate as R filters, the multiplication and addition must be completed within the time T/R, but in reality, the multiplicity R cannot be increased because the calculation time is long. Also, a simple substance (R=
Even when used as a filter in 1), the sampling period T cannot be made small due to the long computation time, so the frequency that can be handled cannot be made high. For this reason, 2
There are several known methods to obtain the filter output of equation (3) without using a base multiplier, and Peled, A.
and Liu, B.: “A new hardware realization.
of digital filters”, IEEE Trans. Acoust.
Speech & Signal Process., ASSP-22, 6.
p.456 (1974) and Alan. This is described in Croisier et al.'s Digital Filter (Special Publication No. 53-30972). These are explained below.

First, the first one (IEEE Trans.ASSP-22)
Let's talk about. The sample value Z _i in equation (3) is expressed as a binary number when handled digitally, but since it can take both positive and negative numbers (it can take both positive and negative numbers), there is a method of representing binary numbers that includes positive and negative numbers, so-called It is expressed in two's complement code. That is, Z _i is a two's complement code sample value. Using this representation method, the size of Z _i whose data word length is expressed in M bits is as follows (to simplify the explanation, we will consider only integers, but the following explanation will of course be based on decimal numbers). (applicable as well).

Z _i =−Z _i ^M 2 ^M-1 + _M-1 〓 ^j=1 Z _i ^j 2 ^j-1 (4) However, Z _i ^j is 0 or 1. From equation (4), Z _i ^M
When Z i is 0, Z _i is a positive number, and when Z _i ^M is 1, Z _i
Since it can be seen that is a negative number, it can be seen that Z _i ^M is a bit representing polarity.

Substituting equation (4) into equation (3), Y= _N-1 〓 ⁱ⁼⁰ α _i (−Z _i ^M 2 ^M-1 + _M-1 〓 ^j=1 Z _i ^j 2 ^j-1 )=− 2 ^M-1 _N-1 〓 ⁱ⁼⁰ α _i Z _i ^M + _L 〓 ^l=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i Z _i ^j …(5) Therefore, the numerical table output ψ ^j and the function ψ are defined as ψ ^j △ = ψ (Z ₀ ^j , Z ₁ ^j , ..., Z _N-1 ^j )△ = _N-1 〓 ⁱ⁼⁰ α _i Z _i ^j ...(6), then Eq. (5) is Y=−ψ(Z ₀ ^M , Z ₁ ^M ,…, Z _N-1 ^M )2 ^M-1 + _M-1 〓 ^j=1 ψ(Z ₀ ^j , Z ₁ ^j ,…, Z _N-1 ^j ) 2 ^j-1 = −ψ ^M 2 ^M-1 + _M-1 〓 ^j=1 ψ ^j 2 ^j-1 …(7)

The function ψ of equation (6) is defined by its N variables Z ₀ ^j , Z ₁ ^j ,
..., Z _N-1 ^j can take on 2 ^N values depending on whether each j is 0 or 1. Therefore, the numerical table output ψ ^j of equation (6) is N
A set of variables Z ₀ ^j , Z ₁ ^j , ..., Z _N-1 ^j , that is, N
A read-only memory (ROM) or random access memory (RAM) in which 2 ^N values of the function ψ are stored using the dimensional vector (Z ₀ ^j , Z ₁ ^j , ..., Z _N-1 ^j ) as the address value. etc. can be withdrawn from storage devices such as Therefore, the operation of sequentially shifting and adding the numerical table output ψ ^j derived in this way from equation (7) is repeated (M-1) times, and at the Mth time, the derived numerical table output ψ ^M is shifted and subtracted. It can be seen that the filter output Y can be obtained by doing the following. A configuration based on this method is shown in FIG. Figure 1 shows that N in equation (3)
=5, α _i = a _i (i=0, 1, 2), α ₃ = b ₁ and α ₄ = b ₂ , and Z _i =X _oi (i=0, 1, 2), Z ₃ =
y _ol , Z ₄ = y _o-2 and Y = y _o obtained as y _o = a ₀ x _o + a ₁ x _o-1 + a ₂ x _o-2 + b ₁ y _o-1 + b ₂ y _o-2
...(8) shows the configuration of a second-order cyclic digital filter. At this time, the numerical table output ψ ^j and the function ψ are obtained from equation (6) as ψ ^j = ψ (x _o ^j , x _o-1 ^j , x _o-2 ^j , y _o-1 ^j , y _o-2 ^j ) = a ₀ x _o ^j
+a ₁ x _o-1 ^j +a ₂ x _o-2 ^j +b ₁ y _o-1 ^j +b ₂ y _o-2 ^j …(9), and the filter output y _o is obtained from equation (7) as y _o = −ψ ^M 2 ^M-1 + _M-1 〓 ^j=1 ψ ^j 2 ^j-1 …(10).

In Figure 1, SR1 to SR3 are serial type shift registers, PSR is a parallel input-serial output type shift register, R1 and R2 are registers, and MEM1
is a storage device such as ROM or RAM, ADS is an adder capable of subtraction, and ACC1 consists of ADS and R2, and the output line of R2 is shifted by one bit toward the lower bit and connected to one input of ADS. The second lower bit of ADS is connected to the first lower bit of ADS, which is an accumulator configured as shown in the figure.

In the figure, each bit of the sample value _xo is sequentially shifted into a shift register starting from the least significant bit.
Given to SR1. At the same time, each bit of x _o-1 is also sequentially transferred to the shift register starting from the least significant bit.
Move from SR1 to SR2, and from SR2 x _o-2
Each bit appears in sequence.

Each bit of x _o , x _o-1 and x _o-2 is applied sequentially to storage device MEM1.

Similarly, each bit of y _o-1 stored in shift register PSR in parallel is sequentially stored in shift register SR.
3, and each bit of y _o-2 comes out sequentially from SR3. Each bit of y _o-1 and y _o-2 is sequentially applied to storage device MEM1.

Therefore, the storage device MEM1 is provided with 5-bit information x _o ^j , x _o-1 ^j , x _o-2 ^j , y _o-1 ^j , y _o-2 ^j . As shown in FIG. 1, the storage device MEM1 has 32 storage locations with the above 5 bits as address values, and each of them has B bits of the value of the function ψ calculated in advance by equation (9) as data. It is stored in two's complement code.

Therefore, given a five-dimensional vector (x _o ^j ,
x _o-1 ^j , x _o-2 ^j , y _o-1 ^j , y _o-2 ^j ), a table output ψ ^j can be derived, which is stored in register R1. Next, the output of register R1 is the accumulator
Partial sum given to adder ADS in ACC1 and stored in register R2 Ψ ^j = _j-1 〓 ^j=1 ψ ^j 2 ^j-1 (this operation is called shift addition).

Next, the new vector (x _o ^j
+1 , x _o-1 ^j+1 , x _o-2 ^j+1 , y _o-1 ^j+1 , y _o-2 ^j+1 ) are given, and the corresponding ψ ^j+1 is extracted. . This is,
It is shifted and added to the partial sum _M-1 〓 ^j=1 ψ ^j 2 ^j-1 stored in the register R2 by the adder ADS through the register R1 again.

Repeat this operation (M-1) times, and at the Mth time, the partial sum _M-1 obtained by shifting and adding (M-1) times stored in register R2 〓 ^j=1 ψ ^j 2 ^{j -1} shifted by 1 bit, vector (x _o ^M , x _o-1 ^M ,
x _o-2 ^M , yo _-1 ^M , ^yo _-2 ^M y _o is required.

Although this example has a simpler circuit configuration and faster calculation time than the method using a binary multiplier described above, the circuit configuration and control are still complex because the adder must also be capable of subtraction. It has the disadvantage of being. Therefore, as a second conventional example (Japanese Patent Publication No. 53-30972), a method for obtaining the filter output only by addition will be described.

The sample value Z _i is expressed as a binary number in the form Z _i = _M 〓 ^j=1 Z _i ^j 2 ^j-1 (11). However, Z _i ^j is 0 or 1.

Substituting equation (11) into equation (3), Y= _N-1 〓 ⁱ⁼⁰ α _iM 〓 ^j=1 Z _i ^j 2 ^j-1 = _M 〓 ^j=1 2 ^j-1 _N-1 〓 ^{i= 0} α _i Z _i ^j …(12) Therefore, if the table output ψ ^j and the function ψ are defined by equation (6), equation (12) becomes Y= _M 〓 ^j=1 ψ (Z ₀ ^j , Z ₁ ^j , ..., Z _o-1 ^j )2 ^j-1 = _M 〓 ^j=1 ψ ^j 2 ^j-1 ...(13) It is expressed as follows, and only addition does not include subtraction. Therefore, equation (13) indicates that the filter output Y can be obtained by sequentially shifting and adding the numerical output ψ ^j M times.

In this example, since there is no need to include subtraction in the adder, the circuit configuration and control are also simplified. However, in order for this example to operate as a filter, (1) Z _i must be non-negative (positive or zero) as is clear from equation (11) (restrictions are imposed on the signals that can be used) (2) In the case of an acyclic filter, Z _i is only the input sample value, so it is sufficient if the input sample value is non-negative, but in the case of a cyclic filter, Z _i includes not only the input sample value but also the output sample value. Z _i
is non-negative and at the same time the filter output Y must be non-negative, that is, α _i such that the impulse response is non-negative is required; in other cases, the filter operation is impossible. . Therefore, this example is applicable only in extremely limited cases. Further, a desirable requirement for a practical filter is that the digital signal (sample value) is a signal that can take on both positive and negative numbers (both positive and negative signs) similarly to analog signals. Filtering only positive signals also increases the overflow of the filter output.

The object of the present invention is to improve the drawbacks of the above-mentioned prior art, and to be usable for signals of both positive and negative signs.
Another object of the present invention is to provide a digital filter that performs only addition operations.

The most basic feature of the present invention is that the first term representing subtraction on the right side of the second equation of equation (5) is a variable Z ₀ ^M ,
Focusing on the fact that Z ₁ ^M , ..., Z _N-1 ^M is a function, the first term is converted to a constant, and the constant is stored in the storage device and retrieved, so that the filter output can be calculated by adding only It is determined by calculation. The present invention will be explained in detail below.

Since the sample value Z _i is a signal with both positive and negative signs, if it is expressed using the two's complement code mentioned above, then from equation (4) Z _i = −Z _i ^M 2 ^M-1 + _M-1 〓 ^j=1 Z _i ^j 2 ^{j -1} ...(4). As mentioned above, substituting equation (4) into equation (3) yields equation
(5) is derived.

Y=−2 ^M-1 _N-1 〓 ⁱ⁼⁰ α _i Z _i ^M + _M-1 〓 ^j=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i Z _i ^j …(5) By the way, please note What should be done is to make sure that Z _i ^j + _i ^j =1 (14) holds true. However, _i ^j is Z _i
represents the negation of ^j .

That is, when Z _i ^j =0, _i ^j =1, and Z _i ^j =
1, _i ^j =0.

From equation (14), Z _i ^j =1- _i ^j , so substituting it into the second term of equation (5) yields Y=-2 ^M-1 _N-1 〓 ⁱ⁼⁰ α _i Z _i ^M + _{M- 1} 〓 ^j=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i (1− _i ^j )＝ _M-1 〓 ^j=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i − _M 〓 ^{j= 1} 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _{i i} ^j …(15) However, it is defined as _i ^M △ = Z _i ^M (16). Equation (16) shows that the polarity bit of Z _i expressed in two's complement code is formally regarded as its inverted _i ^M . Therefore, the functions ψ ₁ ^j , ψ ₁ and the constant ψ ₁ ^M+1 are respectively ψ ₁ ^j △ = ψ ₁ ( ₀ ^j , ₁ ^j , ..., _N-1 ^j ) △ = − _N-1 〓 ^{i= 0} α _{i i} ^j
…(17) ψ ₁ ^M+1 △ =2 ^-M _M-1 〓 ^j=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i =2 ^-M (2 ^M-1 −1) _N-1 〓 Defining ⁱ⁼⁰ α _i …(18), equation (15) becomes Y=ψ ₁ ^M+1 2 ^M + _M 〓 ^j=1 ψ ₁ ^j 2 ^j-1 = _M+1 〓 ^j=1 ψ ₁ ^j 2 ^j-1 …(19) becomes. By the way, equation (18) can be approximately expressed as ψ ₁ ^M+1 (1/2) _N-1 〓 ⁱ⁼⁰ α _i ...(18') when the word length M of Z _i is sufficiently large.

Furthermore, equation (19) is expressed as Y=[ψ ₁ ^M+1 +[ψ ₁ ^M +...+[ψ ₁ ^J +...+{ψ ₁ ³ + (ψ
₁ ² +ψ ₁ ¹ 2 ^-1 )2 ^-1 }2 ^-1 …〕2 ^-1 …〕2 ^-1 〕2 ^M …(20) It is also expressed as: Here, the partial sum Ψ ^j is Ψ ^j △ Ψ ^j △ = ψ ₁ ^j + [ψ ₁ ^j-1 +...+{ψ ₁ ³ + (ψ ₁ ² +ψ ₁ ¹ 2 ^-1 ｝2 ^-1
…]2 ^-1 …(21) If we define Ψ ^j = ψ ₁ ^j + Ψ ^j-1 2 ^-1 …(22) holds. However, it is assumed that Ψ ⁰ △ =0.

From equation (21), equation (20) is expressed as Y=Ψ ^M+1 2 ^M (23).

In addition, instead of equation (14), if we use the identity Z _i ^M + _i ^M = 1 ... (14') and substitute Z _i ^M = 1 - _i ^M into equation (5), equation (15) becomes Y =−2 ^M-1 _N-1 〓 ⁱ⁼⁰ α _i + _M 〓 ^j=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i Z _i ^j …(15′) However, it is defined as Z _i ^M △ = _i ^M …(16′). At this time, ψ ₁ ^j △ = ψ ₁ ( ₀ ^j , ₁ ^j , …, _o-1 ^j ) △ = − _N-1 〓 ⁱ⁼⁰ α _i Z _i ^j … (17′) ψ ₁ ^M+1 = A-(1/2) _N-1 〓 ⁱ⁼⁰ α _i (constant) …(18″) If defined, equations (16′) and (15′) are respectively Y=ψ ₁ ^M+1 2 ^M + _M 〓 ^j=1 ψ ₁ ^j 2 ^j-1 = _M+1 〓 ^j=1 ψ ₁ ^j 2 ^j-1 …(19), and the above equation (16) and It is exactly the same as equation (19). Therefore, in this case as well, the first and second embodiments described below are the same.

The present invention provides equations (16), (17) {(17')}, (18)
{(18″)}, (19) or equation (16), (17) {(17′
)},
Based on the operational principles of (18) {(18″)}, (22), and (23), the following structure is the gist.

That is, the sample values _i = _i ^M , _i ^M-1 , ..., _i ² , _i ¹ in which all bits except the polarity bit of the M-bit two's complement code sample value Z _i are inverted are divided into N pieces (i = 0
,
1,...,N-1) and prepare an N-dimensional vector ( ₀ ^j ,
Z ₁ ^j ,…, _N-1 ^j ). It is equipped with a storage device that stores the values of ψ ₁ and constant A, and extracts ψ ₁ ³ from this storage device using an N-dimensional vector ( ₀ ^j , ₁ ^j , ..., _N-1 ^j ) as an address value, and performs shift addition. Add to the accumulator.

After repeating this operation M times, the constant A is extracted from the storage device and added to the accumulator at the (M+1)th time.

In this way, the filter output Y according to equation (19) or equation (23) is obtained.

That is, the filter output Y for the original sample value Z _i of both positive and negative signs is determined by the operation of addition only.

Next, the present invention will be specifically described with reference to embodiments shown in the drawings. It should be noted that both the embodiments shown in FIGS. 2 and 3 are configured for the second-order cyclic digital filter expressed by equation (8), as in the case of FIG. 1 for simplicity and comparison. It's even.

At this time, the functions ψ ₁ ^j and ψ ₁ are calculated from equation (17) as ψ ₁ ^j = ψ ( _o ^j , _o-1 ^j , _o-2 ^j , _o-1 ^j , _o-2 ^j ) = − (a _{0 o} ^j +a _{1 o-1} ^j , a _{2 o-2} ^j +b _{1 o-1} ^j +b _{2 o-2} ^j ) ...(24), and the constant ψ ₁ ^M+1 is expressed by equation (18) or (18' ), ψ ₁ ^M+1 = A=2 ^-M (2 ^M-1 -1) (a ₀ +a ₁ +a ₂ +b ₁ +b
₂ ) (1/2) (a ₀ + a ₁ + a ₂ + b ₁ + b ₂ )...(25).

Since Equation (19) and Equation (23) are equivalent, for convenience of explanation of operation, using Equation (23) will reduce the filter output y _o
is y _o = Ψ ^M+1 2 ^M …(26).

The first embodiment will be explained with reference to FIG.

In Figure 2, EOR1 and EOR2 are exclusive OR, SR1 to SR3 are serial shift registers,
PSR is a parallel input-serial output type shift register.
NOT is negation, AND1~AND5 is logical product,
MEM2 is a storage device such as ROM or RAM, R
1, R2 is a register, AD is an adder, ACC2 is
It consists of AD and R2, and like ACC1, the output of R2 is shifted by 1 bit towards the lower bit.
is connected to the input of the accumulator, and is constructed as shown. In Figure 2, the sample value x _o
The bits of are serially arranged starting from the least significant bit.
A sample in which all bits except the polarity bit of xo are inverted by applying it to EOR1 and inverting all bits except the polarity bit by setting the signal _LM to high level at a time other than _the transit time of the polarity bit. It is given to the shift register SR1 as the value _o . At the same time, each bit of the input sample value _o-1 delayed by one sample time is sequentially transferred to the shift register.
Move from SR1 to SR2, and from SR2 to 2
Each bit of the input sample value _o-2 delayed by the sample time is output in sequence. Each bit of _o , _o-1 and _o-2 is logically AND1 to AND3, respectively.
through the storage device MEM2. Similarly, 1 is stored in the shift register PSR in parallel.
Each bit of the sample time-delayed output sample value y _o-1 is sequentially and serially passed through an exclusive OR EOR2 to invert all bits except the polarity bit as described above to determine the polarity of y _o-1 . The sample value _o-1 with all bits except bits inverted is moved to shift register SR3, and from SR3 it is transferred to shift register SR3.
Each bit of the sample time delayed output sample value _o-2 comes out in sequence. Each bit of _o-1 and _o-2 is sequentially logically AND4 and AND5, respectively.
through the storage device MEM2. Further, the signal H _M+1 is applied to the storage device MEM2, so that the storage device MEM2 is provided with 6-bit information. The storage device MEM2 stores six-dimensional vectors (1, 0, 0, 0, 0,
0), store the value of the constant A expressed by equation (25) as a B-bit two's complement code,
In the other 32 memory locations from address 0 to address 311, the value of ψ calculated in advance by equation (24) is stored in a B-bit two's complement code. ^{Therefore ,} _{a six - dimensional} ^vector ₍ ^_ _{_} ^_ 0, _o ^j , _o-1 ^j , _o-2 ^j ,
y _o-1 ^j , _o-2 ^j ) as the address value of the storage device MEM
φ ₁ ^j is extracted from 2 and stored in register R1.

Next, the output of the register R1 is given to the adder AD in the accumulator ACC2, and is shifted and added to the partial sum Ψ ^j-1 stored in the register R2 to obtain Ψ ^j .

Repeat this operation (M-1) times to obtain Ψ ^M-1
is calculated, and at the Mth time, the low level signal H _M+1 and the signal L _M are set to low level, and a vector (0, _o ^M , _o-1 ^M ,
Perform the above operation for X _o-2 ^M , _o-1 ^M , _o-2 ^M ) to obtain Ψ ^M , and at the (M+1)th time, set the signal H _M+1 to high level, and Logical AND is performed by the low level signal generated from NOT.
A vector (1, 0, 0,
0, 0, 0). The constant A is extracted from the storage device MEM2 as the address value of the vector, and is stored in the register R1.

Next, the output of the register R1 is given to the adder AD, where it is shifted and added to the partial sum Ψ ^M stored in the register R2, and Ψ ^M+1 , that is, the filter output Y _o of equation (26) is obtained. Also, vector (1, 0, 0, 0, 0, 0) as a predetermined address value.
A configuration that takes other vectors is also possible.

Next, a second embodiment will be explained with reference to FIG.

FIG. 3 is similar to FIG. 2, but the difference is that the NOT and AND1 to AND5 are removed, and instead of the storage device MEM2 in FIG. 2, storage devices MEM3 and MEM4 and multiplexers are used. The point is that a signal switching device MPX such as the above is provided. Regarding the operation in FIG. 3, only the points different from those in FIG. 2 will be explained.

In FIG. 3, a storage device MEM3 stores the contents of addresses 0 to ³¹ of the storage device _MEM2 in FIG. It is stored in the complement code of . Therefore, ψ ₁ ^j is extracted from the storage device MEM3 using the given five-dimensional vector ( _o ^j , _o-1 ^j , _o-2 ^j , _o-1 ^j , _o-2 ^j ) as an address value, and the signal is switched. It is stored in register R1 through device MPX.
Next, the output of register R1 is given to adder AD, and is shifted and added to the previous output Ψ ^j-1 of adder AD stored in register R2.

This operation is repeated (M-1) times, and at the M time, the signal L _M is set to low level, and a vector ( _o ^M , _o-1 ^M , _o-2
The above operation is performed for ^M , _o-1 ^M , _o-2 ^M ).
In this way, the signal H _M+1 is generated at the (M+1)th time, and ψ ₁ ^M+1 is drawn out from the storage device MEM4 through the signal switching device MPX according to the signal, and is stored in the register R1.

Next, the output of register R1 is given to adder AD, and the adder AD stored in register R2
is shifted and added to the previous output Ψ ^M to obtain the filter output y _o of equation (26).

Further, the register R1 may be inserted on the input side of the signal switching device MPX.

In the first and second embodiments, since ψ ₁ ^j for the zero vector is zero, it is also possible to configure so that addition is not performed for the zero vector, and in this case, the filter output y _o The calculation time for the calculation can be shortened. Also, accumulator ACC2
A configuration in which register R2 therein is replaced with a parallel input-parallel output type shift register or a configuration in which register R1 is omitted is also possible. The order of vector components used as address values to storage devices may be arbitrary. Accordingly, the contents of the storage device are made to correspond.

Also, 5-bit information _o ^j , _o-1 ^j , _o-2 ^j , _o-1
Naturally, other means for generating ^j , _o-2 ^j and operations for obtaining the constant value ψ ₁ ^M+1 can be considered.

In the first embodiment, the address value is determined by a six-dimensional vector (0, _o ^j , _o-1 j , o-2 ^j , _o-1 ^j , o-2 ^j ), and in the second embodiment, the address value is determined by a five-dimensional vector (0, o j , _o-1 ^j , _o-2 j , o-1 j , o-2 j ). Although it was defined as a vector ( _o ^j , _o-1 ^j , _o-2 ^j , _o-1 ^j , _o-2 ^j ), the address value generally consists of five pieces of information _o ^j ,
Functions of x _o-1 ^j , _o-2 ^j , _o-1 ^j , _o-2 ^j ( _o ^j , _o-1 ^j
,
x _o-2 ^j , _o-1 ^j , _o-2 ^j ).

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a conventional digital filter using a subtractable adder, FIG. 2 is a diagram showing an embodiment of the present invention having a configuration that can be compared with the conventional example in FIG. The figure shows another embodiment of the invention. In the figure, ADS is a subtractable adder, AD is an adder, MEM1 to MEM4 are storage devices, and SR1 to
SR3 is a serial type shift register, PSR is a parallel input-serial output type shift register, R1 and R2 are registers, EOR1 and EOR2 are exclusive OR,
AND1 to AND5 represent logical products, MPX represents a signal switching device, and ACC1 and ACC2 represent accumulators, respectively.

Claims (1)

[Claims] 1. Filter the M-bit binary code sample value Z _i containing N positive and negative values successively arriving, Y= _N-1 〓 ⁱ⁼⁰ α _i Z _i (where Z _i = −Z _i ^M 2 ^M-1 + _M-1 〓 ^j=1 Z _i ^j 2 ^j-1 ) In a digital filter that outputs a filter output Y expressed by a function, the binary code sample value is received. , an inverting means for selectively inverting bits other than the bits indicating polarity;
vector generating means for sequentially outputting N-bit information _{corresponding} to each bit of the inverted binary code sample values; an accumulating device that accumulates a function ψ determined by the information; an accumulating device that receives the output ψ ^j of the accumulating device and calculates Ψ ^j = ψ ^J + Ψ ^j-1 2 ^-1 ; and an address generating means that generates an address storing a function ψ corresponding to the N-bit information M times when 1≦j≦M, and generates the predetermined address at the M+1 time. Features a digital filter.