JPS6351415B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital filter, and more particularly, it sequentially reads numerical table outputs from an accumulator using vectors corresponding to each bit of a sample value, and accumulates the values. This invention relates to a digital filter that obtains a filter output by calculation.

According to theory, in general, in a digital filter, when the input sequence is a discrete signal (sample value) x(nT) obtained by sampling a continuous signal x(t) at an interval of T (seconds), the output The series y(nT) is y(nT)= _k 〓 ^k=0 a _k x {(n-k)T}+ _L 〓 ^l=0 b _l y{(n-l)T} ...(1) It is determined from a constant coefficient linear difference equation and is also a sample value. Equation (1) represents a cyclic digital filter when at least one b _l is not zero, and represents an acyclic digital filter when all b _l are zero. For convenience, equation (1) is written as y _o = _k 〓 ^k=0 a _k x _ok + _L 〓 ^l=0 b _l y _ol ……(2). However, x _ok △ = x {(n-k)T}
(k=0, 1, ..., K), y _ol △ = y {(n-l)
T} (l=0, 1, ..., L). Furthermore, formula (2) can be formally expressed as Y= _N-1 〓 ⁱ⁼⁰ α _i Z _i ...(3). However, Y=y _o , α _i is a _k or
b _l and Z _i represent x _ok or y _ol , respectively.

If the expression (3) is used as is, N multiplications and (N-1) additions must be performed to obtain the filter output value Y at one sampling point. When handling digitally, since these multiplications and additions are binary operations, it takes time to obtain the output Y, and the circuit configuration becomes very complicated because a multiplier must be provided.

One of the features of digital filters is that so-called time division multiplexing is possible, in which one piece of hardware can equivalently operate as a plurality (R) of filters. In order to operate as R filters, the multiplication and addition must be completed within the time T/R, but in reality, the multiplicity R cannot be increased because the calculation time is long. Also, a simple substance (R=
Even when used as a filter in 1), the sampling period T cannot be made small due to the long computation time, so the frequency that can be handled cannot be made high.

For this reason, there are several known methods to obtain the filter output value of equation (3) without using a binary multiplier. Peled, A. and Liu, B.: “A new
“hardware realization of digital filters”
IEEE Trans. Acoust., Speech & Signal
Process., ASSP-22, 6, p. 456 (1974) and Digital Filter by Alain Croisier et al.

These are explained below.

First, the first one (IEEE Trans.ASSP-22)
Let's talk about. The sample value Z _i in Equation (3) is expressed as a binary number when handled digitally, but since it can take both positive and negative numbers (it can take both positive and negative numbers), it can be expressed as a binary number that includes positive and negative numbers. It is represented by the complement code of That is, Z _i is a two's complement code sample value.

Using this representation method, the size of Z _i whose data word length is expressed in M bits is as follows (to simplify the explanation, we will consider only integers, but the following explanation will of course be based on decimal numbers). (applicable as well).

Z _i =−Z ^M _i 2 ^M-1 + _M-1 〓 ^j=0 Z ^j _i 2 ^j-1 ...(4) However, Z ^j _i is 0 or 1. From equation (4), we can see that when Z ^M _i is 0, Z _i is a positive number, and when Z ^M _i is 1, Z _i is a negative number, so Z ^M _i is a bit that represents polarity. I understand.

Substituting equation (4) into equation (3), Y= _N-1 〓 ⁱ⁼⁰ α _i (−Z ^M _i 2 ^M-1 + _M-1 〓 ^j=1 Z ^j _i 2 ^j-1 ) =− 2 ^M-1 _N-1 〓 ⁱ⁼⁰ α _i Z ^M _i + _M-1 〓 ^j=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i Z ^j _i ...(5), so the number The table output φ ^j and the function φ are φ ^j △ = φ (Z ^j ₀ , Z ^j ₁ , ..., Z ^j _N-1 ) △ = _N-1 〓 ⁱ⁼⁰ α _i Z ^j _i ...(6) _If ^{defined as} _{_} ^_ _{_} ^_ _{_} ^{_ _} _{_} ^j ₁ , ..., Z ^j _N-1 )2 ^j-1 = -φ ^M 2 ^M-1 + _M-1 〓 ^j=0 φ ^j 2 ^j-1 ...(7).

The function φ in equation (6) is defined by its N variables Z ^j ₀ , Z ^j ₁ ,...
..., Z ^j _N-1 can take on 2 ^N values depending on whether each of them is 0 or 1. Therefore, φ ^j in equation (6) is N variables.
A set of Z ^j ₀ , Z ^j ₁ , ..., Z ^j _N-1 , that is, an N-dimensional vector (Z ^j ₀ , Z ^j ₁ , ..., Z ^j _N-1 ) as an address value, 2 ^N read-only memory ROM or random access memory in which the value of φ is stored
It can be extracted from storage devices such as RAM. Therefore, the operation of sequentially shifting and adding φ ^j extracted in this way from equation (7) is repeated (M-1) times, and at the Mth time, the filter output is obtained by shifting and subtracting the extracted φ ^M. It can be seen that Y can be calculated. A configuration based on this method is shown in FIG. In Figure 1, N=5 in equation (3), α _i =a _i (i=0, 1,
2), α ₃ = b ₁ and α ₄ = b ₂ , and Z _i =x _o-1 (i=
0, 1, 2), Z ₃ = y _o-1 , Z ₄ = y _o-2 and Y = y _o
y _o = a ₀ x _o + a ₁ x _o-1 + a ₂ x _o-2 + b ₁ y _o-1 + b ₂ y _o-2
...(8) shows the configuration of a second-order cyclic digital filter. At this time, the functions φ ^j and φ are obtained from equation (6): φ ^j = φ (x ^j _o , x ^j _o-1 , x ^j _o-2 , y ^j _o-1 , y ^j _o-2 ) = a ₀ x ^j
_o +a ₁ x ^j _o-1 +a ₂ x ^j _o-2 +b ₁ y ^j _o-1 +b ₂ y ^j _o-2 ...(9), and the filter output y _o is y _o = from equation (7). −φ ^M 2 ^M-1 + _M-1 〓 ^j=1 φ ^j 2 ^j-1 ……(10).

In Figure 1, SR1 to SR3 are serial type shift registers, PSR is a parallel input-serial output type shift register, R1 and R2 are registers, and MEM1
is a storage device such as ROM or RAM, ADS is an adder capable of subtraction, and ACC1 consists of ADS and R2, and the output line of R2 is shifted by one bit toward the lower bit and connected to one input of ADS, that is, R2 The second lower bit of ADS is an accumulator connected to the first lower bit of ADS, and is constructed as shown in the figure. In the figure, the sample value x _o
The bits are sequentially applied to the shift register SR1 in series starting with the least significant bit. Also at the same time
Each bit of x _o-1 is also sequentially moved from the least significant bit to shift register SR1 to SR2,
Each bit of x _o-2 comes out sequentially from SR2. _xo ,
Each bit of x _o-1 and x _o-2 is sequentially applied to storage device MEM1. Similarly, each bit of yo _-1 stored in parallel in shift register PSR sequentially enters shift register SR3, and each bit of yo _-2 sequentially comes out from SR3. y _o-1 and
Each bit of y _o-2 is sequentially stored in the storage device MEM1.
given to. Therefore, the storage device MEM1 is provided with 5-bit information x ^j _o , x ^j _o-1 , x ^j _o-2 , y ^j _o-1 , y ^j _o-2 . As shown in Figure 1, the storage device MEM
1 has 32 memory locations with the above 5 bits as address values, and in each of these locations, the value of φ calculated in advance by equation (9) is stored as data in a B-bit two's complement code. . Therefore, the given 5
φ ^j can be extracted by the dimensional vector (x ^j _o , x ^j _o-1 , x ^j _o-2 , y ^j _o-1 , y ^j _o-2 ), which is stored in register R1.
is accumulated in Next, the output of register R1 is the accumulator
Provided to adder ADS in ACC1, register R
Partial sum Ψ ^j = _j-1 〓 ^j=1 φ ^j 2 ^j-1 (adder
(The previous output of ADS shifted by 1 bit) is added (this operation is called shift addition).

Next, new vectors (x ^j+1 _o , x ^j+1 _o-1 , x ^j+1 _o-2 , y ^j+1 _o-1 , y ^j+1 _o-2 ) are given to the storage device MEM1. φ ^j+1 corresponding to this is extracted. This is again passed through register R1 to adder ADS, register R2
It is shifted and added to the partial sum _j 〓 ^j=1 φ ^j 2 ^j-1 stored in . Repeat this operation (M-1) times, M
At the time, it is stored in register R2 (M-
1) From the partial sum _M-1 〓 ^j=1 φ ^j 2 ^j-1 obtained by shifting and adding 1) times, shifted by 1 bit, vector (x ^M _o ,
x ^M _o-1 , x ^M _o-2 , y ^M _o-1 , y ^M _o-2 )
By subtracting φ ^M drawn from 1 by the adder ADS through the register R1, y _o in equation (10) can be obtained.

Although this example has a simpler circuit configuration and faster calculation time than the method using a binary multiplier described above, the circuit configuration and control are still complex because the adder must also be capable of subtraction. It has the disadvantage of being.

For this reason, the second conventional example (Special Publication No. 53-30972)
There is a method to obtain the filter output only by addition. I will discuss it below.

The sample value Z _i is expressed as a binary number in the form Z _i = _M 〓 ^j=1 Z ^j _i 2 ^j-1 (11). However, Z ^j _i is 0
or 1.

Substituting equation (11) into equation (3), Y= _M-1 〓 ⁱ⁼⁰ α _iM 〓 ^j=1 Z ^j _i 2 ^j-1 = _M 〓 ^j=1 2 ^j-1 _N-1 〓 ^{i= 0} α _i Z ^{j i} _... (12) Therefore, if the functions φ ^j and φ are defined by equation (6), equation (12) becomes Y= _M 〓 ^j=1 φ(Z ^j ₀ , Z ^j ₁ , ..., Z ^j _o-1 )2 ^j-1 = _M 〓 ^j=1 φ ^j 2 ^j-1
...(13) It is expressed as ``addition only'' and does not include subtraction. Therefore, equation (13) indicates that the filter output Y can be obtained by sequentially shifting and adding the extracted φ ^j M times.

In this example, since there is no need to include subtraction in the adder, the circuit configuration and control are also simplified. However, in order for this example to operate as a filter, (I) Z _i must be non-negative (positive or zero) as is clear from equation (11) (restrictions are imposed on the signals that can be used) () Non-negative In the case of a cyclic filter, Z _i is only the input sample value, so it is sufficient if the input sample value is non-negative, but in the case of a cyclic filter, Z _i includes not only the input sample value but also the output sample value.
Z _i must be non-negative and Y must also be non-negative. In other words, the filter operation is limited to the necessity of α _i such that the impulse response is non-negative, and in other cases, the filter operation is impossible. Therefore, this example is applicable only in extremely limited cases. Further, a desirable requirement for a practical filter is that the digital signal (sample value) is a signal that can take on both positive and negative numbers (both positive and negative signs) similarly to analog signals. Filtering only positive signals also increases the overflow of the filter output.

An object of the present invention is to improve the drawbacks of the above-mentioned prior art, and to be usable for signals of both positive and negative signs.
Another object of the present invention is to provide a digital filter using only addition operations.

The most basic feature of the present invention is that the first term representing subtraction on the right side of the second equation of equation (5) is the variable Z ^j ₀ , Z ^j ₁ ,
..., by focusing on the fact that it is a function of Z ^j _N-1 , converting the first term into a constant, storing the constant in the storage device, and drawing it out, the filter output Y can be calculated using only addition. This is what I asked for. The present invention will be explained in detail below.

Since the sample value Z _i is a signal with both positive and negative signs, it can be expressed using the two's complement code mentioned above. From equation (4), Z _i = −Z ^M _i 2 ^M-1 + _M-1 〓 ^j=1 Z ^j _i 2 ^{j -1} ...(4). As mentioned above, substituting equation (4) into equation (3) yields equation
(5) is derived.

Y=−2 ^M-1 _N-1 〓 ⁱ⁼⁰ α _i Z ^M _i + _M-1 〓 ^j=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i Z ^j _i ……(5) By the way, What should be noted is that Z ^j _i + ^j _i =1 (14) holds true. However, ^j _i is Z ^j _i
represents the negation of That is, when Z ^j _i =0, ^j _i =1
and when Z ^j _i =1, ^j _i =0.

From equation (14), Z ^j _i =1− ^j _i , so substitute it into the second term of equation (5) and get _M-1 〓 ^j=1 2 ^j-1 = 1/2 ( _M 〓 ^j=0 2 ^j-1 −1) Using the relationship Y=−2 ^M-1 _N-1 〓 ⁱ⁼⁰ α _i Z ^M _i + _M-1 〓 ^j=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i (1− ^j _i )=1/2 ( _M 〓 ⁱ⁼⁰ 2 ^j-1 −1) _N-1 〓 ⁱ⁼⁰ α _i − _M 〓 ^j=1 2 ^ji _N-1 〓 ⁱ⁼⁰ α _i ^j _i =-1/2 _N-1 〓 ⁱ⁼⁰ α _i + _M 〓 ^j=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i (1/2- ^j _i ...(15) However, it is defined as ^M _i △ = Z ^M _i ...(16). Equation (16) formally considers the polarity bit of Z _i expressed in two's complement code as the inverted Z ^M _i It is shown that.

Therefore, the functions φ ^j ₁ , φ ₁ and the constant φ ⁰ ₁ are respectively defined as φ ^j ₁ △ = φ ₁ ( ^j ₀ , ^j ₁ , ..., ^j _N-1 ) △ = _N-1 〓 ⁱ⁼⁰ α _i (1/2− ^j _i )
...(17) φ ⁰ ₁ △ = - _N-1 〓 ⁱ⁼⁰ α _i =2φ ₁ (1, 1, ..., 1) ...(18) If defined, equation (15) becomes Y=φ ⁰ ₁ 2 ^-1 + _M 〓 ^j=1=0 φ ^j ₁ 2 ^j-1 = _M-1 〓 ^j=0 φ ^j ₁ 2 ^j-1 ...(19).

Furthermore, equation (19) is Y=[φ ^M ₁ + [φ ^M-1 ₁ +...+[φ ^j ₁ +...+{φ ² ₁ +
(φ ¹ ₁ +φ ⁰ ₁ 2 ^-1 )2 ^-1 }2 ^-1 ……〕2 ^-1 ……〕2 ^-1 〕2 ^M-1
...(20) is also expressed. Here, the partial sum Ψ ^j is Ψ ^j △ Ψ ^j △ = φ ^j ₁ + [φ ^j-1 ₁ +……+{φ ² ₁ + (φ ¹ ₁ +φ ⁰ ₁ 2 ^-1 ) 2
^-1 }2 ^-1 ...]2 ^-1 ...(21) If we define Ψ ^j =φ ^j ₁ +Ψ ^j-1 2 ^-1 ...(22) holds. However, it is assumed that Ψ ⁰ △ = φ ⁰ ₁ .

From equation (21), equation (20) can be expressed as Y=Ψ ^M 2 ^M-1 (23).

In addition, instead of equation (14), using the identity Z ^M _i + ^M _i =1 ...(14') and substituting Z ^M _i =1−Z ^M _i into equation (5), equation (15) is obtained. is Y=−1/2 _N-1 〓 ⁱ⁼⁰ α _i + _M 〓 ^j=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i (Z ^j _i −1/2) ……(15′) Changes to However, it is defined as Z ^M _i △ = ^M _i ……(16′).

At this time, φ ^j ₁ △ = φ ₁ ( ^j ₀ , ^j ₁ , ..., ^j _N-1 ) △ = _N-1 〓 ⁱ⁼⁰ α _i (Z ^j _i −1/2)
...(17') φ ⁰ ₁ △ = - _N-1 〓 ⁱ⁼⁰ α _i =2φ ₁ (1, 1, ..., 1) ...(18) If we define Equation (16') and Equation ( 15′) are each Y=φ ⁰ ₁ 2 ^-1 + _M 〓 ^j=1=0 φ ^j _i 2 ^j-1 = _M 〓 ^j=0 φ ^j _i 2 ^j-1 ...(19), and the above equation (16) and It is exactly the same as equation (19). Therefore, in this case as well, the first and second embodiments described below are the same.

The present invention provides formulas (16), (17) {(17′)}, (18),
(19) or equations (16), (17) {(17′)}, (18),
Based on the calculation principles of (22) and (23), the following structure is the gist.

That is, by adding 0 to the lower order (additional bit) of the least significant bit of the M-bit two's complement code sample value Z _i , all bits except the polarity bit of Z _i are inverted, resulting in a sample value _i = ^M. _i ^M-1 _i …… ² _i ¹
_i ⁰ _i
(additional bit Z ⁰ ₁ = 0) N pieces (i = 0, 1, ...,
N-1) Prepare N-dimensional vectors ( ^j ₀ , ^j ₁ ,...
..., ^j _N-1 ). A storage device is provided in which the value of φ ₁ is stored. First, if each component is an inverted additional bit from the storage device, an N-dimensional vector ( ⁰ ₀ , ⁰ ₁ , ..., Z ⁰ _N-1 Z _{N -1} ), that is, the N-dimensional vector (1, 1, ..., 1) is used as the address value to extract φ ₁ (1, 1, ..., 1) (= φ ⁰ ₁ /2), and the shift adder (accumulator Add to bowl). Next, φ 1 1 is extracted from the storage device using the vector ( ¹ ₀ , ¹ ₁ , ..., ¹ _{N-1 )} as _{the address value, and the unshifted φ 0 1} ^{/ 2} is extracted.
and are added by an accumulator. Furthermore, φ ² ₁ is extracted from the storage device using the vector ( ² ₀ , ² ₁ , . . . , ² _N-1 ) as an address value, and is shifted and added to the previous accumulation result in an accumulator. This operation is represented by a vector ( ^M ₀ , ^M ₁ , ...,
Z ^M _N-1 ), the filter output Y according to equation (19) or equation (23) is obtained. In other words, the original sample value with both positive and negative signs can be obtained by adding only the operation.
A device configuration for obtaining the filter output Y for Z _i can be realized.

Next, the present invention will be specifically described with reference to embodiments shown in the drawings.

It should be noted that both the embodiments shown in FIGS. 2 and 3 are configured for the second-order cyclic digital filter expressed by equation (8), as in the case of FIG. 1 for simplicity and comparison. It is something.

At this time, ψ ^j ₁ and ψ ₁ are calculated from equation (17) as ψ ^j ₁ = ψ ₁ ( ^j _o , ^j _o-1 , ^j _o-2 , ^j _o-1 , ^j _o-2 ) = a ₀ (1 /2− ^j _o )+a ₁ (1/2− ^j _o-1 )+a ₂ (
1/2- ^j _o-2 ) + b ₁ (1/2- ^j _o-1 ) + b ₂ (1/2
^−j _o-2 )
...(24), and the constant ψ ⁰ ₁ is from equation (18), ψ ⁰ ₁ = - (a ₀ + a ₁ + a ₂ + b ₁ + b ₂ ) = 2ψ ₁ (1, 1, 1
, 1, 1)...(25). Equation (19) and Equation (23) are equivalent, so for convenience of explanation of operation, Equation (23) is used to calculate the filter output.
y _o becomes y _o = Ψ ^M 2 ^M-1 ...(26).

The first embodiment will be explained with reference to FIG.

In Figure 2, EOR1 and EOR2 are exclusive OR, SR1 to SR3 are serial shift registers,
PSR1 and PSR2 are parallel input-serial output type shift registers, MEM2 is a storage device such as ROM or RAM, R1 is a register, PPR is a parallel input-parallel output type shift register, AD is an adder,
ACC2 is an accumulator consisting of R1, AD and PPR, and is constructed as shown.

In Fig. 2, in shift register PSR1, 0 is further added to the lower order of the least significant bit of sample value _xo , and each bit becomes an additional bit (=0).
are applied to EOR1 in series starting with .

Here, EOR1 sets the signal _LM to high level except during the polarity bit passage time, inverts all bits except the polarity bit, and sets it as _o to shift register SR1.
give to At the same time, each bit of the input ripple value _o-1 delayed by 1 sample time is sequentially moved from shift register SR1 to SR2, and from SR2 the input sample value _o-2 delayed by 2 sample times is transferred from shift register SR1 to SR2.
Each bit appears in sequence. _o , _o-1 and _o-2
Each bit is sequentially applied to the storage device MEM2. Similarly, from shift register PSR2, a sample value is obtained by adding 0 to the lower order of the least significant bit of the output sample value y _o- 1 delayed by one sample time.
Each bit of y ^* _o-1 is sent out in series, and as before, all bits except the polarity bit are inverted at EOR2 and sent as _o-1 to the shift register SR.
3 is applied. Each bit of the output sample value _o-2 delayed by two sample times is sequentially sent from SR3. Each bit of _o-1 and _o-2 is applied sequentially to storage device MEM2. Therefore, the storage device MEM2 contains 5-bit information ^j _o , ^j _o-1 ,
x ^j _o-2 , ^j _o-1 , ^j _o-2 are given. As shown in FIG. 2, the storage device MEM2 has 32 storage locations with the above 5 bits as address values, and each of them has B bits of the value of φ ₁ calculated in advance by equation (24) as data. It is stored in two's complement code. Therefore, first, we create a five-dimensional vector ( ⁰ _o , ⁰ _o-1 , ⁰ _o-2 ,
y ⁰ _o-1 , ⁰ _o-2 ), that is, a five-dimensional vector (1, 1,
1, 1, 1) as the address value and the storage device MEM
2, φ ₁ (1, 1, 1, 1, 1) (=φ ⁰ ₁ /2) is extracted and stored in register R1 in accumulator ACC2. The output of register R1 is given to adder AD, and shift register PPR is initialized.
The addition result φ ⁰ ₁ /2 is stored in the shift register PPR as an initial value for accumulation. Next, the five-dimensional vector ( ¹ _o , ¹ _o-1 , ¹ _o-2 ,
y ¹ _o-1 , ¹ _o-2 ) is the address value, and φ ¹ ₁ is the storage device.
It is pulled out from MEM2 and applied to adder AD through register R1. In the adder AD φ ¹ ₁ is the signal
Contents of shift register PPR that is not shifted by setting _L1 to low level (initial value φ ⁰ ₁ /2)
and the partial sum Ψ ¹ is stored in the shift register PPR. Furthermore, the vectors ² _o , ² _o-1 , ² _o-2 ,
y ² _o-1 , ² _o-2 ) as the address value of the storage device MEM.
φ ² ₁ drawn from 2 is given to adder AD through register R1, and the content of shift register PPR (Ψ ¹ 2 ^-1 ), which is shifted by 1 bit of the previous partial sum Ψ ¹
The resulting partial sum Ψ ² is stored in the shift register PPR. This behavior is expressed as a vector ( ^M-1 _o , ^M-1 _o-1 , ^M-1 _o-2 , ^M-1 _o-1 , ^M-1 _o
-2 ), the partial sum Ψ ^M-1 is obtained, and finally, the vector ^M _o whose components are the uninverted polarity bits themselves,
x ^M _o-1 , ^M _o-2 , ^M _o-1 , ^M _o-2 ), Ψ ^M , that is, the filter output y _o of equation (26) is obtained.

Next, a second embodiment will be explained with reference to FIG.

Fig. 3 is almost the same as Fig. 2, but the difference is that instead of the accumulator ACC2 in Fig. 2, the shift register PPR is replaced with register R2, and the adder AD and Furthermore, registers R1, R2 and an adder are connected in the same way as the accumulator ACC1 in Figure 1.
The difference is that an accumulator ACC3 to which a signal switching circuit MPX connected to AD is added is provided. Note that the output line of the storage device MEM2 is shifted by one bit and connected to one input of MPX.

Regarding the operation in FIG. 3, only the points different from those in FIG. 2 will be explained. The initial value φ ⁰ ₁ /2 of the accumulation is stored in the shift register PPR through the adder AD in FIG.
In the figure, the initial value φ ⁰ ₁ is stored directly in the register R2 through the signal switching circuit MPX in the accumulator ACC3 by setting the signal H ₀ to a high level, thereby reducing the number of additions by one.

In the second embodiment, it is also possible to provide a separate storage device for storing the initial value φ ⁰ ₁ . Further, a configuration in which the register R2 is replaced with a parallel input-parallel output type shift register or a configuration in which one input of the signal switching circuit MPX is connected to the output of the register R1 is also possible.

In the first and second embodiments, the order of the components of the five-dimensional vector used as the address value to the storage device may be arbitrary. Accordingly, the contents of the storage device are made to correspond.

Also, 5-bit information ^j _o , ^j _o-1 , ^j _o-2 , ^j _o-1
,
means for generating y ^j _o-2 (j=0, 1, ..., M);
Of course, other operations for obtaining a constant value (initial value) and other configurations of the accumulator can be considered. Register R1
It is also possible to omit the configuration.

Furthermore, the address value is a five-dimensional vector ( ^j _o ,
x ^j _o-1 , ^j _o-2 , ^j _o-1 , ^j _o-2 ),
Generally 5 bits of information ^j _o , ^j _o-1 , ^j _o-2 , ^j _o-1
,
Function of y ^j _o-2 (x ^j _o , x ^j _o-1 , x ^j _o-2 , y ^j _o-1 , y ^j _o-2
)
It can also be determined as an address value determined by Accordingly, the contents of the storage device are made to correspond.

[Brief explanation of the drawing]

FIG. 1 shows the structure of a conventional digital filter using subtractable adders. FIG. 2 shows an embodiment of the present invention having a configuration that can be compared with the conventional example shown in FIG. FIG. 3 shows another embodiment of the invention. In the figure, ADS is a subtractable adder, AD is an adder, MEM1 and MEM2 are storage devices, and SR1 to
SR3 is a serial shift register, PSR1, PSR
2 is a parallel input-serial output type shift register,
PSR is a parallel input-serial output type shift register.
R1 and R2 are registers, EOR1 and EOR2 are exclusive OR, MPX is signal switching device, ACC1 to ACC
3 indicates an accumulator.

Claims (1)

[Claims] 1. Filter the M-bit binary code sample value Z _i containing N positive and negative values successively arriving, Y= _N-1 〓 ⁱ⁼⁰ α _i Z _i (where Z _i = −Z ^M _i 2 ^M-1 + _M-1 〓 ^j=1 Z ^j _i 2 ^j-1 ) In a digital filter that outputs a filter output Y expressed by a function, the binary code sample value is received. , an inverting means for selectively inverting bits other than bits indicating polarity and transmitting a logic value 1 in advance of the first bit; N bit information corresponding to each bit of the N inverted binary code sample values; a function ψ ψ ( ^j ₀ , ^j ₁ , ..., ^j _{N-1 )} = ^j = _N-1 〓 ⁱ⁼⁰ α _i ( a storage device that stores Z ^j _i −1/2); receives the output ψ ^j of the storage device, and the first time, Ψ ⁰ = ψ (1, 1, ..., 1); the second time, Ψ ¹ = ψ ¹ + Ψ ⁰ From the third time onwards, a digital filter is provided with an accumulator that calculates ψ ^j = ψ ^j + ψ ^j-1 2 ^-1 .