JPS6352469B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a chip carrier, which is a package for mounting an IC, and a method for manufacturing the same.

[Background of the invention]

Currently, in consumer and industrial electronic equipment,
Dual In-Ine Package (hereinafter referred to as DIP) is a rectangular package with a cavity in the center for mounting an IC chip, with pin-type terminals arranged at equal intervals on both long sides.
is used in large quantities.

However, with DIP, as the number of terminals increases, the imbalance between the chip outer shape and the package outer shape increases, resulting in a significant drop in mounting efficiency. Things are changing.

In order to meet these needs, flat packs and chip carriers are available as packages for efficiently mounting LSI chips with a large number of terminals.Chip carriers in particular are highly versatile, easy to test, and inexpensive, allowing for high-density packaging. It is suitable for implementation, and usage is expected to increase further in the future.

The main types of chippukiyaria currently in use are:
There are ceramic chip carriers in which the package is made of ceramic material, and there are also plastic chip carriers in which the package is made of plastic material.

However, the former uses precious metal paste as a conductor and requires a complicated firing process at high temperatures, making it expensive, while the latter can be manufactured at low cost, but the package is made of plastic. This has the disadvantage that it has a large thermal resistance, making it difficult to mount chips that generate a large amount of heat.

[Purpose of the invention]

The present invention was made in view of the drawbacks of the prior art, and its object is to provide a chip carrier with excellent heat dissipation by forming the package from a metal material, and a method for manufacturing the same.

[Summary of the invention]

The chip carrier according to the first aspect of the present invention is characterized in that the package on which the semiconductor chip is mounted is formed of a metal material, the package has a double structure on the front and back, and the metal plate on either the front or the back is divided. This configuration achieves the above object.

Further, in the method for manufacturing a chip carrier according to the second aspect of the present invention, a conductive film is formed on the surface of a flat substrate, and internal electrode portions and external connection terminal portions are formed on this film by plating resist. After forming a developed pattern of conductive paths, a conductor pattern is plated on the developed conductive path pattern, an insulating film is formed on the conductor-plated surface, and then a first metal plate that will form a package is formed. A second metal plate, which is connected to the central part of the conductive path developed pattern and is divided into two or more parts matching the outer shape of the first metal plate, is bonded onto the end of the conductive path developed pattern, and the flat plate-like After the substrate is peeled off, the first metal plate and the second metal plate are stacked and integrated so that the conductive path is on the outside, and with this configuration, the above object is achieved. Ru.

[Embodiments of the invention]

First, a first embodiment of the present invention will be described based on the drawings.

1 and 2 are diagrams showing a first embodiment of a chip carrier according to the first invention.

In these figures, the chip carrier 1 includes a square package 4 in which a recess 2 for mounting a semiconductor chip is formed in the center, and five conductive paths provided at predetermined intervals on opposite edges of the package 4. It consists of 6.

The package 4 is made of a metal plate such as an aluminum plate, a steel plate, or a copper plate, and includes upper metal plates 4A and 2.
The lower metal plate 4B, which has been divided into two parts, is bonded and integrated.

The conductive path 6 extends from the top surface of the package 4 to the bottom surface via the side edge, and an internal electrode portion 6A is formed near the recess 2 on the top surface of the package, and an external connection terminal portion 6B is formed from the side edge of the package to the bottom surface. has been done.

An insulating coating 8 made of epoxy resin, polyimide resin, phenol resin, etc. is formed between the conductive path 6 and the outer surface of the package 4, and the conductive path 6 and the package 4 made of metal material are Insulated.

A semiconductor chip (not shown) is housed in the recess 2 and connected to the internal electrode section 6A, and the chip carrier 1 is directly or indirectly connected to the printed wiring board through a socket (not shown). (not shown), but since the package 4 of the chip carrier 1 is made of metal, heat is dissipated from the package 4 into the atmosphere, so it is possible to mount a chip that generates a large amount of heat. becomes.

3 to 5 are diagrams showing a second embodiment of the chip carrier according to the first invention.

In these figures, the chip carrier 11 is
The points mentioned above are that the lower metal plate forming the package is formed by four right-angled triangular divided metal plates 14B divided diagonally, and that the conductive paths 6 are provided on the four sides of the package. Unlike the first embodiment, the rest is the same as the first embodiment,
By assigning the same reference numerals, the explanation thereof will be omitted.

FIGS. 6 and 7 are diagrams showing a third embodiment of the chip carrier according to the first invention.

In these figures, the chip carrier 21 has a lower metal plate 24B formed of a single metal plate, and an upper metal plate divided diagonally and having a trapezoidal divided metal plate 24A with the top cut off.
The chip mounting recess 2 is formed by the lower metal plate 24B and the inner edge 25 of the upper metal plate.

Therefore, in this third embodiment, the troublesome processing work of forming a chip mounting recess in the metal plate can be omitted.

The rest is the same as in the previous embodiment, and the explanation thereof will be omitted by giving the same reference numerals.

8 and 9 show a fourth embodiment of the chip carrier according to the first invention, in which the conductive path 6
An insulating coating 8 is formed between the metal package 4 and the upper and lower surfaces of the package 4 and the entire side edge where the conductive path 6 is formed, and the conductive path 6 covers only the surface thereof. The chip carrier 1 is embedded in the coating 8 while being exposed to the outside.
The surface of A is a smooth surface. The other parts are the same as those in the first embodiment, and the explanation thereof will be omitted by giving the same reference numerals.

This fourth embodiment has a structure in which the outer surface of the chip carrier is covered with an insulating coating 8, but the thickness of this coating 8 is very thin compared to the thickness of the package. thickness 2
5 mm, the coating thickness is 10 to 20 μm, and the discharge effect into the atmosphere is limited to chip carriers where the insulating coating 8 is formed only on the lower surface of the conductive path 6 (for example, the
It is not inferior to the one shown in the figure).

Further, since the surface of the chip carrier is smooth, there is an advantage that bonding work can be easily performed.

Next, a first embodiment of the method for manufacturing a chip carrier according to the second invention will be described based on FIGS. 10 to 18.

First, a substrate 30 (usually a stainless steel plate or a titanium plate) with a smooth surface is prepared,
A conductive coating 31 (film thickness 0.1μ) is applied to the surface of this substrate 30.
~10μ).

This conductive film 31 is generally made of copper, but may be made of any conductive metal such as nickel, tin, cobalt, iron, or zinc.
The coating 31 is formed by electroplating, chemical plating, or vacuum plating.
When the film 31 is made of a non-conductive material such as resin, it is desirable to form the film 31 by vacuum plating.

Next, as shown in FIGS. 10 and 11,
A conductive path development pattern including an internal electrode portion and an external connection terminal portion is formed on the conductive film 31 using a plating resist 33 .

As the plating resist material, commonly used positive resist or negative liquid photoresist is used, but when the plating resist is used as a permanent mask without peeling off after plating the conductor. The conductive path development pattern may be formed by screen printing using a resin ink with excellent insulation and heat resistance such as epoxy resin, polyimide resin, or phenol resin, or may be used as a plating resist material. A photosensitive film with excellent heat resistance and insulation properties may be used, and when a photosensitive film is used, the narrower the electrode pitch interval, the more effective it is.

Next, as shown in FIG.
Copper conductor plating is applied to 35. This conductor plating portion 37 forms a conductive path 36 including an internal electrode portion 36A and an external connection terminal portion 36B.

Next, as shown in FIG. 13, the conductor plating portion 37 of the conductor pattern portion is coated with a resin having excellent heat resistance and insulation properties, or a film having similar properties is adhered to form a coating 39. Form. This coating 39 is intended to provide insulation between a metal plate forming a package to be described later and the conductive path 36.

Then, as shown in FIGS. 14 and 15, the metal plate 34A, which has the chip mounting recess 32 formed in the center of the conductive path development pattern, is attached to the adhesive with the recess 32 of the metal plate 34A facing downward. Twist and glue. At this time, the internal electrode portion 36 of the conductive path 36
A will be located near the recess 32.

Furthermore, a metal plate 34B having a size obtained by dividing the metal plate 34A into two is adhered to the left and right sides of the metal plate 34A at a predetermined distance apart and overlapping the end portion of the external connection terminal portion 36B. Both metal plates 34A, 3
The distance between 4B is made equal to the total thickness of both metal plates 34A and 34B.

Next, as shown in FIG. 16, the chip carrier developed body formed on the conductive coating 31 is peeled off from the substrate 30 together with the coating 31, and then the first
As shown in FIG. 7, the conductive film 31 is removed by dissolving it, and the plating resist 33 is also removed. If the conductive film 31 is made of copper, it is desirable to remove it by immersing it in ammonium persulfate.

Note that when the plating resist 33 is used as a permanent mask, the removal work of the plating resist 33 becomes unnecessary.

Next, the metal plate 34B is bent inward (in the direction of the arrow in FIG. 17) and adhered onto the metal plate 34A with an adhesive to form an integral body as shown in FIG. 18. Then, if this is reversed, the first
As shown in the figure, the chip carrier consists of a metal package with a chip mounting recess formed in the center of the top surface, and is equipped with a conductive path 36 extending from the top surface of the package through the side edges to the bottom surface of the package.

In the copper conductor plating process (shown in Figures 11 and 12), a precious metal such as gold, silver, platinum, or rhodium is first plated to a thickness of 0.1 to 5μ, and then By plating a copper conductor with a thickness of 5 to 50 μm, the surface layer of the conductive path of the manufactured chip carrier becomes a noble metal plating layer, which improves the bonding with the chip.

In addition, when forming this precious metal plating layer, patterns for only the internal electrode portions and external connection terminal pad portions are formed using plating resist, and after precious metal plating is applied only to these portions, the resist portion is The amount of expensive precious metals used can be reduced by removing the pattern, then forming the entire conductive path development pattern again using a plating resist, and plating the conductive path development pattern with a conductor.

In the above embodiment, the plating resist 33 is removed after the chip carrier development body is peeled off from the substrate 30, but the plating resist 33 may be removed immediately after conductor plating.

In this case, as shown in FIGS. 19 and 20, an insulating coating 39A is formed over the entire conductive path development pattern to which conductor plating has been applied.
The work of forming an insulating film is easier than in the case where the insulating film is formed only on the conductor plating portion 37 as in the embodiment described above. After that, the metal plate 34
A and 34B are adhered onto the coating 39A, and then the chip carrier development body is peeled off from the substrate 31, and after removing the conductive coating 31, the metal plates 34A and 34B are overlapped and adhered to each other to produce an integrated product. Furthermore, an insulating coating 39A covering the chip loading recess.
By cutting out and exposing the chip mounting recess, a chip carrier having an insulating coating formed on the outer surface as shown in FIG. 8 is manufactured.

In the first embodiment, the plating resist 33 is removed after the insulating film 39 is formed, so there is a risk that the plating resist 33 may adhere to the insulating film 39 and making it difficult to remove the plating resist 33. However, there is no such concern in this second embodiment.

Note that the third embodiment (sixth embodiment) of the first invention
As shown in FIG.
In order to manufacture a chip carrier in which the internal electrode portion 6A of the conductive path 6 is formed by the divided metal plate 24A, the internal electrode portion 6A of the conductive path 6 is placed outwardly and
It is necessary to form a conductive path development pattern using plating resist so that B is on the inside.

〔Effect of the invention〕

As is clear from the above description, according to the first aspect of the invention, a chip can be mounted without considering the amount of heat generated by the chip.

Furthermore, according to the second aspect of the invention, a metal chip carrier with excellent heat dissipation properties can be smoothly manufactured.

[Brief explanation of the drawing]

FIG. 1 is a perspective view of a first embodiment of the first invention, FIG. 2 is a sectional view taken along the line - shown in FIG. 1, and FIG. 3 is a perspective view of a second embodiment of the first invention. A perspective view, FIG. 4 is a bottom view, and FIG. 5 is a developed view.
FIG. 6 is a plan view of the third embodiment of the first invention, FIG. 7 is a developed view thereof, and FIG. 8 is a plan view of the third embodiment of the first invention.
A perspective view of the embodiment, FIG. 9 is a line shown in FIG.
10 to 18 are diagrams showing the chip carrier in each manufacturing process according to the first embodiment of the second invention, and FIG. 11 is a cross-sectional view taken along the line shown in FIG. 10.
15 is a sectional view taken along the line shown in FIG. 14, FIG. 19 is a diagram showing the main steps of the second embodiment of the second invention, and FIG. 20 is a sectional view taken along the line XI-XI. FIG. 20 is a sectional view taken along the line - shown in FIG. 19; 1 , 11 , 21 , 1A...Chip carrier according to the first invention, 2...Chip mounting recess, 4...
... Package cage, 4A, 24A ... Upper layer metal plate, 4
B, 14B, 24B...lower metal plate, 6...conducting path, 6A...internal electrode section, 6B...terminal section for external connection, 8...insulating coating, 30...substrate, 31...
...Conductive coating, 32...Chip mounting recess, 33
...Plating resist, 34A, 34B...Metal plate, 36...Conducting path, 37...Conductor plating part, 3
9,39A...Insulating film.

Claims (1)

[Scope of Claims] 1. A rectangular package having a recess for mounting a semiconductor chip in the center, an internal electrode section provided at a predetermined interval near the recess, and a downward direction from the internal electrode section passing through the side edge of the package. In the chip carrier, the package is made of a metal material, and an insulating coating is provided between the conductive path and the conductive path, and the metal package is made of a metal material. It has a double structure of a first metal plate and a second metal plate, and one of the front and back metal plates of the double metal plate forming this package has a side edge where a conductive path is provided. A chippukiyaria characterized by being divided into two or more metal plates containing the same. 2. After forming a conductive film on the surface of a flat substrate and forming a developed pattern of a conductive path having an internal electrode portion and an external connection terminal portion on this film using a plating resist, the conductive path is developed. A conductor pattern is plated on the pattern, an insulating film is formed on the conductor plated surface, and then a first metal plate forming a package is adhered to the center of the conductive path development pattern, and the conductor pattern is plated. A second metal plate that matches the outer shape of the first metal plate and is divided into two or more is adhered onto the end of the conductive path development pattern, and after peeling off the flat substrate, the conductive path is placed on the outside. A method for manufacturing a chip carrier, characterized in that the first metal plate and the second metal plate are overlaid and integrated.