JPS6355110B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to Which the Invention Pertains] The present invention relates to an improvement in a logarithmic amplifier used to expand its uses by applying it to various measurement circuits.

[Prior art]

Logarithmic amplifiers have traditionally utilized the exponential characteristics of the PN junction of transistors, but the challenge was how to compensate for changes in characteristics due to temperature. FIG. 1 shows an example of a logarithmic amplifier that has been put into practical use. Output of logarithmic conversion circuit 1 for current input I _C when reference current is I _R
V _p1 is expressed as V _p1 = - (kT/q) ln (I/I _R ) k: Boltzmann constant q: electron charge T: absolute temperature (〓), and the scale factor is transistor
It is proportional to the absolute temperature T of Q ₁ and Q ₂ . Therefore, the amplifier circuit 2 uses an element R _S whose resistance value changes depending on the temperature, such as a thermistor, to increase the gain to 1/T.
The output V _p2 is obtained by correcting the temperature characteristics of the output V _p1 of the previous stage.

However, the logarithmic amplifier with the above configuration is
There are problems in that it is difficult to match temperature coefficients between elements and achieve temperature uniformity, and temperature correction is not sufficient.

〔the purpose〕

The present invention was made to solve the above problems, and aims to realize a logarithmic amplifier that is suitable for IC implementation and has excellent linearity and temperature characteristics.

〔overview〕

According to the present invention, the above object can be achieved by combining a logarithmic conversion section and a differential amplification section and compensating the temperature characteristics of the logarithm conversion section with the temperature characteristics of the differential amplification section.

[Explanation of Examples]

The present invention will be explained below based on the drawings.

FIG. 2 is a block diagram showing the basic configuration of the present invention. 3 is a logarithmic conversion unit that logarithmically converts the input current I _C , and 4 is the output V ₁ and V ₂ from this logarithm conversion unit.
The differential amplification section calculates the difference by inputting
It outputs two currents I ₁ and I ₂ that are proportional to V ₁ −V ₂ .

FIG. 3 is an electrical circuit diagram showing one embodiment of the logarithmic conversion section 3. 5 is an input terminal to which input current I _C is applied; 6 is a reference input terminal to which reference current I _R is applied;
Q ₃₁ and Q ₃₂ have their collector terminals connected to the terminals 5 and 6.
The logarithmic conversion transistors A ₁ and A ₂ have their inverted input terminals connected to the collector terminals of these transistors Q ₃₁ and Q ₃₂ , and their non-inverted input terminals connected to the common. , operational amplifiers whose output terminals are respectively connected to the emitter terminals of the transistors, and 7 and 8 are output terminals to which the output terminals of these operational amplifiers are respectively connected. In this case, the input current I _C and the output voltage V ₁
There is a relationship as shown in the following equation.

V ₁ = −kT/q (lnI _C −lnI _S1 ) (1) I _S1 : Emitter saturation current of transistor Q ₃₁ Similarly, the following relationship exists between reference current I _R and output voltage V ₂ . be.

V ₂ = −kT/q (lnI _R −lnI _S2 ) (2) I _S2 : Emitter saturation current of transistor Q ₃₂ Thus, the output voltages V ₁ and V ₂ are the logarithms of the input current I _C and reference current I _R, respectively. It is expressed as a function and at the same time is proportional to absolute temperature. Note that the logarithmic conversion circuit 1 shown in FIG. 1 can be similarly used as the logarithmic conversion section 3.

FIG. 4 is an electrical circuit diagram showing one embodiment of the differential amplifier section 4. As shown in FIG. 9 and 10 are differential input terminals for inputting the voltage outputs V ₁ and V ₂ of the logarithmic conversion section 3, Q ₄₁ and Q ₄₂
are input transistors whose base terminals are connected to the differential input terminals 9 and 10, 13 is a constant current source to which the emitter terminals of the input transistors Q ₄₁ and Q ₄₂ are connected, and 11 and 12 are the input transistors Q ₄₁ and These are output current terminals connected to the collector terminals of _Q42 respectively.

In this case, the following known relationship exists between the output current difference I ₁ - I ₂ and the differential input voltage difference V ₁ - V ₂ (Industrial Research Association "Analog Application Handbook").
P68).

I _p4 : Current flowing through constant current source 13 V _BE1 : Voltage between the base and emitter of transistor Q ₄₁ V _BE2 : Voltage between base and emitter of transistor Q ₄₂ Maclaurin expansion of equation (3) gives I ₁ − I ₂ = I _p4 (x/2−x ³ /24+x ⁵ /240−…) (4), and x≪1, that is, V ₁ −V ₂ ≪kT/q26m
V (at 27° C.), I ₁ −I ₂ I _p4 q/2kT (V ₁ −V ₂ ) (5), and the gain is proportional to 1/T.

In the logarithmic conversion section of Figure 3, the transistor
If Q ₃₁ and Q ₃₂ are matched, I _S1 = I _S2 , so the following equation holds true.

V ₁ −V ₂ = −kT/qlnI _C /I _R (6) Substituting equation (6) into equation (5), I ₁ −I ₂ −I _p4 /2lnI _C /I _R (7) and the output The current difference I ₁ −I ₂ becomes independent of the absolute temperature T. In this way, the temperature characteristic of the difference V ₁ -V ₂ between the outputs from the logarithmic converter shown in FIG. 3 can be compensated for by the differential amplifier circuit described above. This circuit does not use special elements such as thermistors, so
Suitable for IC.

However, in general x>1 (for example, if the input range in Figure 3 is ±3 days, then V ₁
-V ₂ =±180 mV), in which case sufficient linearity and temperature compensation effects cannot be obtained.

In addition, in the logarithmic conversion section of Fig. 3, the transistor
Parasitic impedance of Q ₁ and Q ₂ (emitter resistance +
FIG. 5 shows an equivalent circuit diagram taking into account β×base diffusion resistance). Parasitic impedance is equivalently represented by emitter resistances r _e1 and r _e2 . In this case, equation (6) becomes V ₁ −V ₂ = −kT/qlnI _C /I _R −r _e1 I _C +r _e2 I _R (8), indicating that the influence of parasitic impedance appears as an output error. ing.

FIG. 6 is an electrical circuit diagram showing a differential amplifier with improved linearity and temperature compensation effect, which constitutes a second embodiment of the present invention. 14 and 15 are differential input terminals for inputting the output voltages V ₁ and V ₂ from the logarithmic conversion section 3, respectively; Q _A11 , Q _B11 and Q _B21 ,
Q _A21 has its base terminal as the differential input terminal 14,
15, respectively connected input transistors, Q _A12
〜Q _A1N , Q _B12 〜Q _B1M , Q _B22 〜Q _B2M , Q _A22 〜 Q _A2N are voltage dividing means using series-connected voltage dividing transistors whose collectors and base terminals are sequentially connected to the emitter terminal of the previous stage. The base and collector terminals of the transistors Q _A12 , Q _B12 , Q _B22 , Q _A22 are connected to the input transistors Q _A11 , Q _B11 ,
Connect to the emitter terminals of Q _B21 and Q _A21 , respectively.
16 and 17 are the voltage dividing transistors Q _A1N ,
Constant current sources 18 and 19 are respectively connected to the emitter terminals of Q _A2N and Q _B1M and Q _B2M , and current output terminals 18 and 19 are connected to the collector terminals of the input transistors Q _A11 and Q _B21 and Q _B11 and Q _A21 , respectively. Note that transistors Q _A11 ~ _{Q A1N} , Q _A21 ~Q _A2N , constant current source 16 and transistors Q _B11 ~ _{Q B1M} , Q _B21 ~
Q _B2M and constant current source 17 each constitute a differential amplifier circuit. The collector terminals of the input transistors of each differential amplifier circuit are output terminals 18 and 19.
are cross-connected to each other.

Assuming that all the transistors in the figure have the same characteristics (possible by using ICs, etc.), transistors in the same column have the same emitter current, so the base and
The emitter-to-emitter voltages V _BE are also all equal. Transistors Q _A11 ~ _{Q A1N} , Q _B11 ~ _{Q B1M} , Q _B21 ~ _{Q B2M} , Q _A21
~Q _A2N 's V _BE is V _BEA1 , V _BEB1 , V _BEB2 ,
Assuming V _BEA2 , the following relationship holds.

In other words, the differential input V ₁ - V ₂ has a voltage division ratio of 1/N,
The partial pressure is 1/M. Moreover, the following relationship exists between each current.

I ₁ = I _A1 + I _B2 I ₂ = I _A2 + I _B1 I _A1 + I _A2 = I _A I _B1 + I _B2 = I _B Using the above relationship, the output current difference I ₁ − I ₂ is as follows: .

I ₁ − I ₂ = (I _A1 + I _B2 ) − (I _A2 + I _B1 ) = (I _A1 − I _A2 ) −
(I _B1 - I _B2 ) = {I _A /1 + exp (-x/N) - I _A /1 + exp (x/N
)}−{I _B /1+exp(-x/M)−I _B /1+exp(x/
M)} =I _A (x/2N−x ³ /24N ³ +x ⁵ /240N ⁵ −…)−I _B (x
/2M−x ³ /24M ³ +x ⁵ /240M ⁵ −…) =x/2(I _A /N−I _B /M)−x ³ /24(I _A /N ³ −I _B /
M ³ ) + x ⁵ / 240 (I _A / N ⁵ - I _B / M ⁵ ) +... (10) Here, set the values of constant current I _A and I _B so that I _B = I _A M ³ / N ³ If you choose , the second term of equation (10) becomes zero and the following equation is obtained.

I ₁ - I ₂ = I _A (1-M ² /N ² ) {1/2 (x/N) +
1/240・(−N ² /M ² )・(x/N) ⁵ +…}(11) Comparing equation (11) with equation (4), the input voltage range is N/
(1-M ² /N ² ) times, and the non-linearity also becomes smaller. The influence of the second term in equation (11) is (-N ² /M ² ) times as large as the influence of the third term in equation (4), and to reduce this, the value of M must be adjusted within the range of MN-1. Just make it bigger. FIG. 7 shows the results obtained by simulation of the linearity error for each combination of the values of N and M in equation (11). As the figure shows, M=0, i.e. transistors Q _B11 ~ _{Q B1M} ,
When Q _B21 to _{Q B2M} are not used, linearity improves as N increases, and when M≠0, linearity further improves as N and M increase. Note that this circuit is also similar to the first embodiment.
Suitable for IC.

FIG. 8 is an equivalent circuit diagram in consideration of the parasitic impedance of the transistor in the differential amplification section of FIG. 6. The symbol of the corresponding transistor is used for each parasitic impedance. In this diagram
The equation corresponding to equation (9) is found as follows.

As is clear from equation (12), the parasitic impedance r _e
If there is an influence of 1/T, the gain of the differential amplifier shown in FIG. 8 will not be completely proportional to 1/T.

In FIG. 9, a circuit that corrects the parasitic impedance error in the circuit of FIG. 3 is used as the logarithmic conversion section 3, and a circuit that corrects the parasitic impedance error in the circuit of FIG. 6 as the differential amplifier section 4. FIG. 7 is an electrical circuit diagram showing a third embodiment of the present invention in which a logarithmic amplifier is constructed using the circuit. The same parts as in FIGS. 3 and 6 are designated by the same reference numerals, and their explanation will be omitted. In the logarithmic conversion unit 20, Q _C1 ,
Q _C2 is a transistor R 1 whose one base terminal is connected to the collector terminal of the other, and whose base and emitter terminals are respectively connected to the base and emitter terminals of transistors Q ₃₁ and Q ₃₂ to form _a current mirror circuit. , R ₂ are resistors with a resistance value R _E connected between the base terminals and common of the transistors Q _C1 and Q _C2 , respectively. In the differential amplifier section 21, one end of R ₃ and R ₄ is connected to the emitter terminal of the transistor Q ₃₁ of the logarithmic conversion section 20, and the other end is connected to the transistor Q _A11 and Q _B11 , respectively. The compensating resistors of NR _E and M _E , R ₅ and R ₆ have one end connected to the logarithmic conversion section 20.
Compensation resistors Q cA1 , Q _cB1 , Q _cB2 , Q _cA2 with resistance values N _{E and} M _E are connected to the emitter terminal of the transistor Q ₃₂ and the other ends are connected to the transistors Q _A21 and Q _{B21 ,} respectively. are connected to their collector terminals or the other ends of the compensation resistors R ₅ , R ₆ , R ₄ , R ₃ respectively, and their base and emitter terminals are connected to the bases and emitters of transistors Q _A1N , Q _B1M , Q _B2M , Q _A2N. A transistor connected to the terminal to form a current mirror circuit, 24 a constant current source with a current value of 2I _A connected to the emitter terminals of the transistors Q _cA1 and Q _cA2 , 25 the transistor
Current value connected to emitter terminals of Q _cB1 and Q _cB2
2I _B constant current source.

In the logarithmic conversion unit 20, equal collector currents flow through transistors Q ₃₁ and Q _c1 and Q ₃₂ and Q _c2 that constitute a current mirror circuit. Therefore, current I _C flows through resistor R ₂ and current I _R flows through resistor R ₁ . The emitter terminal output voltage V ₁ of the transistor Q ₃₁ is expressed as follows, taking into account the parasitic impedance f _e1 shown in FIG.

V ₁ = -kT/qlnI _C /I _S1 -R _E I _R -r _e1 I _C (13) Similarly, the emitter terminal output voltage of transistor _Q32 is V ₂ = -kT/qlnI _R /I _S2 -R _E I _C −r _e2 I _R (14). Taking the difference between equations (13) and (14), we get V ₁ −V ₂ = −kT/qlnI _C /I _R + (r _e2 − R _E ) I _R + (R _E − r _e1 ) I _C ( 15) If the resistance values are chosen so that R _E = r _e1 = r _e2 = r _e ,
Equation (15) becomes V ₁ −V ₂ =−kT/qlnI _C /I _R (16), and the output voltage difference V ₁ −V ₂ is no longer affected by parasitic impedance.

In the differential amplifier circuit 21, transistors Q _A1N , Q _cA1 , Q _B1M and
Since the collector currents flowing through Q _cB1 , Q _cB2 and Q _B2M , and Q _cA2 and Q _A2N are equal, the transistors Q _cA1 ,
The collector currents of Q _cB1 , Q _cB2 , and Q _cA2 are I _{A1 and} Q cA2 , respectively.
I _B1 , I _B2 , I _A2 . Compensation resistance R ₃ , R ₄ , R ₅ , R ₆
The voltages at the other end of V ₁₁ , V ₁₂ , V ₂₁ ,
When V ₂₂ is set, an equation similar to equation (9) is found as follows.

here By substituting each of the relationships into equation (17) and using the relationship R _E = r _e , the following equation is obtained.

As a result, the output current difference I ₁ − I ₂ is expressed by equation (11),
No longer affected by parasitic impedance r _e .

That is, according to the differential amplifier shown in FIG. 9, the influence of parasitic impedance on the input/output characteristics is corrected, so that the linearity and temperature characteristics are improved compared to the circuit shown in FIG. 6. Also, like the previous embodiment, since special elements such as a thermistor are not used, the IC
suitable for becoming

FIG. 10 is an electrical circuit diagram showing a fourth embodiment of the present invention, in which a resistive divider circuit is used as the voltage dividing means of the differential amplification section of FIG. In the figure, the same parts as in FIG. 9, such as the logarithmic conversion unit 20, are given the same reference numerals. In the differential amplifier section 28, a resistor (N
-1) R, 2R, (M-1)R constitute a resistor divider circuit, and the differential voltage V ₁₁ -V ₂₁ is divided by a voltage division ratio of 1/N, and the differential voltage V ₁₂ -V ₂₂ is divided by a voltage division ratio of 1/M. There is partial pressure.
Q _A1 , Q _A2 , Q _B1 , Q _B2 are the transistors in Fig. 9
These are input transistors corresponding to Q _A11 , Q _A21 , Q _B11 , and Q _B21 . In the circuit of Fig. 9, multiple voltage dividing transistors Q _A12 ~Q _A1N , Q _B12 ~ _{Q B1M} , Q _B22 ~ _{Q B2M} ,
The effect of expanding the input range obtained by Q _A22 to Q _A2N can be similarly obtained by the above-mentioned resistance division. however,
As in the case of FIGS. 6 and 9, it is assumed that I _B =I _A M ³ /N ³ . Transistors Q _cA1 , Q _cA2 , Q _cB1 , Q _cB2 are the ninth
As in the case shown in the figure, it is used to correct the parasitic impedance r _e . By using the circuit having the configuration shown in FIG. 10 in this way, the same effect as shown in FIG. 9 can be obtained.

In each of the embodiments shown in FIGS. 6, 9, and 10, a differential amplifier circuit may be further added to remove error terms after the fifth order term.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a logarithmic amplifier that is suitable for IC implementation and has excellent linearity and temperature characteristics.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram showing a conventional example of a logarithmic amplifier, FIG. 2 is a block diagram showing the basic configuration of the present invention, and FIG. 3 is an electric circuit diagram showing a logarithmic conversion section in an embodiment of the present invention. FIG. 4 is an electric circuit diagram showing a differential amplifier section in an embodiment of the present invention, FIG. 5 is an electric circuit diagram showing an equivalent circuit of the circuit in FIG. 3, and FIG.
The figure is an electric circuit diagram showing the differential amplifier section in the second embodiment of the present invention, Figure 7 is a characteristic curve diagram showing the linearity characteristics of the circuit in Figure 6, and Figure 8 is the equivalent of the circuit in Figure 6. FIG. 9 is an electric circuit diagram showing a third embodiment of the present invention, and FIG. 10 is an electric circuit diagram showing a fourth embodiment of the present invention. 3, 20... Logarithmic conversion section, 4, 21, 28...
Differential amplifier section, 11, 12, 18, 19, 26, 2
7, 33, 34...output terminal, 16, 17, 2
4, 25, 31, 32...constant current source, V ₁ , V ₂ ...
…Differential input voltage, Q ₄₁ , Q ₄₂ , Q _A11 , Q _B11 , Q _B21 ,
Q _A21 , Q _A1 , Q _A2 , Q _B1 , Q _B2 ... Input transistor, Q _A12 ~ Q _A1N , Q _B12 ~ _{Q B1M} , Q _B22 ~ _{Q B2M} , Q _A22
~Q _A2N ... Voltage dividing transistor, R ₃ , R ₄ , R ₅ ,
_R6 ... Compensation resistance.

Claims (1)

[Claims] 1. A logarithmic conversion section that utilizes the voltage-current characteristics of a PN junction of a transistor and has a temperature characteristic in which the difference in output voltage is approximately proportional to temperature; 1. A logarithmic amplifier comprising: a differential amplifier section having a temperature characteristic substantially inversely proportional to temperature; and wherein the temperature characteristic of the logarithmic conversion section is compensated by the temperature characteristic of the differential amplifier section. 2. The differential amplifier section includes voltage dividing means for dividing the input voltage differentially applied to the input transistors, and a constant current source of a current corresponding to the voltage division ratio, and the input voltage is commonly applied and the 2. The logarithmic amplifier according to claim 1, comprising a plurality of differential amplifier circuits in which collector terminals of input transistors are cross-connected to output terminals. 3. The logarithm according to claim 2, which uses as voltage dividing means a number of voltage dividing transistors corresponding to the voltage dividing ratio in series with the input transistor and sequentially connecting the emitter terminal of the previous stage to the base terminal and collector terminal of the next stage. amplifier. 4. The logarithmic amplifier according to claim 2, which uses a resistance dividing circuit as the voltage dividing means. 5 The differential amplifier section includes a compensation resistor, one end of which is connected to a differential input signal, and the other end of which is connected to the base terminal of the input transistor, and an input transistor that is in a differential relationship with the input transistor. 2. The logarithmic amplifier according to claim 1, further comprising a differential amplifier circuit having a current mirror circuit that causes the same current as the collector current to flow through the compensation resistor.