JPS6361710B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image data arbitrary area cutting device for cutting out image data stored in a memory as continuous data.

An image information processing device extracts image data read from a document as two-dimensional data corresponding to a predetermined area of the document, and performs information processing such as enlarging or reducing characters or removing noise based on this data. There are many. For example, to remove noise from image data, some data (1 dot)
Suppose we want to determine the value of . In this case, the surrounding 8
If dots are to be referred to, image data of 3×3 dots is cut out. That is, in this case, a rectangular area with three dots on each side is cut out on the original.

By the way, in image information processing apparatuses, originals are usually read using a raster scanning method. FIG. 1 shows this reading principle. First, one-dimensional image data for a first line _l1 is read from a document 1. Then the second line l ₂
Similarly, one-dimensional image data about the image is read. The same applies below.

FIG. 2 shows how the image data read in this way is stored in the memory. Image data can be 8 bits or 16 bits.
It is stored in the memory 2 in word units such as bits. Image data for each line is composed of a plurality of words. Therefore, the image data of the first line _l1 is stored in the memory 2 in a form divided into several stages in the scanning direction (arrow direction).

When one page of image data is stored in the memory 2 in this manner, image data is cut out for an arbitrary rectangular area 3 of the document 1 shown in FIG. 3. In this diagram,
From the Nth line l _N (N is any integer) to the N+2th line
The image data is cut out for a predetermined portion of the lines up to line l _N+2 . As described above, the image data in the memory 2 is not stored as two-dimensional data. That is, the image data corresponding to the rectangular area 3 is stored in the memory 2 in a distributed form as shown by diagonal lines in FIG. Therefore, when cutting out image data, the data in the memory 2 must be sequentially read out in the sub-scanning direction, and necessary data must be recognized one by one.

On the other hand, for example, Japanese Patent Laid-Open No. 134331/1983 describes a graphic preprocessing device. This graphic preprocessing device is provided with a matrix mesh that stores quantized information of a minute area scanned by the scanning means using a plurality of pixels. The input end of a shift register is connected to the output side of this matrix mesh, and the output end of this shift register is connected to the input end of the matrix mesh. Then, by inputting the binary information obtained by scanning the original figure to the other input terminal of the matrix mesh, this binary information is circulated between the matrix mesh and the shift register. let As a result, the quantized information of the minute area mentioned above is stored intensively in the matrix mesh under predetermined conditions. Therefore, the contents of the matrix mesh at this time can be regarded as the cutout of a predetermined minute area.

However, this matrix mesh has a predetermined shape and size, so if you want to change the size or shape of the minute area to be cut out, you will need to prepare and select another matrix mesh each time. There was a problem that I had to do it.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide an arbitrary region cutting device for image data that can cut out image data of various sizes or shapes stored in a memory as continuous data. do.

In the present invention, (i) a reading unit that reads image data existing in an area on a document to be cut out from memory in word units, and (ii) a plurality of shift registers that store image data in word units are arranged in parallel. and (iii) a shift register in this source register is selected in accordance with the structure of cutting out the image data, and the image data read out by the reading means is transferred to the selected shift register. storage means for storing one word at a time, and (iv) arranged to input in parallel one bit at a time the carry bits output from each shift register constituting the source register, and output from each shift register storing image data. A result register that accommodates only the bits existing in the area to be cut out of the carry bits; and (v) This result register is shifted by one bit in a predetermined direction each time one shift operation of all selected shift registers is completed. The apparatus for cutting out an arbitrary area of image data is provided with a control means for controlling the image data so that the next carry bit is stored in a position where no carry bit has been stored yet. This device cuts out an arbitrary area of image data stored one-dimensionally (bit serially) as continuous bits by supplying necessary data from the image data set in the source register to the result register. becomes possible.

The present invention will be explained below with reference to Examples.

FIG. 5 shows a device for cutting out an arbitrary area of image data. The image data arbitrary area cutting device 5 includes a source register 51 that stores image data read from the memory 2 in units of words. A carry register 52 for storing a carry bit from the source register 51 is arranged on the left side of the source register 51 in the figure. When the source register 51 is shifted to the left, the N shift registers R ₁ that make up the source register 51 are shifted to the left.
The carry bits output from each of _.about.RN are stored in a carry register 52. N pieces of parallel image data 5 outputted from the carry register 52 are combined with a designation signal 6 outputted from the shift control register 53,
An AND circuit 54 performs logical product. Necessary image data 7 output from the AND circuit 54 is supplied to a shift control circuit 56 via an OR circuit 55, and from there to a result register 57. On the other hand, the designation signal 6 output from the shift control register 53 is also supplied to the inverter 58. Inverter 58
The designation signal 8 whose logic state has been inverted is supplied to an AND circuit 59, where it is ANDed with the previous continuous signal 9 output from the result register 57. The output signal 11 output from the AND circuit 59 is the OR circuit 5 described above.
5.

Next, a case will be described in which the image data arbitrary area cutting device is used to cut out the image data in the area surrounded by the dashed line in FIG. 6.
The area 61 cut out in FIG. 6 is a rectangular area of 4×4 dots. In this case, shift registers of the source register 51 shown in FIG. 5 are required for the total number of bits present in the area 61.
For the shift control register 53 and the result register 57, registers capable of accommodating the same number of 16 bits are used.

Now, when the cutting operation is started, the area 61
Four words φW to 3W containing part of are selected, transferred through the bus line 13, and supplied to the source register 51. In the source register 51, the seventh
As shown in Figure A, the 0th word φW is placed in the third register _R3 , the first word 1W is placed in the seventh shift register _R7 , and the second word 2W is placed in the Bth shift register _RB. , and further store the third word 3W in the F-th shift register R _F respectively. At this time, the previously stored image data Bφ to BF remain in the result register 57 as they are. Furthermore, the shift control register 53 does not specify shift registers R ₁ to _RF at this stage. In this state, the source register 51 first performs the first shift operation. As a result, each image data φφ, 1φ,
2φ and 3φ are output as carry bits from the source register 51 along with other image data,
It is stored in the carry register 52. The carry register 52 supplies this to the AND circuit 54 as 16-bit parallel image data 5. AND circuit 54 is shift control register 53
A logical AND is performed for each register with the designation signal 6 output from the register. All signal contents of the shift control register 53 are at L (low) level in this state. Therefore, all the image data 7 output from the AND circuit 54 become L level signals. In this state, all contents of the result register 57 are cleared to L level. Therefore, the output signal 11 of the AND circuit 59 which receives the continuous signal 9 which is all at the L level and the designation signal 8 whose logic state is inverted from the inverter 58 is also all the signal which is at the L level. The OR circuit 55 takes the logical sum of these signals 7 and 11 and outputs an L level signal as the logical sum signal 14. Under this signal state, the shift control circuit 56 outputs image data whose logic state is all at L level to the result register 57. As a result, the result register 57
In this state, the contents of all become L level signals.

When the next shift operation is performed, the image data φ1, 11,
21 and 31 are output together with other image data. These image data are all input into the result register 57 as L level signals in the same manner as described above. source register 51
The same holds true when the next shift operation is performed. FIG. 7B shows a state in which this third shift operation has been performed.

Now, when the source register 51 performs the fourth shift operation, the necessary image data φ3, 13, 23, and 33 are taken into the carry register 52 along with other image data, as shown in FIG. 4C. At the same time, the signal contents of the shift control register 53 change as shown in FIG. That is, image data φ3, 13, 23,
The signal in the shift control register 53 corresponding to the position where 33 is output changes to an H (high) level (indicated by diagonal lines in the figure). Such signal changes within the shift control register 53 are set in advance in relation to the range (area) of data to be extracted. The AND circuit 54 performs a logical product of the image data 5 and the designated signal 6, and as a result, the desired image data φ3, 13, 23, 3 are obtained.
3 is supplied to the OR circuit 55 as image data 7. In this state, only the L level signal is stored in the result register 57. Therefore, the output signal 11 consists entirely of L level signals. The OR circuit 55 takes the logical sum of these signals 7 and 11,
Image data φ3,1 as the logical sum signal 14
Outputs signals that directly represent the signal contents of signals 3, 23, and 33. The shift control circuit 56 inputs these signals 14 to the parallel input terminals of the result register 57, and also inputs the signals 14 to the parallel input terminals of the result register 57.
is shifted upward in the diagram by one bit (FIG. 7D).

In this state, the source register 51 performs the fifth shift operation. As a result, image data φ4,
14, 24, and 34 are stored in the carry register 52 along with other image data. Among these, the image data φ4, 14, 24, and 34 are logically ANDed with the designation signal 6 output from the shift control register 53, and are supplied to the OR circuit 55 as image data 7. On the other hand, after the designated signal 6 has its logic state inverted by the inverter 58 (FIG. 8A), the next consecutive signal 9
(FIG. 8B). The output signal 11 obtained in this way (FIG. 8C) is
A logical OR is performed with image data 7. The OR output signal 14 (FIG. 8D) is supplied to the parallel input terminals of the result register 57. Shift control circuit 56 then shifts result register 57 upward by one bit (FIG. 7E).

After this, the source register 51 performs the sixth shift operation. As a result, image data φ5,1
5, 25, and 35 are stored in the carry register 52 along with other image data. Among these, image data φ5, 15, 25, and 35 are supplied to the OR circuit 55 as image data 7. On the other hand, after the designated signal 6 has its logic state inverted by the inverter 58 (FIG. 9A), the next consecutive signal 9
(FIG. 9B). The output signal 11 obtained in this way (FIG. 9C) is
A logical OR is performed with image data 7. The OR output signal 14 (FIG. 9D) is supplied to the parallel input terminals of the result register 57. The shift control circuit 56 then shifts the result register 57 upward by one bit (FIG. 7F).

The same holds true when the source register 51 performs the seventh shift operation (FIG. 7G). However, in this case, the shift control circuit 56 supplies the result register 57 with a signal to stop the shift operation, so the most recent image data φ3 is not pushed out from the result register 57.

When this seventh shift operation is completed, the cut out image data is serially arranged in the result register 57. Therefore, by outputting this as a parallel 16-bit cutout signal 16, desired image data as shown in FIG. 10 can be obtained. The cutout signal 16 may be transferred to an information processing device (not shown) via the bus line 13, or may be stored in a predetermined area of the line 2.

In the image data arbitrary region cutting device of this embodiment, when necessary image data is being output as image data 5, the contents of the shift control register 53 are not changed. If the contents of the shift control register 53 are changed every time the source register 51 performs a shift operation, it becomes possible to cut out a triangular area 17 as shown in FIG. 11 as continuous image data, for example. However, as will be described later, in this case, care must be taken in selecting the source register 51 in which the image data is set.

Next, in the image data arbitrary region cutting device of this embodiment, the contents of the result register 57 are retained even if the contents of the source register 51 are reset after being shifted several times. Therefore, as shown in FIG. 12, by sequentially storing data from the memory in the source register 51,
Image data spanning two or more words can also be extracted as continuous image data. Furthermore, 16×16 bit image data is stored in the source register 51 (R ₀ to R ₄ ), and a designated signal 6 of all H is sent from the shift control register 53.
If you output the image data without performing a shift operation in the result register 57 and read it every time the shift operation of the source register 51 is performed, the image data rotated 90 degrees to the left as the cutout signal 16 will be output. can be obtained.

Next, a case will be described in which image data that is divided in memory is converted into image data that is continuous in one direction. FIG. 13 shows the data structure before conversion. Image data is arranged in a line of 4 bits each. In this case as well, a register capable of accommodating 16 bits is used as the shift register constituting the source register 51.

When the extraction operation is started, the words φW to 3φ to be converted are selected, transferred through the bus line 13, and supplied to the source register 51. In the source register 51, as shown in FIG. 14A, the 0th word φW is transferred to the third register _R3 , and the first word
1W is stored in the seventh register _R7 , the second word 2W is stored in the _B -th register RB, and the third word 3W is stored in the F-th register _RF . At this time, in the shift control register 53, the signals corresponding to shift registers R ₃ , R ₇ , R _B , and _RF go to H level, and the others go to L level.

When the source register 51 repeats the shift operation three times in this state, the result register 5
Image data is stored in 7 (14th
Figures B-D). The circuit operation for this purpose is the same as that explained in FIG. 7, and the explanation will be omitted. When the source register 51 performs the fourth shift operation,
As shown in FIG. 14E, one word of image data is stored in the result register 57 in a continuous form. At this time, the shift control circuit 56 does not shift the result register 57. When one word of image data is written in the result register 57, if it is read out as the cutout signal 16, the 0th word φW' is obtained as shown in FIG. Following this, if the above operation is repeated three times, the first word will be created as shown in Figure 15.
Words 1W' to 3W' are obtained in the same manner, and the conversion to continuous image data is completed. It does not require any particular explanation that inverse transformation is also possible using the image data arbitrary region cutting device shown in FIG.

Next, the general principle regarding which shift register of the source register 51 stores a word when cutting out image data will be explained. Suppose now that a pentagonal region 18 shown in FIG. 16 is cut out. In FIG. 17, consecutive numbers are assigned to the image data to be cut out for convenience.
The following will explain using these numbers. Since a total of 16 bits of image data exists within the area 18, the number of shift registers in the source register 51 (FIG. 5) is 16.

Now, when the cutting operation starts, area 18
Four words φW to 4W containing a portion of are selected and stored in the source register 51. At this time, the shift register to store the 0th word φW is determined as follows. That is, the maximum bit length between the 0th image data "φ" and the other words 1W to 4W is determined. In this case, it is 2 bits, so two shift registers are skipped and the second
The 0th word 0W is stored in the shift register _R2 of (FIG. 18).

The other words 1W to 4W will be explained based on FIG. 19. FIG. 19 shows how each word is stored in the source register 51. In the source register 51, when the 0th image data "φ" is output as a carrier bit, the 2nd, 6th, A, and D image data "Z", "6", "A", and "D" are output. Ru.
Therefore, the first word 1W is image data “1”
At this stage, the result register 57 is accommodated in shift registers with the minimum number of shift registers interposed therebetween. In this case, there is one shift register in between, so the fourth shift register
The first word 1W is accommodated in _R4 . Next, for the second word 2W, the third image data “3” and the fourth image data “4” and “5”
are image data “2” and image data “6”
Therefore, the second word 2W is accommodated in the eighth shift register _R8 . Similarly, the third word 3W is stored in the C-th shift register _RC , and the fourth word 4W is stored in the F-th shift register _RF .

Five words φW~5W are source register 51
Once stored in the image data, a mask operation is performed using the carry register 52 so that only the necessary image data is supplied to the OR circuit 55. In this case, the signal contents of the shift control register 53 will differ each time the source register 51 performs a shift operation. Other circuit operations have already been explained in detail, so they will be omitted.

As described above, according to the present invention, the image data stored in the memory can be output as continuous image data, so the image data processing circuit becomes simple. Furthermore, since it is possible to cut out image data with a complex shape, it has the advantage that it can be used for various image processing.

In the embodiment, the words of the region to be cut out are inputted as they are into the source register 51, but it is also possible to input only the necessary image data strings with their ends (left end in the figure) aligned. Of course. Furthermore, in the embodiment, a method for detecting the point in time when all the necessary image data has been stored in the result register 57 was not explained;
For example, there is a method of storing a carry bit in advance in the result register 57 and detecting the point in time when the carry bit is output. According to this method, there is no need to manage the number of shifts of the source register 51 using a shift counter.

[Brief explanation of drawings]

FIG. 1 is a plan view for explaining reading of a document using the raster scanning method, FIG. 2 is an explanatory diagram showing the state in which image data read using the raster scanning method is stored in memory, and FIG.
FIG. 4 is an explanatory diagram showing a state in which the same portion is cut out in memory, and FIGS. 5 to 19 are for explaining an embodiment of the present invention. Of these, Fig. 5 is a block diagram of a device for cutting out arbitrary areas of image data, and Fig. 6 is a block diagram of a device for cutting out arbitrary areas of image data.
The figure is an explanatory diagram showing the state of pixels on a document when cutting out into a rectangular shape, and Figure 7 shows the signal state of the source register, etc. when cutting out as shown in Figure 6. A is an explanatory diagram showing a state in which the desired word is stored in the source register, and B is the same diagram.
is an explanatory diagram showing the state after the source register has performed the shift operation three times, C is an explanatory diagram showing the state after the fourth shift operation, and D is an explanatory diagram showing the state after the source register has performed the shift operation for the fourth time. An explanatory diagram showing the state after the fifth shift operation, Figure E is an explanatory diagram showing the state after the fifth shift operation, and Figure F is an explanatory diagram showing the state after the sixth shift operation, 8G is an explanatory diagram showing the state after the seventh shift operation, FIGS. 8A to 8D are explanatory diagrams showing the process of processing signals supplied to the result register in the fifth shift operation, Figure 9 is an explanatory diagram showing the processing process of the signal supplied to the result register in the sixth shift operation, and Figure 10 shows the state in which the rectangular area image data shown in Figure 6 is converted into continuous image data. FIG. 11 is an explanatory diagram showing the state of pixels on a document when cutting out into a triangular shape. FIG. 12 is an explanatory diagram when cutting out image data of two or more words.
The figure is an explanatory diagram showing the state of image data divided in memory, and Fig. 14 shows the signal states of source registers, etc. in the procedure for converting the image data shown in Fig. 13 into continuous image data. Figure A is an explanatory diagram showing the state in which the desired word is stored in the source register, Figure B is an explanatory diagram showing the state after the first shift operation, and Figure C is an explanatory diagram showing the state after the second shift operation. An explanatory diagram showing the state after performing the shift operation. Figure D is an explanatory diagram showing the state after the third shift operation. Figure E shows the state after the fourth shift operation. An explanatory diagram, Fig. 15 is an explanatory diagram showing the state converted into continuous image data, Fig. 16 is an explanatory diagram showing the state of pixels on the document when cutting out into a pentagonal shape, and Fig. 17 is an explanatory diagram showing the state of pixels on the document when cutting out into a pentagonal shape. An explanatory diagram that generalizes the image data existing in a pentagonal area. Figure 18 is an explanatory diagram showing the state in which each word is stored in the source register. Figure 19 is an explanatory diagram showing the image data to be cut out and the storage of these image data. FIG. 2 is an explanatory diagram showing the relationship between a shift register in a source register and a shift register. 2...Memory, 17...Triangular area, 18...Pentagonal area, 51...Source register, 53...
Shift control register, 56...Shift control circuit, 57...Result register, 6
1... area.

Claims (1)

[Scope of Claims] 1. A reading device that reads image data existing in an area on a document to be cut out from a memory in word units, and a plurality of shift registers that store image data in word units, arranged in parallel. Select a source register and a shift register within this source register according to the structure of image data extraction,
Storage means stores the image data read out by the reading means word by word in the selected shift register, and carry bits outputted from each shift register constituting the source register are input in parallel one by one. one shift operation of all the selected shift registers is completed; control means for controlling the result register to be shifted by one bit in a predetermined direction each time the result register is stored so that the next carry bit is stored in a position where no carry bit has been stored, An arbitrary area cutting device for image data, characterized in that only the data is sequentially stored in a result register, and continuous data is created from only the cut out image data.