JPS643063B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present application relates to an integrated circuit with an improved terminal structure.

In the conventional integrated circuit package, all the terminals had the same structure, and the structures of the power supply terminals and the signal terminals were also uniform (for example, see Japanese Patent Publication No. 13112/1983). ). When this is used in high-speed logic circuits or memory circuits, there is a drawback that electromotive force is generated due to the inductance of the terminal that supplies the output current, which acts as a noise voltage on other circuits. For this reason, countermeasures are taken in logic circuits and the like, such as providing a separate terminal for supplying output current.

In FIG. 1, an information signal read out from a memory cell array 1 by a sense circuit 2 is sent to a current switching circuit composed of emitter-coupled transistors Q ₁ and Q ₂ . Transistor _Q3 is an output transistor of the integrated circuit, and its collector current varies depending on the information, and generally 22 mA flows when the logic output is at a high potential, and 4 mA flows when the logic output is at a low potential. In other words, the 18mA current switches quickly.

This current flows through the terminal of the integrated circuit package, and the inductance of this terminal is 10 μH.
It produces an induced voltage of 90mV. (Calculated assuming the output current rise and fall times are 2 ns) In conventional memory integrated circuits, power supply lines 3 and 4 are connected to the same package terminal, so this induced voltage is generated between the memory cell array 1 and the sense circuit. 2 as a noise voltage and may cause malfunction. As a solution to this problem, the power supply line 3
Although there is a solution to separate 4 and 4, the number of terminals increases and the mounting efficiency decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit that satisfies the need to reduce the number of terminals in terms of mounting aspects of memory integrated circuits, etc., and further reduces the noise voltage applied to the memory circuit due to the induced voltage generated when switching the output current. The purpose is to

To achieve the above object, the present invention includes a memory cell array 1, emitter-coupled transistors Q ₁ and Q ₂ that respond to information signals read from the memory cell array 1, and emitter-coupled transistors Q 1 and Q ₂ .
an output transistor Q ₃ whose base responds to a signal at the collector of one transistor Q ₁ of Q ₂ ;
A first operating potential supply line 3 for supplying a predetermined operating potential to the memory cell array 1 and the emitter-coupled transistors Q ₁ and Q ₂ , and a first operating potential supply line 3 for supplying a predetermined operating potential to the output transistor Q ₃ The second operating potential supply line 4 and one branched terminal 1
7A, the other branched terminal 17B, and a common part 17C connected to these branched terminals 17A, 17B, and the branched terminal 17A of the branched terminal 17 and the first operation. A first metal wire 15 that connects the potential supply line 3 and a second metal wire 1 that connects the other branched terminal 17B of the branch type terminal 17 and the second operating potential supply line 4.
5.

Examples of the present invention will be described in more detail below.

FIG. 2 is a plan view showing the terminals of the integrated circuit package 11 of the present invention, and the terminals 16 are of a conventional structure. Terminal 17 and terminal 18 are branch type terminals according to the present application, and here terminal 17 will be described as pads 19, 19A, and 19B provided on integrated circuit 13.
The terminal 17 is connected using the metal wire 15 to supply power, but one of the branched terminals 17A is connected to the first terminal 17A.
The terminal 17B is connected to the pad 19A to which the power supply line 3 shown in the figure is connected, and the other terminal 17B is connected to the pad 19B to which the power supply line 4 shown in FIG. 1 is connected.

Figure 3 shows a conventional terminal 16 and a branch type terminal 1 of the present invention.
7 is a diagram showing the integrated circuit package from the front in order to show the difference in structure of FIG. 7 in more detail. The branched terminals 17A and 17B are the package 1 of the terminal 17.
They are connected at a leg 17C (common part) in a direction perpendicular to the plane of the first part.

By doing this, even if an induced voltage is generated in the power supply line 4 due to switching of the output current, the branch point such as the terminal 17 will not approach the power supply board (not shown) in the mounting board (not shown). Therefore, the potential of the power supply line 17A is constant, and the same effect as when separated can be produced.

[Brief explanation of drawings]

Figure 1 is a circuit diagram for a conventional integrated circuit;
The figure is a plan view of an integrated circuit showing an embodiment of the present invention, and FIG. 3 is a front view thereof.

Claims (1)

[Claims] 1. An integrated circuit comprising: a memory cell array; an emitter-coupled transistor responsive to an information signal read from the memory cell array; and a signal at the collector of one of the emitter-coupled transistors. an output transistor whose base responds; a first operating potential supply line for supplying a predetermined operating potential to the memory cell array and the emitter-coupled transistor; and a first operating potential supply line for supplying a predetermined operating potential to the output transistor. a second operating potential supply line for the branched terminal; a branched terminal having one branched terminal, the other branched terminal, and a common part connected to these branched terminals; A first metal line connecting the terminal and the first operating potential supply line; and a second metal line connecting the other branched terminal of the branch type terminal and the second operating potential supply line. An integrated circuit characterized by: 2. The information signal read from the memory cell array is transmitted to the emitter-coupled transistor via a sense circuit, and the sense circuit is supplied with power from one of the branched terminals of the branch type terminal. An integrated circuit according to claim 1.