JPS644372B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synthesizer type receiving device.

A block diagram of a conventional synthesizer type receiver is shown in FIG. In the figure, a signal radio wave coming from an antenna 1 is amplified by a high frequency amplifier 2, converted to an intermediate frequency by a local oscillator 4 and a frequency mixer 3, passed through an intermediate frequency amplifier 5, and then detected by a detector 6. . This output is further amplified by a low frequency amplifier 7 and reproduced as an audio output by a speaker 8. On the other hand, a part of the output of the local oscillator 4 is supplied to the programmable counter 10 and is frequency-divided according to the frequency division ratio N set by the frequency division ratio setting circuit 13. This output is compared with the output frequency F of the reference frequency generation circuit 9 by the phase comparator 11, and its error component is fed back to the local oscillator 4 via the low-pass filter 12. That is, a phase-locked loop (PLL) circuit 16 is configured, and the local oscillator 4 has a frequency of N×F.
It will oscillate stably at .

By the way, since the frequency division ratio setting circuit 13 is controlled by the channel selection pulse generator 15, the state changes every time an up or down pulse 17, 18 occurs, and the frequency division ratio N changes each time. Ta. At this time, the time interval between the generation of tuning pulses is
There is no problem if the response time is sufficiently long compared to the response time of 6, but if the former becomes shorter than the latter,
The frequency division ratio will be changed one after another before the PLL circuit 16 completely responds, and if this continues, the PLL circuit 16 will not be able to keep up with the rotation of the pulse generator 15, and the received sound The disadvantage was that it became very unstable. In addition, the frequency division ratio setting circuit 13 also has a limit in its response speed to input pulses, and if the repetition rate of up or down pulses 17 and 18 becomes faster than a certain value, it will no longer be able to follow changes beyond that, and pulse generation will occur. Vessel 1
There was an inconvenience that the rotational operation speed of No. 5 and the actual frequency change speed did not correspond.

The present invention eliminates the above-mentioned drawbacks, and will be described below with reference to drawings of embodiments.

FIG. 2 shows an embodiment of the present invention. In the same figure, the output of the pulse generator 15 is supplied to an up-down counter 21, and this output is supplied to a latch circuit 20.
The signal is supplied to the frequency division ratio setting circuit 13A through the.

The counter 21 changes state in response to input pulses, and its output is read by a latch circuit 20 every time T by a latch pulse generated by a periodic pulse generator 22. The value read by the latch circuit 20 is held until the next latch pulse.

The frequency division ratio setting circuit 13A operates so that each time a new value is read into the latch circuit 20, the previous value and this new value are added (or subtracted), and this becomes the new frequency division ratio N.

Therefore, if the time T is made longer than the response time of the PLL circuit 16, the PLL circuit 16 will reliably follow the frequency division ratio N every time T. Note that the addition or subtraction time in the frequency division ratio setting circuit 13A is sufficiently smaller than the time T.

Immediately after the output of the counter 21 is read into the latch circuit 20, the counter 21 is reset by a reset pulse generated from the periodic pulse generator 22.
is reset and counts the input pulses from the pulse generator 15 again.

Thereafter, as mentioned above, the output of the counter 21 is read into the latch circuit 20 by the latch pulse, and is added (or subtracted) by the frequency division ratio setting circuit 13A.
Therefore, the number of pulses generated by the pulse generator 15 matches the number of increases and decreases in the frequency division ratio set by the frequency division ratio setting circuit 13A.

This ensures that the actual frequency is
will be reliably controlled.

That is, as in the conventional example described above, the pulse generator 1
This eliminates the inconvenience that the rotational operation speed of No. 5 does not correspond to the actual frequency change speed.

As described above, according to the present invention, the number of pulses generated from the channel selection pulse generator 15 is counted at each time T, and the frequency division ratio N is increased or decreased according to the counted value, and is set in this way. Since the PLL circuit reliably responds in accordance with the divided frequency ratio N, the pulse generator 15 not only allows the frequency to be reliably controlled, but also prevents the received sound from becoming unstable during tuning. It has excellent features such as the absence of

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional synthesizer-type receiver, and FIG. 2 is a block diagram of a main part showing an embodiment of the synthesizer-type receiver of the present invention. 3...Frequency mixer, 16...PLL circuit, 4...Tuning local oscillator, 10...Programmable counter, 1
1... Phase comparator, 13... Frequency division ratio setting circuit, 15...
Tuning pulse generator, 20...Latch circuit, 21...Up-down counter, 22... Periodic pulse generator.

Claims (1)

[Claims] 1 In a receiving device having a local oscillation circuit controlled by a phase-locked loop circuit, there is a tuning pulse generator that generates an up pulse or a down pulse depending on input for tuning, a periodic latch pulse, and a pulse generator that generates a periodic latch pulse and a pulse that follows the latch pulse. a periodic pulse generator that generates a reset pulse; a counter that counts up or down pulses from the channel selection pulse generator and is reset by the reset pulse from the periodic pulse generator;
A latch circuit reads the output of the counter by a latch pulse generated by the periodic pulse generator, and each time the value of the output of this latch circuit changes, the value already set in this latch circuit and the value of the latch circuit are and a frequency division ratio setting circuit that sets a frequency division ratio of a programmable counter constituting the phase-locked loop circuit as a frequency division ratio N by adding or subtracting the frequency division ratio of the programmable counter. A synthesizer type receiving device characterized in that the oscillation frequency is changed by.