JPS5826849B2 - Frequency sweep receiver using PLL oscillator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a frequency sweep receiver that uses a PLL oscillator as a local oscillator, and an object thereof is to prevent malfunctions during periods when the PLL oscillator is out of synchronization.

The circuit of a frequency sweep receiver using a PLL oscillator as a local oscillator generally has a high frequency amplification stage 1, a frequency conversion stage 2, an intermediate frequency amplification stage 3, a detection number 4, and a squelch or AGC control voltage generation stage 5, as shown in FIG. signal circuits such as, sweep oscillator 6, sweep control gate 7, control code generation counter 8
, control code offset correction stage 9, PLL oscillation stage 10
The sweep operation is started by applying a sweep start signal to the gate 7, and stopped by a sweep stop signal derived from the squelch control voltage or the AGC control voltage.

The PLL oscillator consists of a reference frequency oscillator, a voltage controlled oscillator, a programmable frequency divider, and a phase detector.The frequency of the voltage controlled oscillator is determined according to the frequency setting code input to the programmable frequency divider, but during the transient period when the frequency changes. Since the oscillation frequency may change unspecified and cause unnecessary output from the receiver, the receiver output is stopped using the unlock signal generated by the phase detector during this out-of-synchronization period. This is a commonly used method.

However, since this alone is not sufficient for a frequency sweep receiver, the circuit configuration and operation of the present invention will be explained below.

(1) Figure 2 shows a configuration example in which a voltage such as a squelch control voltage whose rise and fall are synchronized with the input signal is used as the sweep stop signal. Another control gate 1 is located between the sweep control gate 7 and the sweep control gate 7.
1 is provided, and an unlock signal generated during the out-of-synchronization period of the PLL oscillator is added to this to inhibit the operation of the gate 11, thereby eliminating a malfunction of the sweep stop.

(2) When using the AGC control voltage for the sweep stop signal, the AGC control voltage generation stage force normally has a time constant so that the rise is fast and the fall is relatively slow. , AG once due to unnecessary signals and noise
When C voltage is generated, P
There is a possibility that the unlock signal of the LL oscillator disappears and the sweep malfunctions, or that the gain of the signal circuit is not sufficiently recovered and the normal signal is ignored.

Therefore, as shown in FIG. 3, the unlock signal of the PLL oscillator is passed through the signal expansion circuit 12 to the control gate 11 and the sweep counter 8. Malfunctions can be prevented by configuring the circuit to stop the sweep.

Note that the unlock signal passed through the signal expansion circuit 12 may be added to the sweep oscillator 6 to stop the oscillation.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a frequency sweep receiver using a PLL oscillator as a local oscillator, and FIGS. 2 and 3 are circuit diagrams of a frequency sweep receiver according to the present invention. 1... High frequency amplification stage, 2... Frequency conversion stage, 3... Intermediate frequency amplification stage, 4...
Detection stage, 5...Squelch or AGC control voltage generation stage, 6...Sweep oscillator, 7...Sweep control gate, 8...Control code generation counter, 9...Offset correction stage, 10...
・PLL oscillator, 11... Control gate, 12.
...Signal expansion circuit.

Claims (1)

[Claims] 1. Using a programmable frequency divider, a PLL oscillator whose oscillation frequency is set by inputting a digital code is used as a local oscillator, and the oscillation frequency of the local oscillator is swept and changed according to a predetermined program to check the presence or absence of a desired signal. In the receiver circuit to be searched, a squelch control voltage whose rise and fall are synchronized with the input signal is used as the sweep stop signal, and input of the sweep stop signal is prohibited while the PLL oscillator unlock signal is being generated. A frequency sweep receiver using a PLL oscillator. 2. In a receiving circuit that uses a programmable frequency divider and uses a PLL oscillator whose oscillation frequency is set by inputting a digital code as a local oscillator, and searches for the presence or absence of a desired signal by sweepingly changing the oscillation frequency of the local oscillator according to a predetermined program, A frequency sweep receiver using a PLL oscillator, characterized in that an AGC control voltage that is delayed by a time constant is used as a sweep stop signal, and the sweep is stopped for a predetermined time after an unlock signal of the PLL oscillator is generated.