JPS648346B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for driving a display device such as a bar graph. Currently, bar graph display devices using liquid crystals are used in a wide variety of fields, and examples include the following. For example, FIG. 1 shows three rows of display sections S ₁ , S ₂ , S ₃ that display independent data, and in order to reduce the number of lead wires, each segment electrode group S ₁₁ ...S ₁₆ ,S ₂₁ ...
S ₂₆ , S ₃₁ ... Connect S ₃₆ to 10 lead wires like the second
_P0 ...Connected with _P9 . Each segment electrode group
S ₁₁ ...S ₁₆ , S ₂₁ ...S ₂₆ , S ₃₁ ...S ₃₆ have common electrodes C ₁₁ ...C ₁₆ , C ₂₁ ...C ₂₆ ,
C ₃₁ ...C ₃₆ are opposed to each other with a liquid crystal (not shown) interposed therebetween. Conventionally, the following methods have been used to drive the display device. For example, when displaying as shown in Fig. 1, display blocks B ₁₃ . . . B ₁₆ , B ₂₅ , which deselect all display segments are used.
Common electrode of B ₂₆ , B ₃₄ , B ₃₅ , B ₃₆ C ₁₃ ...C ₁₆ ,
Lead wire q ₁₃ of C ₂₅ , C ₂₆ , C ₃₄ , C ₃₅ , C ₃₆ ...
The control signal _a1 shown in FIG. 4 is constantly supplied to q ₁₆ , q ₂₅ , q ₂₆ , q ₃₄ , q ₃₅ , and q ₃₆ . Also, the common electrodes C ₁₁ , C ₂₁ , C ₂₂ , C ₂₃ , C ₃₁ , C ₃₂ of the display blocks B ₁₁ , B ₂₁ , B ₂₂ , B ₂₃ , B ₃₁ , B ₃₂ to select all the display segments Lead
Control signal _a2 is constantly supplied to _q11 , _q21 , _q22 , _q23 , _q31 , and _q32 . Furthermore, display blocks B ₁₂ and B in which display segments to be selected and display segments that are not selected are mixed.
₂₄ , B ₃₃ common electrode C ₁₂ , C ₂₄ , C ₃₃ lead wire q ₁₂ ,
The control signal a ₃ is sequentially supplied to q ₂₄ and q ₃₃ in a time-sharing manner, and the control signal a ₁ is supplied at other times.
For example, at time _t1 , the control signal _a3 is supplied to the common electrode _C12 , and the control signal _a1 is supplied to the supply electrodes _C24 , _C33 , and at time _t2 , the control signal a1 is supplied to the common electrode _C24. The control signal a ₁ is supplied to the common electrodes C ₁₂ and C ₃₃ by the signal a ₃ . Then, at time _t3 , the control signal _a3 is supplied to the common electrode _C33 , and the common electrodes _C12 ,
A control signal _a1 is supplied to _C24 . On the other hand, the control signals a ₄ and a ₅ are selectively supplied to the lead wires P ₀ and P ₉ in FIG. 2 in synchronization with the supply of the control signal a ₃ to the common electrodes C ₁₂ and C ₃₃ . be. That is, at time _t1 , the control signal _a5 is supplied to the lead wires _P0 , _P1 , _P2 , and the control signal _a4 is supplied to the lead wires _P3 ... _P9 . This results in display block B ₁₂
A response signal _a6 is applied to the lower seven display segments. On the other hand, _a non-response signal _a8 or _a9 is applied to the display segments _of display blocks B24 and B33 . Also, at time _t2 , the lead wire _P0 ... _P4
By supplying the control signal _a5 to the lead wires _P5 ... _P9 and the control signal _a4 to the lead wires P5...P9, the response signal _a6 is applied to the lower five display segments of the display block _B24 , and the other A non-response signal _a7 is applied to the display segment. At this time, either non-response signal a ₈ or a ₉ is applied to the display segment of display block B ₁₂ or B ₃₃ . Furthermore, at time _t3 , by supplying the control signal _a4 to the lead wires _P0 , _P1 and the control signal _a5 to the lead wires _P2 ... _P9 , the lower two display segments of the display block B33 are controlled _. A response signal _a6 is applied to the other display segments, and a non-response signal _a7 is applied to the other display segments.
At this time _, either non-response signal _a8 or _a9 is applied to the display segment of display block B12 _or B24 . On the other hand, the display blocks to be selected are B ₁₁ , B ₂₁ , B ₂₂ ,
The display segments B ₂₃ , B ₃₁ , and B ₃₂ contain response signals.
Either a ₁₀ or a ₁₁ is constantly applied, and unselected display blocks B ₁₃ , ... B ₁₆ , B ₂₅ , B ₂₆ , B ₃₄ , B
The display segments of ₃₅ , B ₃₆ , and non-response signals a ₈ ,
Either a ₉ is applied. However, this requires a decoder and a drive circuit for selecting a common electrode for each display section, making the circuit configuration complicated. Also, since five different voltages are required, the power supply circuit becomes complicated.
Furthermore, in order to equalize all the effective values of the voltages applied to the display segments to be selected, the control signal a is applied to a voltage √38·V, (3− √38) Contains V. If these voltages were to be obtained by resistor division, the dividing resistor would have to be made sufficiently smaller than the resistance value of the liquid crystal, which would increase current consumption by the resistors, making it undesirable. Furthermore, it is necessary to change the waveform of the control signal _a2 depending on the number of display sections. In other words, when the number of display sections changes, the effective value of the voltage applied to the display segment to be selected in the display block in which selection and non-selection are mixed changes, and the effective voltage value of the response signals a ₁₀ and a ₁₁ is kept the same. This is because it has to be done. Therefore, each time the number of display sections changes, the configuration of the control signal generation circuit must be changed. Therefore, the present invention selects a plurality of display sections two by two in a time-sharing manner so that they can be driven with only voltages of 0, V, and 2V, and uses a common control signal even if the number of display sections changes. This allows for a large operating margin. An embodiment of the present invention will be described below based on the drawings. In Figure 5, OSC is a crystal oscillator, D is a frequency divider, and RC is a timing pulse generator consisting of a ring counter, etc., and its output terminals r ₁ , r ₂ , r ₃ generate pulses for time division. However, from terminal r ₀ , a narrow pulse is generated every time a pulse is generated from terminals r ₁ , r ₂ , and r ₃ . PG is a signal generation circuit, RS ₁ ... RS ₆ are registers, and registers RS ₁ , RS ₂ , and RS ₃ are display sections S ₁ , S ₂ , and S ₃ respectively.
The data of the first place is stored in registers RS ₄ , RS ₅ ,
RS ₆ stores the 10th data of the display section, S ₁ , S ₂ , and S ₃ . SE ₁ ... SE ₄ are selection circuits, DE ₁ ... DE ₄ are decoders, CT ₁ and CT ₂ are control circuits, and L ₁ ... L ₄ are latch circuits. RS ₁ ,
RS ₂ and RS ₃ are signal selection circuits, and SW is a switching circuit. 6, 7 and 8 respectively show a signal selection circuit PS ₁ , a signal selection circuit PS ₂ and a switching circuit SW. In each figure, G ₁ ...G ₁₀ are gate circuits, TG ₁ ...TG ₂₂ is the transmission gate, VT ₁ ,
VT ₂ and VT ₃ are inverters. Next, the operation will be explained. Terminals Sss, Ssn, Sns, Snn, Cn of the signal generation circuit PG in Fig. 5,
From Cma, Cmb, and Cs, the first segment electrode selection signal b ₁ , the second segment electrode selection signal b ₂ , and the third segment electrode selection signal in FIG. 9 are respectively obtained.
b ₃ , segment electrode non-selection signal b ₄ , common electrode non-selection signal b ₅ , first common electrode selection signal b ₆ , second common electrode selection signal b ₇ and common electrode all selection signal b ₈ are set to occur. It has been done. Since each of the signals b ₁ ...b ₈ is configured with a voltage of 0, V, or 2V, the power supply circuit can be the simplest booster circuit. Furthermore, the signals _b1 ... _b7 are all at the same potential (in this example, 0) at the same timing (third scale from the left in the figure), and the signal _b8 is configured to have a different potential at this timing. has been done. First, at time t ₁ , when a pulse is generated from terminal r ₁ of the timing pulse generator RC in FIG.
Selection circuit SE ₁ ... SE ₄ registers respectively.
The outputs of RS ₁ , RS ₂ , RS ₄ and RS ₅ are selected, that is, the data on display sections S ₁ and S ₂ in FIG. 1 are selected.
Next, when a pulse is generated from terminal _r2 at time _t2 , the outputs of registers _RS2 , _RS3 , _RS5 , and _RS6 are selected by selection circuits _SE1 ... _SE4 , respectively, and
The data in display sections S ₂ and S ₃ are selected. Further time t ₃
When a pulse is generated from the terminal _r3 , the selection circuits _SE1 ... _SE4 select the registers RS3 _{and RS3} , respectively.
The outputs of RS ₁ , RS ₆ , and RS ₄ are selected, and the display section S ₃ ,
The data in S ₁ is selected. First register by a pulse from terminal r ₁
When the outputs of RS ₁ , RS ₂ , RS ₄ , and RS ₅ are selected,
Each output is supplied to decoders DE ₁ , DE ₄ , and the outputs of decoders DE ₃ , DE ₄ are latched into latch circuits L ₃ , L ₄ by pulses from terminal r ₀ of timing pulse generator RC. Ru. On the other hand, decoder DE ₁ ,
The output of DE ₂ is supplied to the control circuits CT ₁ and CT ₂ , and when the data at the 10th place on the display sections S ₁ and S ₂ is an even number, the output from the terminals d ₁₀ , d ₁₉ , d ₂₀ , ... d ₂₉ occur at the terminals e ₁₀ ...e ₁₉ , e ₂₀ ...e ₂₉ , respectively, and when the number is odd, the outputs from the terminals d ₁₀ ... d ₁₉ , d ₂₀ ... d ₂₉ are generated at the terminals e ₁₉ ... e ₁₀ , e, respectively. ₂₉ ……e It is something that occurs in ₂₀ . This is because each segment electrode group is connected in a zigzag manner with a common lead wire, and the lead wires are connected in the reverse order for even-numbered segment electrode groups and odd-numbered segment electrode groups. . Therefore, when displaying as shown in FIG. 1, since the 10th place of the data on the display sections S ₁ and S ₂ are both odd numbers, the terminals d ₁₀ of the decoders DE ₁ and DE ₂ ...
d ₁₉ , d ₂₀ ...output of d ₂₉ (1111111000),
(1111100000) are generated at the terminals e ₁₉ ... e ₁₀ , e ₂₉ ... e ₂₀ of the control circuits CT ₁ and CT _2, respectively, and the latch circuit
L ₁ , L ₂ and is latched by the above pulse from terminal r ₀ . Thus, with the generation of a pulse from terminal r ₁ ,
The decoded output of the data at the 1st position of the display sections _S1 and _S2 is latched in the latch circuits _L1 and _L2 , and the decoded output of the data at the 10th position is latched in the latch circuits _L3 and _L4 . Therefore, signals b ₅ ... b ₈ are selectively supplied to the common electrodes C ₁₁ ...C ₁₆ , C ₂₁ ...C ₂₆ by the outputs of the latch circuits L ₃ and L ₄ as follows. It is something. Output terminals _m1 ... _m6 of latch circuit _L3 are display parts
When the data at the 10th place of S ₁ is 0...5, each terminal
m ₁ , m ₁ , m ₂ , m ₁ , m ₂ , m ₃ ... m ₁ ... m ₆ are "1", and when displaying up to the 17th as shown in Figure 1, , terminals m ₁ , m ₂ in Figure 7
becomes “1”. Therefore, the outputs of gate circuits G ₆ and G ₇ become "1", transmission gates TG ₇ and TG ₉ are turned on, and terminals M ₁ and M ₂ are connected to terminals Cs and TG 9, respectively.
A common electrode full selection signal b ₈ and a common electrode non-selection signal b ₆ from Cma are generated. On the other hand, a common electrode non-selection signal _b5 from the terminal Cn is generated at the terminals _M3 ... _M6 .
That is, when the data at the 10th place on the display section _S1 is 0...5, signals are generated at the terminals _M1 ... _M6 as shown in FIG. 10, respectively. Also, from the terminals N ₁ ... N ₆ of the signal selection circuit PS ₃ ,
When the data at the 10th position on the display section _S2 is 0...5, the common electrode non-selection signal _b5 , the second common electrode selection signal _b7 , and the common electrode all selection signal _b8 are generated as shown in FIG. It is something. Then, the signals from the terminals M ₁ ...M ₆ , _{N 1} ... _{N 6} are supplied to the switching circuit SW, and as shown in FIG. 8, the signals from _{the terminals M 1 . 17} , supplied to TG ₂₁ .
Since a pulse is now being supplied to terminal r ₁ , transmission gates TG ₁₄ , TG ₁₇ , and TG ₂₀ are turned on, and the terminal
Signals from Mj and Nj (j=1, 2...6) are sent to the common electrodes C 1j and C _1j in FIG. 3 via terminals q ₁ j and q ₂ j, respectively.
A common electrode non-selection signal b ₅ from the terminal _Cn is supplied to the common electrode C _3j via the terminal q _3j . In other words, at time t ₁ , A, B, C in Fig. 12
Common electrodes C ₁₁ ... C ₁₆ , C ₂₁ ... C ₂₆ , C ₃₁
...The signal is supplied to _C36 . On the other hand, the terminals l _{10 ,} l ₂₀ ... l ₁₉ , of the latch circuits L 1 and L ₂
The output terminals _P0 ... _P9 of the signal selection circuit _PS1 are supplied with the first segment electrode selection signal _b1 , the second segment electrode selection signal _b2 , and the third segment electrode by the output from _l29 . The selection signal b ₃ and the segment electrode non-selection signal b ₄ are generated as follows. Now, terminals l ₁₀ ... l ₁₉ , l ₂₀ ... l ₂₉ of latch circuits L ₁ and L ₂ are held at (0001111111) and (0000011111), respectively, and looking at the signal generated at terminal P ₀ ,
Since the terminals l ₁₀ and l ₂₀ are "0", the transmission gate TG ₄ is turned on by the output of the gate circuit G ₄ of FIG. 6. Therefore, as shown in FIG. 12D, a segment electrode non-selection signal _b4 from the terminal Snn is generated at the terminal _P0 . Similarly, the terminals l ₁₁ , l ₂₁ , l ₁₂ , l ₂₂ are also “0”
Therefore, the segment electrode non-selection signal _b4 is also supplied to the terminals _P1 and _P2 . Also, since the terminals l ₁₃ and l ₂₃ are "1" and "0", respectively, the transmission gate TG ₂ is turned on by the output of the gate circuit G ₂ in FIG. 6, and the terminal P ₃ is connected to the terminal Ssn. A second segment electrode selection signal b ₂ is generated at the terminal P 4 , and a signal b ₂ is also generated at the terminal P ₄ . Furthermore, terminals l ₁₅ ... l ₁₉ , l ₂₅ ... l ₂₉
are all "1", so the first segment electrode selection signal _b1 from the terminal Sss is generated at the terminals _P5 ... _P9 . Therefore, each display segment of display section _S1 has
Signals are applied as shown in FIG. 13, among which the response signals b ₉ , b ₁₀ , b ₁₂ of FIG. 9 are applied to the display block B ₁₁ .
is applied. Also, response signals b ₁₇ and b ₁₈ are applied to the lower seven display segments of the display block B ₁₂ , and a non-response signal is applied to the upper three display segments.
b ₂₀ is applied. Further display blocks B13 ... B16 contain response _{signals .}
b ₂₁ , b ₂₂ , and b ₂₄ are applied. On the other hand, a signal is applied to each display segment of the display section _S2 as shown in FIG. 14, and _the display blocks B21 , B
A response signal is applied to each of the display segments ₂₂ and B ₂₃ , a response signal is applied to the lower five display segments of display block B ₂₄ , and a non-response signal is applied to the other display segments. Further, non-response signals b ₂₁ , b ₂₂ , and b ₂₄ are applied to each display segment of the display section S ₃ . Next, at time _t2 , when a pulse is generated from the terminal _r2 of the timing pulse generator RC, the outputs of the registers _RS2 and _RS3 are selected and the outputs of the decoders _DE1 ,
At the _same time, the outputs of registers RS ₄ and RS ₅ are selected and supplied to decoders DE ₃ and DE ₄ . The outputs of decoders DE ₁ and DE ₂ are connected to control circuits CT ₁ and
The outputs of the decoders DE ₃ and DE ₄ are latched to the latch circuits L 1 and L 2 via CT ₂ , and the outputs of the decoders DE ₃ and DE ₄ are latched to the latch circuits L ₃ and L ₄ . Therefore, terminals m ₁ of latch circuits L ₃ and L ₄
...m ₆ , n ₁ ... n ₆ are each (111100),
(111000), and the terminals of signal selection circuits PS ₂ and PS ₃
M ₁ ...M ₆ , N ₆ ...N ₆ have signals b ₈ ,
b ₈ , b ₈ , b ₆ , b ₅ , b ₅ , b ₈ , b ₈ , b ₇ , b ₅ , b ₅ , b ₅ are generated. The switching circuit of FIG. ₈ connects the transmission gates TG ₁₅ , TG ₁₈ ,
Since TG ₂₁ is on, terminals M ₁ ... M ₆
The signals from the terminals are supplied to the common electrodes C ₂₁ ...C ₂₆ via terminals q ₂₁ ... q ₂₆ , respectively. One terminal N ₁ ...
...N ₆ are respectively supplied to common electrodes C ₃₁ ...C ₃₆ via terminals q ₃₁ ... q ₃₆ . Further terminal
q ₁₁ ... q ₁₆ is the common electrode non-selection signal from terminal Cn.
_b5 is generated and supplied to the common electrodes _C11 ... _C16 . Thus, at time _t2 , signals are supplied to each common electrode as shown in FIG. 12A, B, and C. On the other hand, a signal is selected from the signal selection circuit PS ₁ by the outputs of the latch circuits L ₁ and L ₂ in the same manner as above,
A signal is generated at the terminals P _{0 .} . . P ₉ as at time t ₂ in FIG. 12D. As a result, a response signal is applied to the hatched display segments of the display sections S ₂ and S ₃ in FIG. 1, and a non-response signal is applied to the other display segments. Further, a non-response signal is applied to each display segment of the display section _S1 . Next, at time _t3 , when a pulse is generated from terminal _r3 of the timing pulse generator RC, the display
Data S ₃ and S ₁ are selected, and based on this data, signals are supplied to each common electrode and terminals P _{0 .} . . P ₉ as at time t ₃ in FIG. 12A . As a result, a response signal is applied to the hatched display segments of display portions S ₃ and S ₁ , and a non-response signal is applied to the other display segments. Further, a non-response signal is applied to each display segment of the display section _S2 . As described above, two display sections are selected in a time-sharing manner. By the way, looking at the effective voltage value of the signal applied to each display segment, a response signal is applied to the display segment to be selected for two-thirds of one period of time division, and a non-response signal is applied for one-third. is applied, and its effective value becomes √119. Further, a non-response signal is always applied to non-selected display segments, and its effective value is √13. Therefore, the operating margin, which is the ratio of both effective values, is √113, which can be large, so that a display with good contrast can be performed. Although the above embodiment describes the case where three display units are driven, the present invention is not limited to this, and four or more display units may be driven in the same manner. In this case as well, the same control signal as above can be used, and if the number of display sections is N, the operating margin is expressed as √(8+). Further, in the above embodiment, a bar graph display has been described, but the present invention is not limited to this, and the present invention may be used to display hours, minutes, seconds, etc. by arranging three display sections concentrically. As described in detail above, according to the present invention, a plurality of display sections that perform integration display are sequentially selected and driven two by two in a time-sharing manner, and each display segment is controlled by voltages of 0, V, and 2V. A simple booster circuit can be used as the power supply circuit, the configuration can be simplified, and the device can be driven at a low voltage. Moreover, since the operating margin of the signal applied to the selected and non-selected display segments can be increased to √(8+) (N is the number of display sections), there is no cross stroke and good contrast can be obtained. Furthermore, even if the number of display sections changes, there is no need to change the waveform of the control signal, so there is no need to change the design of the control signal generation circuit.

[Brief explanation of drawings]

FIG. 1 is a front view of the display section, FIGS. 2 and 3 are explanatory diagrams showing segment electrodes and common electrodes, respectively, FIG. 4 is a signal waveform diagram according to the conventional driving method, and FIG. 5 is a diagram showing the signal waveforms according to the present invention. FIGS. 6, 7 and 8 are block diagrams showing the circuit configuration of one embodiment, and FIGS. 9 and 9 are logic circuit diagrams showing the main parts of FIG.
The figure is a signal waveform diagram showing an example of a signal waveform according to the present invention, and FIGS. 10 to 14 are signal explanatory diagrams for explaining the operation. _{S1 , S2 , S3: display section, B11 to} B16 , _B21 to _B26 ,
_B31 to B36 : Display block , S11 _{to S16} , S21 _{to S
26} : Segment electrode group, C ₁₁ to C ₁₆ , C ₂₁ to _{C 26} , C ₃₁
~ _C36 : common electrode, _b1 : first segment electrode selection signal, _b2 : second segment electrode selection signal,
b ₃ : Third segment electrode selection signal, b ₄ : Segment electrode non-selection signal, b ₅ : Common electrode non-selection signal,
b ₆ : first common electrode selection signal, b ₇ : second common electrode selection signal, b ₈ : common electrode all selection signal, b ₉ to b ₁₃ ,
b ₁₅ , b ₁₇ , b ₁₈ : response signal, b ₁₄ , b ₁₆ , b ₁₉ to _{b 24} :
Non-response signal.

Claims (1)

[Scope of Claims] 1. N (N is an integer of 2 or more) display blocks each including a common electrode and a group of segment electrodes facing the common electrode via a liquid crystal to perform integrated display. It has a display section, each of the segment electrode groups is connected by a common lead wire, two of each of the display sections are sequentially selected in a time-sharing manner, and a voltage of 0, Any of the common electrode non-selection signal b ₅ , the first common electrode selection signal b ₆ , the second common electrode selection signal b ₇ , and the common electrode full selection signal b ₈ consisting of at least any two voltages among V and 2V. A first segment electrode selection signal consisting of at least two voltages among voltages 0, V and 2V is supplied to the segment electrodes selectively.
b ₁ , the second segment electrode selection signal b ₂ , the third segment electrode selection signal b ₃ and the segment electrode non-selection signal b ₄ to apply a response signal to a desired liquid crystal; The common electrode non-selection signal b ₅ is supplied to each common electrode of the display section, and a non-response signal is applied to all the liquid crystals, and the common electrode non-selection signal b ₅ and the first common electrode selection signal b ₆ , the second common electrode selection signal b ₇ ,
the first segment electrode selection signal b ₁ , the second segment electrode selection signal b 1 ;
The segment electrode selection signal b ₂ , the third segment electrode selection signal b ₃ and the segment electrode non-selection signal b ₄ all have portions that are at the same potential at the same timing, and the common electrode all selection signal b ₈ is a potential different from the same potential at the above timing, and the common electrode non-selection signal b ₅ , the first segment electrode selection signal b ₁ , and the second segment electrode selection signal b ₂ , the third segment electrode selection signal
a non-response signal applied to the liquid crystal due to the potential difference between b ₃ and the segment electrode non-selection signal b ₄ ; the first common electrode selection signal b ₆ and the third segment electrode selection signal b ₃ ; A non-response signal applied to the liquid crystal due to the potential difference between the segment electrode non-selection signal _b4 , the second common electrode selection signal _b7 , the second segment electrode selection signal _b2 , and the segment electrode non-selection signal. The non-response signal applied to the liquid crystal due to the potential difference with the signal _b4 has the same effective voltage value, and the common electrode all selection signal _b8 , the first segment electrode selection signal _b1 , and the second segment electrode selection signal b ₂ , the third segment electrode selection signal
a response signal applied to the liquid crystal due to the potential difference between b ₃ and the segment electrode non-selection signal b ₄ ; the first common electrode selection signal b ₆ and the first segment electrode selection signal b ₁ ; a response signal applied to the liquid crystal due to a potential difference between the segment electrode selection signal b ₂ of the second common electrode selection signal b ₇ and the first segment electrode selection signal b ₁ of the third segment electrode; The response signal applied to the liquid crystal due to the potential difference with the selection signal _b3 has the same effective voltage value, and the ratio of the effective voltage value of the non-response signal and the response signal is √(8+). A method for driving a display device.