JPH0113764B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD OF THE INVENTION The present invention relates to a digital filter that can efficiently perform filter operations when input data and operation results are stored in a memory and the filter operations are executed. Prior Art and Problems In a digital filter, the required output is obtained by multiplying input data and operation results by sequentially delayed signals by a certain sampling time, and adding the obtained results. . Figure 1 shows two examples of digital filters.
This figure shows the configuration of the following cyclic digital filter. In the figure, Z ^-1 is the sampling time delay element, x _o is the current sample input, x _o - ₁ is the input one sample before, x _o - ₂ is the input two samples before,
y _o is the filter output for the current sample, y _o - ₁ is the filter output from one sample before, y _o - ₂ is the filter output from two samples before, and a, b, c, e, f are coefficients. With this configuration, the transfer function shown in the following equation can be realized. y _o =a+bZ ^-1 +cZ ^-2 /1+eZ ^-1 +fZ ^-2 _{x oIn} the digital filter shown in Fig. 1, the delay element Z ^-1 has conventionally been constructed of, for example, a shift register, and therefore the amount of hardware has been reduced. It was impossible to avoid an increase in Therefore, it has been considered to perform filter operations using a read/write memory (hereinafter abbreviated as RAM) without using a register or the like as a delay element. FIG. 2 shows the configuration of an arithmetic circuit that performs filter operations using a conventional RAM. In the figure, 1 is a read-only memory (hereinafter abbreviated as ROM) that stores coefficients, 2 is a coefficient addressing circuit that specifies addresses in ROM 1, and 3 is a memory that stores input data and calculation result data.
RAM, 4 is an address designation circuit that specifies an address in RAM 3, 5 is an arithmetic unit, and in the arithmetic unit 5, the data stored in RAM 3 is multiplied by the coefficient stored in ROM 1 to perform calculations. Filter operations are performed by storing the results in the RMA 3 and performing operations such as addition and multiplication using the data of the operation results. The calculation procedure when the arithmetic circuit of FIG. 2 performs the calculation of the digital filter shown in FIG. 1, for example, is as shown in the following table.

[Table] As shown in Table 1, the calculation procedure consists of the operations including the five multiplications shown in ~, and the input data and operation results shown in ~ stored in RAM for filter operation in the next sampling period. It consists of four rewriting operations to rewrite to the address one sample earlier. The operation that includes 5 multiplications is
Although it is essential for filter calculation, four RAM rewriting operations increase the number of calculation execution steps and cause a decrease in filter calculation speed. Figure 3 shows the calculation procedure shown in Table 1.
This is a memory map showing RAM data rewriting. In the figure, a indicates the start of filter operation, b indicates the end of the operation, and c indicates the start of the next operation, indicating that RAM is rewritten four times in accordance with the steps of ~ in Table 1. ing. Note that before performing the filter operation, the input x _o is normally brought to address (N+4) on the RAM 3, but the input x _o is directly input to the arithmetic unit 5 without going through the RAM 3 to perform the filter operation. After the calculation is completed, the data may be stored at address (N+3) in the RAM 3. Purpose of the Invention The present invention aims to solve the problems of the prior art, and its purpose is to store input data and calculation result data in a RAM, and use the stored data. In the digital filter calculation circuit that performs filter calculation,
It is an object of the present invention to provide a circuit format capable of reducing the number of rewriting operations of memory contents in RAM and improving the speed of filter calculation. Embodiments of the Invention Table 2 is a calculation procedure for a filter operation showing the principle of the invention.

[Table] FIG. 4 is a memory map showing data rewriting of RAM in the calculation procedure shown in Table 2. In the figure, a indicates the start of calculation, b indicates the end of calculation, and c indicates the start of the next calculation. That is, in the first operation, y _o - ₂ (address N), y _o - ₁ (address N+1), x _o - ₂ (address N+2),
Calculation is performed by combining each data of x _o - ₁ (address N+3) and x _o (Figure 4 a), and when the calculation is completed, the filter output, that is, y _o is transferred to the position of data x _o - ₂ (address N+2). At the same time, input data x _o is stored at the first address of data x _o - ₁ (N+
4) (Figure 4b). When the next sample x _o+1 is input and the second filter operation is performed, y _o - ₁ (address N+1), y _o
The calculation is performed by combining the data of (address N+2), x _o - ₁ (address N+3), x _o (address N+4), and x _{o +1} (FIG. 4c). That is, the filter operation is performed using a combination of data whose address is increased by one address with respect to the combination of data used in the previous operation. In the second calculation, the filter output y _o+1 is also used as data at the end of the calculation.
The input data _{x o} - ₁ (address N+3) is stored, and the input data x _{o +1} is stored at the address above the data x _o (address N+5) in preparation for the next operation. Comparing the calculation procedure of the present invention shown in Table 2 with the conventional calculation procedure shown in Table 1, the number of storage operations in memory is reduced to 2 in the present invention compared to 4 in the conventional method. , so the filter operation speed is obviously improved. FIG. 5 shows an embodiment of the digital filter of the present invention constructed based on the above-described principle. In the figure, reference numeral 11 denotes an address designation unit, which designates an address in a RAM (not shown) using, for example, binary numbers a ₀ to a ₆ by a program or a counter. Reference numeral 12 is a pointer, which is a register equipped with a counter or an adder for counting binary numbers p ₀ to _{p 2} , and is incremented at the end of each filter operation, and returns to 0 when it is fully counted. It is composed of 13 is an AND gate that opens when an address designation signal is applied to pointer 1.
Outputs a signal with a count value of 2. 14 _-1 is a half adder HA, and 14 _-2 and 14 _-3 are full adders FA, which add the lower bits a ₀ to _{a 2} of the address specifying section 11 and the outputs p ₀ to p ₂ of the pointer 12. The outputs of adders _14-1 to _14-3 and upper bits _a3 to _a6 of address specification section 11 are used as execution addresses.
Output to RAM. At this time, the carry of the top adder _14-3 is ignored. Therefore, when the address shift specification is performed, among the addresses a ₀ to a ₆ in the address specification section 11, the lower
The output of the pointer 12 is added to _a0 to _a2 , and only the lower three bits are sequentially incremented by 1, and the addressing returns to the beginning again. Note that RAM is normally used for purposes other than filter operations, and the AND gate 13 is provided to control whether or not to perform address shifting in such cases and in filter operations. . FIG. 6 explains RAM addressing in the digital filter shown in FIG.
In the figure, A indicates the specified address range, and it is shown that the upper bits _a3 to _a6 are fixed, but the lower three bits change in the range of 000 to 111. FIG. 7 explains the contents of the RAM in the digital filter shown in FIG. 5 when addressing the RAM and performing filter operations. In the same figure, 1 to 8 are the first
The data of the RAM in the 8th to 8th calculations are shown, and only the range A in FIG. 6 is shown. During the first calculation, the value P of the pointer is set to 0. At this time, if addresses 0 to 4 are specified as addresses, the addresses to be executed are y _o - ₂ (address 0), y _o - ₁ (address 1), x _o - ₂ (address 2), x _o - ₁ (3
address), x _o (address 4), and a filter operation is performed by this combination. At the end of the calculation, data x _o is stored at address 4, and data y _o is stored at address 2. Also, in line with this, the pointer value P is 1
Add. During the second calculation, if you specify the same address as the first calculation, it will be executed.
Since P is added to the pointer value for RAM addresses, y _o - ₁ (address 1), y _o (address 2), x _o - ₁ (address 3), x _o (address 4), x _{o + 1} ( 5), and a filter operation is performed by this combination. At the end of the calculation, data x _o+1 is stored in address 5, and data y _o+1
is stored at address 3, and 1 is added to the pointer value P. After that, perform the third to eighth operations in the same way, and add 1 to the pointer value P for each operation, so that all execution addresses for the next operation add 1 to the previous address. value, so the data used in the filter operation will be a value shifted by 1 bit, and therefore the data will be
Filter operations can be performed correctly without shifting on RAM. Also, as is clear from Figure 7, the addresses are shifted sequentially,
When the limit of the RAM usage range is reached, the process returns to the beginning and cycles from the smallest address again. This is the fifth
This is because in the circuit configuration shown in the figure, the pointer 12 repeats counting a certain number of times to prevent it from affecting upper addresses, and this makes the RAM area unnecessarily large. I try not to. In the digital filter shown in FIG.
When calculating one stage of the next section filter, 8
The execution address returns to its original state after each operation. When the number of filter stages increases, it is necessary to widen the range in which the address is shifted. To do this, the number of pointer bits is further increased and an adder circuit that adds the output of the address specification section and the output of the pointer is required. The number of digits also needs to increase. Furthermore, when performing calculations on a plurality of filters with different numbers of stages, it is effective to make the range in which addresses are shifted variable. FIG. 8 shows another embodiment of the memory access circuit of the present invention,
This shows a configuration in which the shift area is made variable. In the same figure, the same parts as in FIG. 5 are indicated by the same numbers, 12A is a pointer, 13
A is AND gate, 14 _-4 is full adder, 15,
16 is an AND gate. In FIG. 8, pointer 12A points to binary number p ₀ ~
It consists of a register with a counter or an adder for calculating p ₃ , and the AND gate 13A is connected to the pointer 1
2A is provided corresponding to each bit.
In the AND gate 15, the shift area designation signal is “0”
It closes when , and prevents output of the most significant bit _p3 of pointer 12A. Further, when the output of the AND gate 15 is "0", the AND gate 16 closes and prevents the carry of the full adder _14-3 from being input to the full adder _14-4 . Therefore, when the shift area designation signal is "0", only the lower 3 bits of the address for the RAM are shifted according to the lower 3 bits _p0 to _p2 of the pointer 12A, and the same operation as the circuit shown in FIG. 5 is performed. Let's do it. On the other hand, when the shift area designation signal is “1”,
AND gate 15 is opened and the most significant bit _p3 of pointer 12A is added to full adder _14-4 and AND gate 16, so that the address to RAM is such that the least significant four bits are _p0 of pointer 12A.
Shift according to ~p ₃ . Figure 9 shows the digital filter in Figure 8.
Indicates the address shift area in RAM, A indicates the address shift area when the shift area designation signal is "0", and B indicates the address shift area when the shift area designation signal is "1", and indicates the shift area designation. It is shown that the address shift area is doubled by changing the signal from "0" to "1". FIG. 10 shows the configuration of a filter calculation circuit using the memory access circuit of the present invention. In this figure, the same parts as in FIG. 2 are designated by the same numbers, and 4A is a memory access circuit.
In this way, in the conventional filter operation circuit, the memory access circuit can be used in place of the conventional addressing circuit, thereby improving the filter operation speed. Effects of the Invention As explained above, according to the digital filter of the present invention, in a digital filter circuit that stores input data and operation result data in RAM and performs a filter operation using the stored data, each filter operation is The number of data transfer operations on the RM can be reduced, and the filter operation speed can be improved.

[Brief explanation of drawings]

Figure 1 is a diagram showing the configuration of a secondary cyclic digital filter, Figure 2 is a block diagram showing the configuration of an arithmetic circuit that performs filter calculations using conventional RAM, and Figure 3 is a diagram showing the configuration of a conventional filter calculation procedure.
FIG. 4 is a memory map showing an example of data rewriting of RAM in the filter calculation procedure according to the present invention. FIG. 5 is a block diagram showing an example of the digital filter of the present invention. , FIG. 6 is a diagram explaining the RAM address specification in the digital filter of FIG. FIG. 8 is a block diagram showing the configuration of another embodiment of the digital filter of the present invention, and FIG.
FIG. 10 is a diagram showing the address shift area in the RAM in the case of the digital filter shown in the figure, and FIG. 10 is a diagram showing the configuration of the filter operation circuit in the digital filter of the present invention. DESCRIPTION OF SYMBOLS 1... Read-only memory ROM for coefficients, 2... Address specification circuit for coefficients, 3... Read/write memory RAM, 4... Address specification circuit, 4A... Memory access circuit, 5... Arithmetic unit, 11... Address specification section, 12, 12A ...Pointer, 13, 13A...
AND gate, 14 _-1 ...half adder HA, 14
_-2 ,14 _-3 ,14 _-4 ...Full adder FA, 15,1
6...AND gate.

Claims (1)

[Claims] 1. A RAM that writes and reads input data and operation result data in accordance with address specification, and reads out filter coefficients in accordance with address specification.
ROM and data read from the RAM
A digital filter is equipped with an arithmetic unit that performs an arithmetic operation on data read from a ROM and writes the result to the RAM, and the digital filter includes a pointer that is incremented every sampling and repeatedly counts a fixed number, and a pointer that repeatedly counts a certain number by incrementing it every sampling, and a pointer that repeatedly counts a fixed number by incrementing it every sampling, and a pointer that repeatedly counts a fixed number by incrementing it every sampling, and an addition means for adding to an address determined by the configuration, and the output of the addition means is used as an address to add to the RAM.
A digital filter characterized in that data for filter calculation is read by accessing. 2. Claim 1, characterized in that the counting range of the pointer can be changed by an external signal.
The digital filter described in section.