JPH0114733B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a relative delay adjustment circuit for NRZ signals between multiple digital transmission lines in a digital transmission system.

The conventional NRZ signal delay adjustment circuit expands the delay adjustment range by connecting variable phase shifters in multiple stages to clock pulses synchronized with the NRZ signal and controlling the control elements thereof through interlocking operations. As a result, there are drawbacks such as the control element itself being expensive and the circuit configuration becoming extremely complex.

Figure 1 shows a conventional NRZ with these drawbacks.
FIG. 2 is a block diagram of a signal delay adjustment circuit. In the figure, the input NRZ signal 1 is input to the first pulse shaping circuit 1.
01 and is converted into an NRZ signal 2 having a reference phase under the control of an input clock pulse 4.
On the other hand, an input clock pulse 4 is converted into a clock pulse 5 having a variable phase shift of (n×φ) [rad] by a mechanical or electrical control 6 that interlocks and controls n variable phase shifters 103. In addition, in this case 1
The phase shift amount of the variable phase shifter 103 is φ [rad]. For input clock pulse 4 (n×φ)
The NRZ signal 2 is transmitted to the second pulse shaping circuit 10 by controlling the clock pulse 5 having a phase shift amount of [rad].
2, the NRZ signal 2 is converted into an NRZ signal 3 having a phase shift amount of (n×φ) [rad].

FIG. 3 is a time chart showing an example of the operation of the circuit shown in FIG.

In the figure, each waveform represents a signal with the same sign that is input to or output from each circuit section in FIG. 1.

The signals 5-1 and 5-2 are signals passed through a plurality of variable phase shifters 103, and when 5-1 does not provide a phase difference, the signal 5-2 passes through three variable phase shifters 103.
This is the case where a phase difference of φ is given to the clock 4, respectively.

Therefore, when pulse shaping is performed using the 5-1 signal, the output NRZ signal 3 has a phase difference of 0 from the input NRZ signal.
-1 is obtained. Further, when pulse shaping is performed using the signal 5-2, an output NRZ signal 3-2 having a phase difference of 3×φ from the input NRZ signal is obtained.

FIG. 4 shows a specific configuration example of the variable phase shifter 103, which is generally well known.

This variable phase shifter 103 has, for example, a maximum of 0-
180 degree phase shift is possible. However, due to the incompleteness of the circuit and the inability to vary the capacitance A to a minimum/maximum value, it is not possible to obtain a variable phase shift amount of 0 to 180 degrees.
Therefore, in order to obtain 0-360 degrees, three pieces are required, assuming that one piece can vary from 0-150 degrees. In such a case, it is required to vary these three capacitances simultaneously. Therefore, expensive elements or expensive circuits are required, and the stability is also degraded by three times that of a single phase shifter.

The purpose of the present invention is to solve the above-mentioned drawbacks, and to provide an NRZ that has more stable operation and lower manufacturing cost than the conventional one.
An object of the present invention is to provide a signal delay adjustment circuit.

NRZ according to the present invention to achieve the above object
The signal delay adjustment circuit includes a frequency dividing circuit that divides the input clock pulse by n, a first pulse shaping circuit that shapes the waveform of the input NRZ signal using the input clock pulse, and a first pulse shaping circuit that shapes the waveform of the input NRZ signal by the frequency dividing circuit output signal. a serial-to-parallel conversion circuit (hereinafter abbreviated as an S-P conversion circuit) that branches into columns; a variable phase shifter that changes the phase of the output signal of the frequency dividing circuit; and a variable phase shifter that changes the phase of the output signal of the frequency dividing circuit; It is composed of a parallel-to-serial conversion circuit (hereinafter abbreviated as P-S conversion circuit) that inversely converts the conversion circuit output signal into one column, and an n-tay multiplication circuit that multiplies the output signal of the variable phase shifter by n times.

According to the above configuration, the object of the present invention is completely achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the NRZ signal delay adjustment circuit according to the present invention. Input NRZ
Signal 1 is applied to a first pulse shaping circuit 101 and converted into an NRZ signal 2 having a reference phase under the control of input clock pulse 4. On the other hand, the input clock pulse 4 is frequency-divided by n in the n (n≧2) frequency divider circuit 106, and the frequency of the input clock pulse 4 is divided by n.
The NRZ signal 2 is converted to the S-P conversion circuit 10 by the control of
4, it is converted into n columns of NRZ signals 8. The clock pulse 7 whose frequency has been divided by n is converted by one variable phase shifter 103 into a clock pulse 9 having a variable phase shift amount of φ [rad]. Variable phase shift amount φ at this time
[rad] is the variable phase shift amount for clock pulse 7, and the variable phase shift amount for clock pulse 4 is (n×φ) [rad]. clock pulse 4
The n-column NRZ signal 8 is controlled by a clock pulse 9 having a variable phase shift of (n×φ) [rad].
The P-S conversion circuit 105 converts the NRZ signal 3 to the NRZ signal 2 with a variable phase shift amount of (n×φ) [rad].
Convert to

On the other hand, clock pulse 5 synchronized with NRZ signal 3
obtains the clock pulse 9 through an n-time multiplier circuit 107. It goes without saying that the clock pulse 5 has a variable phase shift amount of (n×φ) [rad] with respect to the clock pulse 4. FIG. 5 is a timing chart for explaining the operation of FIG.
This is an example of the case where =3. If the maximum variable range of one phase shifter is 0 to 150 degrees as explained in the conventional example, it will be 0 to 3 × 150 (450) degrees, which can be larger than 2π and the phase within one period can be changed. Can be adjusted.

In the figure, each waveform represents a signal with the same sign that is input to or output from each circuit section in FIG. 2.

Signals 9-1 and 9-2 are signals obtained by passing the frequency divided output 7 through one variable phase shifter 103, and
1 is a case in which no phase difference is provided, and 9-2 is a case in which a phase difference of φ is provided by one variable phase shifter 103. Therefore, when the signal 9-1 is subjected to PS conversion, an output NRZ signal 3-1 having a phase difference of 0 from the input NRZ signal is obtained. Also, P-S at the 9-2 signal.
When converted, an output NRZ signal 3-2 with a phase shift difference of 3×φ from the input NRZ signal is obtained.

As explained above, the NRZ signal delay adjustment circuit according to the present invention differs from the configuration of interlocking operation control using a conventional multi-stage variable phase shifter, and has a variable phase shifter having one control element in addition to the first pulse shaping circuit. It is economical because it uses a circuit and a logic element as its constituent elements, and the circuit structure is simple, so the operation is more stable than in the past.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional NRZ signal delay adjustment circuit, and FIG. 2 is a circuit block diagram showing an embodiment of the NRZ signal delay adjustment circuit according to the present invention. Figure 3 is a timing chart for explaining the operation of the circuit in Figure 1, Figure 4 is a circuit diagram showing a specific example of a phase shifter, and Figure 5 is a timing chart for explaining the operation of the circuit in Figure 2. This is a timing chart. 101...first pulse shaping circuit, 102...
Second pulse shaping circuit, 103...variable phase shifter,
104...S-P conversion circuit, 105...P-S conversion circuit, 106...n frequency divider circuit, 107...n-tay multiplier circuit.

Claims (1)

[Claims] 1. A frequency dividing circuit that divides the input clock pulse by n, a first pulse shaping circuit that shapes the waveform of the input NRZ signal using the input clock pulse, and the output signal of the pulse shaping circuit is branched into n columns using the frequency dividing circuit output signal. a series-to-parallel conversion circuit; a variable phase shifter that changes the phase of the frequency dividing circuit output signal;
It is composed of a parallel-to-serial conversion circuit that inversely converts the output signal of the series-to-parallel conversion circuit into a single string by the output signal of the variable phase shifter, and an n-tay multiplication circuit that multiplies the output signal of the variable phase shifter by n times. NRZ signal delay adjustment circuit.