JPH0141033B2 - - Google Patents
Info
- Publication number
- JPH0141033B2 JPH0141033B2 JP57012700A JP1270082A JPH0141033B2 JP H0141033 B2 JPH0141033 B2 JP H0141033B2 JP 57012700 A JP57012700 A JP 57012700A JP 1270082 A JP1270082 A JP 1270082A JP H0141033 B2 JPH0141033 B2 JP H0141033B2
- Authority
- JP
- Japan
- Prior art keywords
- brazing
- lead pins
- lead
- lead pin
- plate material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、半導体用リードピンの製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing lead pins for semiconductors.
近時、半導体IC或いはLSIは、高集積化の要請
から従来使用されてきたデユアル・イン・パツケ
ージ型のものからプラグ・イン・パツケージ型の
ものに変りつつある。 Recently, semiconductor ICs or LSIs are changing from the conventional dual-in-package type to the plug-in package type due to the demand for higher integration.
そのプラグ・イン・パツケージ型の半導体IC
に用いるリードピンのセラミツク基板へのろう付
は、従来第１図ａに示す如くセラミツク１の表面
にメタライズ２を行い、次にそのメタライズした
セラミツクにニツケルめつき３を施し、次いで第
１図ｂに示す如くカーボン治具１０をセツトし、
次にセラミツク１のニツケルめつき３の上にろう
材４をセツトし、次いでろう材４の上にリードピ
ン５をセツトし、然る後電気炉中でリードピン５
をろう付する方法が一般的であつた。 Its plug-in package type semiconductor IC
Conventionally, lead pins used for soldering to a ceramic substrate are metallized 2 on the surface of the ceramic 1 as shown in Fig. 1a, then nickel plating 3 is applied to the metallized ceramic, and then as shown in Fig. 1b Set the carbon jig 10 as shown,
Next, a brazing filler metal 4 is set on the nickel plating 3 of the ceramic 1, and then a lead pin 5 is set on the brazing filler metal 4, and then the lead pin 5 is set in an electric furnace.
The most common method was to braze.
ところで、かかるろう付方法では、ろう材を所
定の位置に正確に位置させることが極めて困難で
あり、またろう付強度にばらつきがあつて低く不
安定であり、さらにはろう付されないものが生じ
るものである。従つてろう付不良の半導体ICが
多量に生じ、しかも一度ろう付不良を起した半導
体ICは処分するか、或いは再ろう付を行わなけ
ればならない。 However, with such brazing methods, it is extremely difficult to accurately position the brazing material in a predetermined position, and the brazing strength varies and is low and unstable, and furthermore, some brazing materials may not be brazed. It is. Therefore, a large number of semiconductor ICs are produced with defective brazing, and semiconductor ICs that have once caused defective brazing must be disposed of or re-brazed.
然し乍ら、前者の手段では歩留りが甚だ悪く、
後者の手段では手間が掛り、この点の改善が要望
されていた。 However, with the former method, the yield is extremely low;
The latter method is time-consuming, and improvements in this respect have been desired.
この為、第一工程で第２図ａ，ｂに示す如くろ
う材４が予め融着されたリードピン５′を作り、
第二工程で第１図ａに示されるようにメタライズ
２が行われ、さらにニツケルめつき３が施された
セラミツク１のニツケルめつき３上に治具を用い
て前記リードピン５′をセツトし、電気炉中でリ
ードピン５′をろう付する方法が考えられている。 For this purpose, in the first step, lead pins 5' with brazing filler metal 4 fused in advance are made as shown in FIGS. 2a and 2b.
In the second step, as shown in FIG. 1a, the lead pin 5' is set on the nickel plating 3 of the ceramic 1 which has been metallized 2 and further provided with the nickel plating 3 using a jig, A method has been considered in which the lead pins 5' are brazed in an electric furnace.
ところで、ろう材４が予め融着されたリードピ
ン５′を作るには、カツトしたリードピン５にカ
ツトしたろう材４を電気炉中でろう付する所調バ
ツクろう方式を用いるのであるが、この方式では
カツトしたろう材４が小さいので、これをリード
ピン５をセツトせる治具内に入れると、リードピ
ン５一本に対し複数個のろう材４が入つたり、全
く入らなかつたりすることがあつた。またリード
ピン５一本に対し一個ずつろう材４が入つてもろ
う材４のセツト位置の調整が難しく第３図ａ，ｂ
に示す如くろう材４のリードピン５に対するろう
付位置の不良や第３図ｃ，ｄに示す如くろう材４
のリードピン５への回り込み、或いは第３図ｅ，
ｆに示す如くろう材４がリードピン５に融着しな
いなどの現象が生じ、リードピン５′の品質が甚
だばらつき、不良品も多かつた。 By the way, in order to make the lead pin 5' to which the brazing filler metal 4 has been fused in advance, a partial back brazing method is used in which the cut brazing filler metal 4 is brazed to the cut lead pin 5 in an electric furnace. Now, since the cut brazing filler metal 4 is small, when it is placed in a jig for setting the lead pin 5, sometimes multiple pieces of brazing filler metal 4 fit into one lead pin 5, or sometimes none at all. . In addition, even if one piece of brazing material 4 is inserted into each lead pin 5, it is difficult to adjust the set position of the soldering material 4 as shown in Figures 3a and b.
As shown in FIG.
wrap around the lead pin 5, or as shown in Fig. 3 e,
As shown in f, phenomena such as the brazing filler metal 4 not being fused to the lead pin 5 occurred, and the quality of the lead pins 5' varied greatly and there were many defective products.
本発明は、かかる問題を解決すべくなされたも
のであり、ろう材が予めリードピンのセラミツク
基板とのろう付部に接合されて一体化されて成る
半導体用リードピンを、効率良く且つ確実に精度
良く作ることのできる方法を提供せんとするもの
である。 The present invention was made in order to solve this problem, and efficiently, reliably, and accurately produce semiconductor lead pins in which a brazing material is pre-bonded to the brazed portion of the lead pin and the ceramic substrate. The purpose is to provide a method that can be used to create such materials.
本発明の半導体用リードピンの製造方法は、第
４図ａ，ｂ，ｃに夫々示されるように、リードピ
ンとなるべき材料を所要の断面形状の板材６，
６′６″に成形加工し、次にこの板材６，６，′
６″の一側端部の所要位置に第５図ａ，ｂ，ｃに
夫々示されるように所要の断面形状の線条ろう材
７，７′，７″をシーム溶接、レーザー溶接、熱圧
接等により接合して一体化して複合板材８，８′，
８″を作り、次いでこの複合板材８，８′，８″を
順次一定寸法に切断して第６図ａ，ｂ，ｃに夫々
示されるような複合線材の半導体用リードピン
９，９′，９″を作ることを特徴とするものであ
る。 As shown in FIGS. 4a, b, and c, the method for manufacturing lead pins for semiconductors of the present invention involves preparing a material to be a lead pin into a plate material 6 with a desired cross-sectional shape,
6'6'', then this plate material 6,6,'
At the desired position on one side end of 6", wire filler metals 7, 7', and 7" with the desired cross-sectional shapes as shown in Fig. 5 a, b, and c are seam welded, laser welded, or thermocompression welded. etc. to form a composite board 8, 8',
8'', and then sequentially cut the composite plate materials 8, 8', 8'' to a certain size to obtain composite wire semiconductor lead pins 9, 9', 9 as shown in FIGS. 6a, b, and c, respectively. It is characterized by making ``.
尚、前記半導体用リードピン９，９′，９″は横
断面角形であるが、場合によつてはこれらリード
ピン９，９′，９″を転造機などを用いて第７図
ａ，ｂ，ｃに夫々示されるように所要の部分を円
形に成形しても良いものである。 The semiconductor lead pins 9, 9', 9'' have a rectangular cross section, but in some cases these lead pins 9, 9', 9'' may be formed using a rolling machine or the like as shown in FIGS. 7a, b, c. Required portions may be formed into circular shapes as shown in FIG.
本発明による半導体用リードピンの製造方法
は、前述の如くリードピンとなるべき材料を板材
に成形加工し、この板材の板端部に線条ろう材を
接合して一体化し、この複合板材を一定寸法に切
断するのであるから、得られるリードピンのろう
材はセラミツク基板とのろう付部の正確な位置に
確実に接合され且つその形状は所要の一定した形
状となり、極めて精度の良いリードピンとなる。
従つてかかるリードピンはセラミツク基板とのろ
う付が確実、容易に行われ、そのろう付強度は高
く安定するものである。またろう付されないもの
が全く生じないので、極めて歩留りが良く、品質
良好な半導体ICを得ることができる。 As described above, the method for manufacturing lead pins for semiconductors according to the present invention involves forming a material to be a lead pin into a plate material, joining a filament brazing material to the end of the plate material to integrate the composite plate material, and forming the composite plate material to a certain size. Since the soldering material of the resulting lead pin is reliably joined to the ceramic substrate at the correct position of the brazed portion, and the shape becomes the required constant shape, the resulting lead pin becomes an extremely accurate lead pin.
Therefore, such lead pins can be reliably and easily brazed to the ceramic substrate, and the brazing strength is high and stable. Moreover, since there is no unbrazed material, it is possible to obtain semiconductor ICs with extremely high yield and good quality.
また本発明による半導体用リードピンの製造方
法は、前記の如く板材から製造するので、極めて
作業性ひいては生産性に優れているので安価に量
産できるものである。 Furthermore, since the method for manufacturing lead pins for semiconductors according to the present invention is manufactured from a plate material as described above, the workability and productivity are extremely excellent, so that the lead pins can be mass-produced at low cost.
次に本発明による半導体用リードピンの製造方
法の具体的な実施例と従来例について説明する。 Next, specific examples and conventional examples of the method for manufacturing semiconductor lead pins according to the present invention will be described.
実施例 １
通常42合金と呼ばれるFe−Ni42重量％合金で
厚さ0.4mm、幅４mmの第４図ａに示されるような
板材６を作り、次にこの板材６の一側端面に第８
図ａに示す如く直径0.4mmのAg−Cu28重量％合金
より成る線条ろう材７ａをシーム溶接にて溶接し
一体化して複合板材８ａを作り、次いでこの複合
板材８ａを0.4mmずつ順次切断して第８図ｂに示
す如き複合線材の半導体用リードピン９ａを得
た。Example 1 A plate material 6 as shown in FIG. 4a having a thickness of 0.4 mm and a width of 4 mm is made of an Fe-Ni 42 wt.
As shown in Figure a, wire brazing filler metal 7a made of Ag-Cu28% alloy with a diameter of 0.4 mm is seam welded and integrated to form a composite plate 8a, and then this composite plate 8a is sequentially cut into 0.4 mm increments. Thus, a semiconductor lead pin 9a made of a composite wire material as shown in FIG. 8b was obtained.
実施例 ２
コバールと呼ばれるFe−Ni29重量％−Co17重
量％合金で厚さ0.88mm、幅５mm、一側部に厚さ
0.18mm、幅0.15mmの直交するフランジを有する第
４図ｃに示されるような板材６″を作り、次にこ
の板材６″のフランジの上面基部に第５図ｃに示
す如く直径0.05mmのAgより成る線条ろう材７″を
YAGレーザーを用いてシーム溶接し一体化して
複合板材８″を作り、次いでこの複合板材８″を
0.88mmずつ順次切断して第６図ｃに示す如き複合
線材の半導体用リードピン９″を作り、さらにリ
ードピン９″の下部を直径0.5mmの円柱状に成形し
た。Example 2 Fe-Ni29wt%-Co17wt% alloy called Kovar, thickness 0.88mm, width 5mm, thickness on one side.
A plate 6'' as shown in Fig. 4c is made with perpendicular flanges of 0.18 mm and width 0.15 mm, and then a 0.05 mm diameter plate is attached to the upper base of the flange of this plate 6'' as shown in Fig. 5 c. A filament brazing filler metal 7″ made of Ag
Seam welding is performed using a YAG laser to create a composite plate 8″, and then this composite plate 8″ is
Sequential cutting into pieces of 0.88 mm was used to produce composite wire semiconductor lead pins 9'' as shown in FIG. 6c, and the lower part of the lead pins 9'' was shaped into a cylinder with a diameter of 0.5 mm.
従来例
Fe−Ni42合金を直径0.4mmに線引し、これを長
さ5.0mmに切断の上ヘツダー加工して頭径0.6mm、
頭高0.5mm、脚径0.4mm、脚長４mmのリードピンを
成形した。次にAg−Cu28重量％合金を直径0.4mm
に線引し、これを0.4mmの厚さで切断して粒状ろ
う材を作つた。次いで治具内に粒状ろう材をセツ
トし、その上に前記リードピンを載せ、800℃、
N2＋H25％の雰囲気のコンベア炉中でろう付を
行い、ろう材の接合されたリードピンを作つた。
このリードピンを検査した処第３図ｂ，ｄに示す
ような不良品が発生し不良率は30〜40％であつ
た。Conventional example Fe-Ni42 alloy is drawn to a diameter of 0.4 mm, cut to a length of 5.0 mm, and then processed into a header with a head diameter of 0.6 mm.
A lead pin with a head height of 0.5 mm, a leg diameter of 0.4 mm, and a leg length of 4 mm was molded. Next, Ag-Cu28wt% alloy with a diameter of 0.4mm
This was then cut to a thickness of 0.4 mm to make granular brazing filler metal. Next, set the granular brazing filler metal in the jig, place the lead pin on top of it, and heat it at 800°C.
Brazing was performed in a conveyor furnace in an atmosphere of 5% N 2 +H 2 to produce lead pins to which the brazing metal was bonded.
When this lead pin was inspected, defective products as shown in FIGS. 3b and 3d occurred, and the defective rate was 30 to 40%.
然して実施例１、２のリードピン及び従来例の
選別した良品のリードピンを夫々セラミツク基板
上にろう付けした処、実施例１、２のリードピン
に於いてはろう付不良は皆無であつたのに対し、
従来例のリードピンに於いてはろう付不良率が10
〜20％もあつた。これは選別しきれないリードピ
ンの不良によるものと考えられる。 However, when the lead pins of Examples 1 and 2 and the selected good lead pins of the conventional example were brazed onto ceramic substrates, there were no brazing defects in the lead pins of Examples 1 and 2, whereas there were no brazing defects in the lead pins of Examples 1 and 2. ,
The brazing defect rate for conventional lead pins was 10
~20% warmer. This is thought to be due to defective lead pins that could not be sorted out.
以上詳記した通り本発明による半導体用リード
ピンの製造方法によれば、ろう材が予めリードピ
ンのセラミツク基板とのろう付部の正確な位置に
確実に接合され且つその形状が所要の一定した形
状で極めて精度の良いリードピンを能率良く製造
できるという優れた効果がある。 As detailed above, according to the method for manufacturing semiconductor lead pins according to the present invention, the brazing material is reliably joined in advance to the correct position of the brazed portion of the lead pin with the ceramic substrate, and the shape is kept in the required constant shape. This has the excellent effect of efficiently manufacturing lead pins with extremely high precision.
また本発明の製造方法により得られたリードピ
ンをセラミツク基板にろう付けすれば、そのろう
付が確実、容易に行われ、ろう付強度は高く安定
し、歩留りの良い品質良好な半導体ICが得られ
る。 Furthermore, if the lead pins obtained by the manufacturing method of the present invention are brazed to a ceramic substrate, the brazing can be performed reliably and easily, the brazing strength is high and stable, and a semiconductor IC of good quality with a high yield can be obtained. .
第１図ａ，ｂはセラミツク基板にリードピンを
ろう付する従来の方法の工程を示す図、第２図
ａ，ｂはろう材が了め融着された従来のリードピ
ンの例を示す図、第３図ａ乃至ｆは第２図ａ，ｂ
に示すリードピンの製造において生じる不良品を
示す図、第４図乃至第６図の各ａ，ｂ，ｃは夫々
本発明による半導体用リードピンの製造方法の工
程を示す図、第７図ａ，ｂ，ｃは第６図ａ，ｂ，
ｃのリードピンをさらに円形に成形した状態を示
す図、第８図ａ，ｂは第４図ａに示す板材からリ
ードピンを製造する本発明の製造方法の具体的な
実施例を示す図である。
６，６′，６″……板材、７，７′，７″，７ａ…
…線条ろう材、８，８′，８″，８ａ……複合板
材、９，９′，９″，９ａ……リードピン。
Figures 1a and b are diagrams showing the steps of a conventional method for brazing lead pins to a ceramic substrate; Figures 2a and b are diagrams showing an example of a conventional lead pin that has been fused after soldering; Figure 3 a to f are Figure 2 a, b
Figures a, b, and c in Figures 4 to 6 show the steps of the method for manufacturing lead pins for semiconductors according to the present invention, and Figures 7 a, b , c are Fig. 6 a, b,
FIGS. 8a and 8b are views showing a specific embodiment of the manufacturing method of the present invention for manufacturing lead pins from the plate material shown in FIG. 4a. FIGS. 6, 6', 6''...Plate material, 7, 7', 7'', 7a...
... Line brazing material, 8, 8', 8'', 8a... Composite plate material, 9, 9', 9'', 9a... Lead pin.
Claims (1)
断面形状の板材に成形加工し、次にこの板材の一
側部に所要の断面形状の線条ろう材を接合して一
体化し、次いでこの複合板材を順次一定寸法に切
断して複合線材の半導体用リードピンを作ること
を特徴とする半導体用リードピンの製造方法。1. The material to be used as lead pins for semiconductors is formed into a plate material with the desired cross-sectional shape, and then a wire brazing material with the desired cross-sectional shape is joined to one side of this plate material to integrate it, and then this composite plate material is A method for manufacturing a semiconductor lead pin, which comprises sequentially cutting a composite wire into a predetermined size to make a semiconductor lead pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57012700A JPS58130548A (en) | 1982-01-29 | 1982-01-29 | Manufacture of lead pin for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57012700A JPS58130548A (en) | 1982-01-29 | 1982-01-29 | Manufacture of lead pin for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58130548A JPS58130548A (en) | 1983-08-04 |
| JPH0141033B2 true JPH0141033B2 (en) | 1989-09-01 |
Family
ID=11812662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57012700A Granted JPS58130548A (en) | 1982-01-29 | 1982-01-29 | Manufacture of lead pin for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58130548A (en) |
-
1982
- 1982-01-29 JP JP57012700A patent/JPS58130548A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58130548A (en) | 1983-08-04 |
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