JPH0141276B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for surface treatment of a conductive pattern in an intermediate layer constituting a multilayer printed circuit board.

(2) Background of the technology When forming a desired conductor pattern on multiple printed circuit boards as intermediate layers and laminating them with prepreg interposed to form a multilayer printed circuit board, the adhesive strength between each printed circuit board and the prepreg is In order to ensure this, a method is used in which the surface of the conductor pattern on the printed circuit board is roughened to increase the bonding area.

(3) Prior Art and Problems Figure 1 shows a cross-sectional view of a multilayer printed circuit board, and Figure 2 shows a cross-sectional view of a through hole.

In the figure, 1 is a multilayer printed circuit board, 2 is an intermediate layer printed circuit board, 3 is a conductor pattern, 4 is a prepreg layer, 5 is a surface layer printed circuit board, 6 is a through hole, 7 is a land, and 8 is a pattern. show.

As shown in FIG. 1, the multilayer printed circuit board 1 is composed of a double-sided surface layer printed circuit board 5, a plurality of intermediate layer printed circuit boards 2, and a prepreg layer 4 for bonding each printed circuit board. The printed circuit boards 2 and 5 are bonded via the prepreg layer 4, and the bonding strength between the printed circuit boards 2 and 5 varies depending on the bonding state between the surfaces of the respective printed circuit boards 2 and 5 and the prepreg layer 4. be done.

Therefore, in order to increase the bonding force between the respective printed circuit boards 2 and 5, the surfaces of the conductive patterns 3 formed on the printed circuit boards 2 and 5 that are in contact with the prepreg layer 4 are roughened to increase the surface area for bonding with the prepreg layer 4. A method based on the anchoring effect of the joint is common.

Therefore, to roughen the surface of the conductor pattern 3, blackening treatment is performed with a solution containing sodium hypochlorite and caustic soda as main ingredients, and the diameter of cupric oxide is 1 to 2 μm.
By forming dense needles with a length of about 2 μm,
In order to increase the effective surface area per unit area of the conductor pattern 3 and to have an anchoring effect with the epoxy resin of the prepreg layer 4, the conductor pattern 3 is laminated and formed, and as shown in FIG. 2, the desired through holes are drilled. The through-holes 6 thus obtained are electrolessly plated.

At this time, the land 7 of the intermediate layer printed circuit board 2 to be connected is exposed on the inner wall of the through hole 6.

A dilute hydrochloric acid solution with a concentration of 10% is used as a pretreatment for electroless plating of the through-hole holes 6, but the surface of the land 7 is removed from the exposed part of the inner wall of the through-hole hole 6 by the dilute hydrochloric acid in step 2. The ferric oxide is easily reduced, and the acicular cupric oxide inward from the inner wall surface is removed, forming a cavity and forming a haloing state. The electrolyte liquid permeates into this cavity and remains. Electroless plating and electrolytic plating are performed to form the multilayer printed circuit board 1. When the board is used as a package for mounting components and configuring electronic equipment, migration occurs due to the potential difference between the lands 7 and the patterns 8, and the insulation resistance between them increases. It may deteriorate to about 1/1,000,000 times its normal state and lose its function as a package.

Conventionally, the minimum distance between land 7 and pattern 8 was
When it is 500 μm or more, there was no practical problem because the insulation resistance value was high and the deterioration time was long, but recently, the pattern density has become dense and the land 7 and the adjacent pattern 8 are When the minimum spacing is about 100 μm, the insulation resistance value is low and the deterioration time is short, so it is no longer possible to maintain the required insulation resistance between the circuits.

(4) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional art, the present invention provides a method for electroless plating in the through-hole in which the land of the conductor pattern on the bonding surface of the printed circuit board is exposed to the through-hole. The object of the present invention is to provide a method for manufacturing a multilayer printed circuit board that forms lands that do not cause haloing through processing.

(5) Structure of the Invention According to the present invention, this purpose is to reduce in advance cupric oxide obtained by blackening the conductor pattern of the printed circuit board to be bonded to become cuprous oxide or copper. This is achieved by providing a method for manufacturing a multilayer printed circuit board, which is characterized in that the method is then laminated and molded.

(6) Examples of the invention Examples of the invention will be described in detail below with reference to the drawings.
FIG. 3 is a schematic diagram of the needle state caused by cupric oxide on the surface of the conductive pattern, and FIG. 4 is a schematic diagram showing the reduction of the cupric oxide in FIG. 3.

In the figure, 9 is copper foil, 10 is cupric oxide, 11
12 and 13 are copper oxide, reduced copper, and imidazole coatings, respectively.

A schematic enlarged sectional view of the surface of the conductor pattern 3 on the laminated surface of the intermediate layer printed circuit board 2 and the surface layer printed circuit board 5 constituting the multilayer printed circuit board 1 is shown in FIG.
As shown in the figure, the surface of the copper foil 9 of the conductor pattern 3 is blackened to form cupric oxide 10, and protrusions with a diameter of 1 to 2 μm and a length of about 2 μm grow densely.

The present invention converts cupric oxide 10 shown in FIG. 3 into cuprous oxide 11 or reduced copper 12, which is not easily reduced with a strong acid such as dilute hydrochloric acid, prior to lamination, and then inserts a through hole in a desired position after lamination. Through hole 6 for plating
When a dilute hydrochloric acid bath is applied to the exposed portion of the land 7 of the conductor pattern 3 on the inner wall obtained by drilling the through hole 6 as a pretreatment for electroless plating of the inner wall of the through hole 6, the land 7 of the conductor pattern 3 is exposed to the through hole 6. On the surface of the land 7, cupric oxide 10, which is easily reduced, is converted into cuprous oxide 11 and reduced copper 12, and the bond between the copper foil 9 and the prepreg layer 4 does not cause haloing. Since no cavities are formed and the electrolyte solution does not permeate, migration does not occur between adjacent patterns 8.

To convert this cupric oxide 10 into cuprous oxide 11 and reduced copper 12, imidazole-based benzotriazole, which has a slow reducing action, is used to oxidize cupric oxide 10 as shown in Figure 4. The cuprous oxide 11 and the reduced copper 12 are used to form a rust-preventive coating of imidazole 13 with a thickness of about 1 μm on the surface of the cuprous oxide 11, and to improve the adhesion to the resin of the prepreg 4.

(7) Effects of the Invention As is clear from the above explanation, according to the method for manufacturing a multilayer printed circuit board of the present invention, there is no migration between the land in contact with the inner wall of the through hole and the adjacent pattern, so that dense Even if the printed circuit board has a very narrow pattern and the spacing between the land and the pattern is extremely narrow, a highly reliable package can be formed because there is no deterioration in insulation resistance.

[Brief explanation of drawings]

Fig. 1 shows a cross-sectional view of a multilayer printed circuit board, Fig. 2 shows a cross-sectional view of a through hole, Fig. 3 shows a schematic diagram of a needle state caused by cupric oxide on the surface of a conductor pattern, and Fig. FIG. 4 is a schematic diagram showing the reduction of cupric oxide in FIG. 3. In the figure, 2 is an intermediate layer printed circuit board, 4 is a prepreg layer, 5 is a surface layer printed circuit board, 6 is a through hole, 7 is a land, 8 is a pattern, 10
indicates a cupric oxide layer, and 13 indicates imidazole.

Claims (1)

[Claims] 1. The surface of the conductor pattern on the joint surface of the surface layer and intermediate layer printed circuit board constituting a multilayer printed circuit board is blackened, and the cupric oxide obtained is reduced with an imidazole solution and then laminated. Features: A method for manufacturing multilayer printed circuit boards.