JPH0143322B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention connects input/output elements such as limit switches and relays provided in each of a plurality of machine units and a sequence controller via multiple transmission lines. The present invention relates to a multiplex transmission device configured to do so.

In particular, the multiplex transmission line has the function of variably converting the input/output addresses of the input/output elements that are controlled by the channel of the multiplex transmission line and the sequence controller, as well as detecting duplicate settings of input/output addresses. Regarding transmission equipment.

[Prior Art] Conventionally, as a system for synchronously controlling a large number of machine units, there has been known a control system that performs time-division control using a sequence controller via a serial transmission path.

This control system consists of a master control unit 3 that controls the channels, as shown in Figure 2.
, a multiplex transmission line 4, a sequence controller 1 that controls each machine unit, a multiplex transmission interface 2 that is an interface between the sequence controller 1 and the multiplex transmission line 4, and a multiplex transmission line 4 connected to each machine unit. Transmitting units 52, 53 and receiving unit 5 arranged in the unit
It consists of 1,54 mag.

The master control unit 3 sequentially outputs a reset pulse P1 and a channel count pulse P6, as shown in FIG. Each transmitting/receiving unit has a specific channel number set by a deep switch 531, 511, etc., and when the value of its channel counter 532, 512 becomes equal to the set channel number, The identified transmitter/receiver unit outputs the data signals P2, P4 to the multiplex transmission line, or outputs the data signals P2, P4 from the multiplex transmission line.
Enter 4.

The reset pulse P1 outputted from the master control unit 3 resets the contents of the channel counters 532, 512 of each transmitting/receiving unit and the channel counter of the multiplex transmission interface 2, and sets the channel number to zero. In addition, the channel count pulse P6 is outputted from the master control unit 3 at a constant cycle, and updates the value of each channel counter by 1.
The used channels of the transmission line are sequentially updated. When the set maximum channel is reached, a reset pulse P1 is outputted, and the transmission line is again time-division multiplexed sequentially starting from the zero channel.

In this way, the master control unit 3
The channels of the transmission line are controlled in a time-division manner, and each transmitter/receiver unit
When the transmission line is set, data can be sent and received to and from the sequence controller 1. In the above manner, the transmitting units 52, 53
can output the states of input elements such as limit switches, operation switches, and relay contacts to the sequence controller 1 using their respective channels, and the sequence controller 1 can output the states of input elements such as limit switches, operation switches, and relay contacts to the receiving units 51 and 54 through their respective channels. can be used to output a signal indicating the operating state of an output element such as a lamp or relay coil.

In the conventional multiplex transmission system, a plurality of machine units are controlled by a sequence controller with the above configuration and operation.

[Problems to be Solved by the Invention] The multiplex transmission system described above is provided with a multiplex transmission interface 2 that is an interface between the sequence controller 1 and the multiplex transmission line 4. This multiplex transmission interface 2 is a device that performs mutual conversion between data controlled independently by a sequence controller in units of input/output addresses and data multiplexed in time division in units of channels.
Therefore, in this multiplex transmission interface 2,
A device is required to perform mutual conversion between the channel and the input/output address of the control unit of the sequence controller, and it is desirable in terms of system design and operation that this correspondence relationship can be easily changed. However, in the conventional device, a depth switch is provided for each channel, and corresponding input/output addresses are set. For this reason, the volume of the device is large;
It was not possible to increase the number of channels per multiplex transmission device. Furthermore, since a code generator corresponding to the operating state of the decoder and depth switch is used to convert the channel to the input/output address, the circuit configuration is complicated. In addition, there is a risk that input/output addresses may be mistakenly set twice for different channels, and in that case, the system will run out of control, and once set, it is not easy to detect this.

The present invention was made in order to improve the above-mentioned drawbacks, and it facilitates channel/input/output address conversion and their settings and changes, prevents duplicate settings of input/output addresses, and improves system reliability. The purpose is to improve performance and ensure smooth operation of the system.

[Means for Solving the Problems] The present invention provides an interface that connects a time-division multiplex transmission line to which a plurality of transmitter/receivers are connected and a sequence controller. a channel counter that inputs count pulses that determine the channel of a line; and a buffer that is arranged between the sequence controller and the multiplex transmission line and that is connected to the address bus of the sequence controller and that inputs and outputs input and output addresses. a data storage device to be accessed by designation, storing said input/output address corresponding to said channel, connecting an address bus to said channel counter, and connecting a data bus to said address bus for accessing said data storage device; a channel/address converting device comprising a storage device configured to convert the channel and input/output address; and a channel/address converting device connected to the channel/address converting device so as to be able to access the device, and configured to convert the input/output address corresponding to the channel. an input/output address setting device that sets an output address to the channel/address conversion device; detecting duplicate settings of the input/output address set by the channel/address setting device;
The present invention is characterized in that it includes a duplicate setting detection device that displays duplicate input/output addresses.

The apparatus of the present invention is characterized in that the conversion device for converting a channel and an input/output address uses a storage device that stores, as data, an input/output address corresponding to the channel at an address specified by the channel. It is said that Therefore, by accessing the memory device using the channel signal as an address signal, the input/output address signal can be taken out on the data line, and channel/input/output address conversion is easily performed. Further, the conversion device is provided with an input/output address setting device for setting an input/output address corresponding to each channel, and the input/output address can be set in the storage device by this device. Furthermore, the above conversion device includes
A duplicate setting detection device is connected that detects and displays duplicate set input/output addresses.
Erroneous and duplicate settings of input/output addresses can be easily prevented.

The value of the channel counter indicates a number that changes sequentially, indicating that the transmission line is currently being used for the channel of that number. Viewed from the sequence controller, each channel is divided into an input channel and an output channel for input elements and output elements. The input channel is from the transmitting unit.
This is a channel for transmitting data to the sequence controller side, and the output channel is a channel for outputting data from the sequence controller to the receiving unit. Therefore, the input channel corresponds to the input address, and the output channel corresponds to the output address.

The data storage device is accessed by the sequence controller by specifying an input/output address, and at the same time, it is also accessed by the channel/address conversion device. Typically, one channel carries data that controls multiple input or output elements, so one channel corresponds to a group of input or output addresses. Therefore, the input/output address corresponding to the channel is represented by a representative value of the input/output address group.

The channel/address translation device is connected so as to be accessible from both the channel counter and the input/output address setting device.

[Operation] First, an input/output address corresponding to each channel is set using the input/output address setting device. In this state, the system is in operation, and channels are sequentially switched in a time-division manner, and data on each channel is transmitted and received. Now, if the channel counter indicates the 0th channel,
A corresponding input/output address signal of the 0th channel is generated on the data bus of the channel/address conversion device. By using this input/output address signal as the address signal of the data storage device (for example, an upper address signal), the input/output address group exclusive to that channel can be accessed, and the received data of that channel can be sequentially stored in the corresponding address. Or, conversely, serial data can be output to that channel by sequentially accessing the input/output address group corresponding to that channel. Further, the duplicate setting detection device operates before the system is operated, and displays input/output addresses that have been erroneously set duplicated by the input/output address setting device. Therefore, it is possible to prevent the multiplex transmission device from running out of control.

[Examples] Hereinafter, the present invention will be described in detail based on specific examples.

FIG. 1 is a block diagram showing the configuration of a multiplex transmission interface used in a multiplex transmission apparatus according to a specific embodiment of the present invention.

FIG. 2 is a block diagram showing the overall configuration of a multiplex transmission system having a multiplex transmission interface 2. As shown in FIG.

The multiplex transmission line 4 (serial transmission line) is connected to the line driver/receiver 200,
Line driver/receiver 200 outputs data signals to multiplex transmission line 4 and receives channel count pulses and data signals from multiplex transmission line 4 . The line driver/receiver 200 includes
A channel counter 21 that inputs channel count pulses and a serial/parallel converter 22 that converts received data and serial data into parallel data are connected. The serial/parallel converter 22 is connected to a data storage device 28 via an addressable gate 201, and the received data is stored at different addresses bit by bit.
The data storage device 28 includes RAM 2 of the storage unit.
81, RAM282, RAM283, RAM284
They are 1-bit RAM accessed at the same address. Each RAM is further
Multiplexer 285, 286, 287, 288
It has an address bus 11 of the sequence controller 1, a channel/address conversion device 2
It is accessed from both address buses 291 on the 9 side. Each time the RAM selection circuit 206 receives a reset pulse input from the multiplex transmission line,
RAM281, 282, 283, and 284 are selected in sequence. That is, for all input and output addresses,
There are four RAMs for storing data.
At every channel multiplexing period, the RAM that is input from the multiplex transmission line and stored is switched. The double-check circuit 207 has a function of taking the majority value of the contents of the three RAMs that are not accessed from the multiplex transmission line side, and the sequence controller 1
can read the input element data stored in the data storage device 28 as the majority decision value. The channel/address conversion device 29 includes a channel/address setting RAM 291, a multiplexer 292, a latch circuit 293, and a gate circuit 29.
4, and has the function of converting the transmission line channel and the input/output address of the sequence controller. The input/output address of the sequence controller consists of 11 bits, and one address is assigned to each bit of data.
Each channel occupies 8 bits of data. Therefore, each channel has 1
Eight input/output addresses are occupied per channel. Therefore, channel/address settings
The RAM 291 stores a correspondence table between channel numbers and upper 8-bit input/output addresses.
The upper 8-bit address of the input/output address group exclusive to the channel set in the channel counter 21 is set in the latch circuit 293.
In addition, the channel/address setting RAM 291 is
A RAM that stores whether the channel corresponds to an input address group or an output address group, that is, whether it is an input channel or an output channel.
have. Therefore, this signal is also connected to the latch circuit 2.
93 and is used as a control signal for switching modes between transmission and reception. Eventually, the address signal of the upper 8 bits of the input/output address is output.
That is, in this embodiment, the maximum number of input/output channels is
It is 256. This correspondence table shows the computer 26,
It can be created using the console panel 27. Also, the lower 3 bits of the input/output address are
Sequentially set by clock 205.

On the other hand, the output data from the sequence controller 1 is transmitted via the data line D to the address bus 11.
The data is stored in three RAMs that are not accessed from the multiplex transmission line side at addresses set by . Data is output to the multiplex transmission line as follows. First, the contents of one memory unit selected at the corresponding address are sequentially outputted to the output shift register 202 by the clock 205 via the gate circuit 289 to the channel set in the channel counter 21. . Next, the parallel/serial converter 203 sends the serial data to the multiplex transmission line via the line driver/receiver 200.

In the above manner, the channel counter 21
The channel changes cyclically from the zero channel to the set maximum channel, and the channel/address conversion device 29 sets the upper address of the input/output address corresponding to the set channel at that time. Input data is input to the serial/parallel converter 22, and is input bit by bit to one RAM selected by the RAM selection circuit 206 via the addressable gate 201.

Figure 4 a and b are channel/address settings
3 is a diagram showing a data structure of RAM 291. FIG. Input/output addresses corresponding to channels #0 to #n are sequentially stored. The relative address where the input/output address is stored matches the channel number. Therefore, the channel signal is used as a relative address signal, and it is used as the start address of the table (SRM).
By adding , it is possible to obtain the absolute address that stores the input/output address corresponding to that channel. This absolute address (SRM+#)
The input/output address corresponding to channel # can be outputted to the data bus using the data. Further, as shown in FIG. 4b, the input/output mode of channel # can be accessed by similar processing, and an input/output mode control signal can be output to the data path.

The input/output address setting device is the computer 26
and a console panel 27. FIG. 5 is a plan view showing the console panel 27. FIG. A keyboard 270 is provided for inputting input/output addresses, an address display section 273 for displaying input/output addresses, and a channel display section 271 for displaying channels.

FIG. 6 is a flowchart showing the processing of the computer 26. In step 100, it is determined whether the selection key 275 has been operated, and if it has been operated, the input mode is converted in step 102.
The input mode is a mode that determines whether a value that can be input from the keyboard 270 is an input/output address or a channel, and the selected state of the mode is displayed by lighting on the mode display section 274. In step 104, it is determined whether the numeric keypad 270a has been operated. If it has been operated, the process moves to step 106, where the current input mode is determined and the input value is displayed on the display section on the mode side.
That is, if it is the input/output address mode, the input value is displayed on the input/output address display section 273 in step 108. If the channel mode is selected, the input value is displayed on the channel display section 271 in step 110. Below, to simplify the explanation,
The input and output addresses shall be set based on the channel. At step 110, the first channel number is entered and displayed. The computer cycles through steps 100, 112, 116, and 120, looping until a key is pressed. Next, when the selection key 275 is operated, the input mode is switched to the input/output address side in steps 100 and 102, and the input/output address corresponding to the channel displayed on the channel display section 271 can be input. The address is displayed on the input/output address display section 273 by operating the numeric keypad 270a. Next, in order to indicate whether the channel is an input channel or an output channel, the input/output mode keys 270b and 270c are operated to set the input/output mode in step 114.
This is displayed on the mode display section 276. Next, when the write key 270d is operated, a determination is made in step 116, and an address to be stored is calculated from the channel number in step 118.
Set the input/output address in RAM291. Similarly, the input/output mode is also set. In this way, the input/output address corresponding to the first channel is set. Next, when the update keys 270e and 270f are operated, the display value of the unselected input mode side, that is, the channel, is changed by +1 or -1 in step 122.
Update it so that the input/output address of the next channel can be set. Next, enter the input/output address and perform the same operation as above to set the input/output address. In this way, input and output addresses can be set by sequentially changing the numbers for all channels.

The above example explained the setting method based on the channel, but using the input/output address as the reference,
You can also input and set channel numbers sequentially.

The duplicate setting detection device is composed of a computer 26 and a console panel 27 similarly to the input/output address setting device. The duplicate setting detection device has a function of detecting that the input/output address set by the input/output address setting device is set redundantly for different channels. FIG. 7 is a flowchart showing the processing of the computer 26, and FIG. 8a, like FIG. 4a, specifically displays the contents of the channel/address setting RAM. FIG. 8b is a correspondence table between input/output addresses and channels created in order to detect input/output addresses that have been set overlappingly. The calculator begins execution at step 200.
The routine from step 200 to step 210 uses the input/output address table formed in the channel/address setting RAM 291 to create a table (b) in FIG. This is a routine to create. IOADC is a parameter indicating the input/output address. In step 202,
The channel/address setting RAM is accessed for the input/output address indicated by the IOADC, and the address where it is stored is detected. At step 204
the input/output addresses identified by the IOADC,
At the same time, the address where it is stored, ie, the channel number, is created as shown in the system table of FIG. 8b. In step 208, the value of IOADC is updated by 1, and the search is repeated again from step 202, thereby creating the table shown in FIG. 8b as a system table.

Next, proceed to step 212 and set the value of the parameter ROC to the start address STAD of the created table.
In step 214, the content of the address specified by the ROC is displayed on the input/output address display section 273. Next, the process moves to step 216, where the value of the ROC is updated by 1, and the process moves to step 218, where the content of the address specified by the ROC, that is, the channel number, is displayed on the channel display section 271. As a result, the input/output addresses and their corresponding channel numbers are displayed in descending order of input/output address. Next, proceed to step 220, wait for key input, and proceed to step 220.
When the "+1" key is operated in 224, step 226
Then, the ROC value is updated by 1, and the process moves to step 214. That is, the next table is accessed to display the next input/output address and the corresponding channel. Also, at step 228, “-1”
When the key is input, the process moves to step 230 and the previous input/output address is displayed again. In this way, input/output addresses and corresponding channel numbers can be sequentially displayed on the input/output address display section 273 and the channel display section 271 by operating the "+1" key 270e and the "-1" key 270f. Therefore, if there is a duplicate setting, the input/output address will not change, but the channel number will change. This makes it possible to easily detect duplicate settings of input/output addresses. In the above embodiment, as an example, duplicate settings are detected by sequentially displaying input/output addresses and their channels. However, the present invention is not limited to these embodiments, and the overlap may be automatically detected and its input/output address and channel displayed.

[Effects of the Invention] The present invention provides a channel/address translation device with the following features:
A storage device is used that stores input and output addresses at addresses specified by channel numbers.
Therefore, when a channel signal is input from the address bus of the storage device, the stored input/output address signal is output to the data bus, and channel/address conversion can be easily performed. or,
Since the above method has a high degree of integration, it is possible to increase the number of conversion channels in one device.
In addition, the channel/input/output address conversion device includes
Because the input/output address setting device is connected,
You can easily set and change addresses. Further, the duplicate setting detection device can easily detect duplicate settings of input/output addresses, prevent system runaway, and facilitate system change design.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a multiplex transmission interface according to a specific embodiment of the present invention. FIG. 2 is a block diagram showing the overall configuration of the multiplex transmission device. Third
The figure is a waveform diagram showing signal waveforms appearing on multiple transmission lines. FIG. 4 is a structural diagram showing the data structure of the channel/address setting RAM of the embodiment device. FIG. 5 is a plan view showing the console panel of the same embodiment device. FIG. 6 is a flowchart showing the computer processing of the apparatus of the embodiment. FIG. 7 is a flowchart showing the processing of the computer 26. FIG. 8 is a configuration diagram showing a system table created through processing by the same computer. P1...Reset pulse, P2, P4...Data signal, P6...Channel count pulse, 2
71...Channel display section, 272...Data display section, 270...Keyboard.

Claims (1)

[Scope of Claims] 1. A multiplex transmission device for a sequence controller, comprising an interface for connecting a time-division multiplex transmission line to which a plurality of transmitter/receiver units are connected and a sequence controller, the interface comprising: , a channel counter connected to the multiplex transmission line and inputting a count pulse for determining a channel of the multiplex transmission line; and a buffer disposed between the sequence controller and the multiplex transmission line, the buffer disposed between the sequence controller and the multiplex transmission line. a data storage device connected to the address bus of the channel counter and accessed by specifying an input/output address; and a data storage device that stores the input/output address corresponding to the channel, connects the address bus to the channel counter, and connects the data bus to the channel counter; a channel/address translation device comprising a storage device connected to the address bus for accessing a data storage device and converting the channel and input/output address; and a channel/address translation device capable of accessing the device. an input/output address setting device that is connected and sets the input/output address corresponding to the channel to the channel/address conversion device; and detects duplicate settings of the input/output address set by the channel/address setting device. 1. A multiplex transmission device for a sequence controller, comprising: a duplicate setting detection device for displaying duplicate input/output addresses.