JPH0339420B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention connects input/output elements such as limit switches and relays provided in each of a plurality of machine units and a sequence controller via multiple transmission lines. The present invention relates to a multiplex transmission device configured to do so.

In particular, the present invention relates to a multiplex transmission device having a function of easily and variably converting input/output addresses of input/output elements to be controlled by a sequence controller and a channel of a multiplex transmission line.

[Conventional technology]

BACKGROUND ART Conventionally, a control system is known in which a large number of machine units are time-divisionally controlled by a sequence controller via a serial transmission line as a system for synchronously controlling a large number of machine units.

This control system consists of a master control unit 3 that controls the channels, as shown in Figure 2.
, a multiplex transmission line 4, a sequence controller 1 that controls each machine unit, a multiplex transmission interface 2 that is an interface between the sequence controller 1 and the multiplex transmission line 4, and a multiplex transmission line 4 connected to each machine unit. Transmitting units 52, 53 and receiving unit 5 arranged in the unit
It consists of 1,54 mag.

The master control unit 3 sequentially outputs a reset pulse P1 and a channel count pulse P6, as shown in FIG. Each transmitter/receiver unit has a specific channel number set by a deep switch 531, 511, etc., and when the value of its channel counter 532, 512 becomes equal to the set channel number, The identified transmitter/receiver unit outputs the data signals P2, P4 to the multiplex transmission line, or outputs the data signals P2, P4 from the multiplex transmission line.
Enter 4.

The reset pulse P1 outputted by the master controller unit 3 resets the contents of the channel counters 532, 512 of each transmitting/receiving unit and the channel counter of the multiplex transmission interface 2, and sets the channel number to zero. In addition, the channel count pulse P6 is outputted from the master control unit 3 at a constant cycle, and updates the value of each channel counter by 1.
The used channels of the transmission line are sequentially updated. When the set maximum channel is reached, a reset pulse P1 is outputted, and the transmission line is again time-division multiplexed sequentially starting from the zero channel.

In this way, the master control unit 3
The channels of the transmission line are controlled in a time-division manner, and each transmitter/receiver unit
When the transmission line is set, data can be sent and received to and from the sequence controller 1. In the above manner, the transmitting units 52, 53
can output the states of input elements such as limit switches, operation switches, and relay contacts to the sequence controller 1 using their respective channels, and the sequence controller 1 can output the states of input elements such as limit switches, operation switches, and relay contacts to the receiving units 51 and 54 through their respective channels. can be used to output a signal indicating the operating state of an output element such as a lamp or relay coil.

A conventional multiplex transmission device has the above-described configuration and operation and controls a plurality of machine units by a sequence controller.

[Problem that the invention seeks to solve]

The multiplex transmission system is provided with a multiplex transmission interface 2 which is an interface between the sequence controller 1 and the multiplex transmission line 4. This multiplex transmission interface 2 is a device that performs mutual conversion between data controlled independently by a sequence controller in units of input/output addresses and data time-division multiplexed in units of channels.
Therefore, in this multiplex transmission interface 2,
A device is required to perform mutual conversion between the channel and the input/output address of the control unit of the sequence controller, and it is desirable in terms of system design and operation that this correspondence relationship can be easily changed. However, in the conventional device, a depth switch is provided for each channel, and corresponding input/output addresses are set. For this reason, the volume of the device is large;
It was not possible to increase the number of channels per multiplex transmission device. Furthermore, since a code generator corresponding to the operating state of the decoder and depth switch is used to convert the channel to the input/output address, the circuit configuration is complicated.

Therefore, the present invention has been made to improve the above-mentioned drawbacks, and it facilitates conversion of channels/input/output addresses and their settings and changes, and also increases the number of conversion channels by improving the degree of integration. The purpose is to

[Means for solving problems]

The present invention provides an interface that connects a time-division multiplex transmission line to which a plurality of transmitter/receiver units are connected and a sequence controller, and a count that is connected to the multiplex transmission line and that determines the channel of the multiplex transmission line. a channel counter for inputting pulses; a buffer disposed between the sequence controller and the multiplex transmission line, connected to the address bus of the sequence controller, and accessed by input/output address designation; said channel comprising a data storage device; and a storage device for storing said input/output addresses corresponding to said channel, having an address bus connected to said channel counter, and a data bus connected to said address bus for accessing said data storage device; a channel/address conversion device that mutually converts input and output addresses; and a channel/address conversion device that is connected to the channel/address conversion device so that the device can be accessed, and that converts the input/output address corresponding to the channel to the channel/address conversion device. The present invention is characterized in that it includes an input/output address setting device for setting in the device.

The apparatus of the present invention is characterized in that the conversion device for converting a channel and an input/output address uses a storage device that stores, as data, an input/output address corresponding to the channel at an address specified by the channel. It is said that Therefore, by accessing the storage device using the channel signal as an address signal, the input/output address signal can be taken out on the data line, and channel/input/output address conversion is easily performed. Further, the conversion device is provided with an input/output address setting device for setting an input/output address corresponding to each channel, and the input/output address can be set in the storage device by this device.

The value of the channel counter indicates a number that changes sequentially, indicating that the transmission line is currently being used for the channel of that number. Seen from the sequence controller, each channel is divided into an input channel and an output channel for input elements and output elements. The input channel is a channel for transmitting data from the transmitting unit to the sequence controller side, and the output channel is a channel for outputting data from the sequence controller to the receiving unit. Therefore, input channels correspond to input addresses, and output channels correspond to output addresses.

The data storage device is accessed by the sequence controller by specifying an input/output address, and at the same time, it is also accessed by the channel/address conversion device. Typically, one channel carries data that controls multiple input or output elements, so one channel corresponds to a group of input or output addresses. Therefore, the input/output address corresponding to the channel is represented by a representative value of the input/output address group.

The channel/address translation device is connected so as to be accessible from both the channel counter and the input/output address setting device.

[Effect]

First, an input/output address corresponding to each channel is set using an input/output address setting device. In this state, the system is in operation, and channels are sequentially switched in a time-division manner, and data on each channel is transmitted and received. Now, if the channel counter indicates the 0th channel,
A corresponding input/output address signal of the 0th channel is generated on the data bus of the channel/address conversion device. By using this input/output address signal as the address signal of the data storage device (for example, an upper address signal), the input/output address group exclusive to that channel can be accessed, and the received data of that channel can be sequentially stored in the corresponding address. Or, conversely, by sequentially accessing the corresponding input/output address group of that channel, serial data can be output to that channel.

〔Example〕

Hereinafter, the present invention will be explained in detail based on specific examples.

FIG. 1 is a block diagram showing the configuration of a multiplex transmission apparatus according to a specific embodiment of the present invention.

FIG. 2 is a block diagram showing the overall configuration of a multiplex transmission device having a multiplex transmission interface 2. As shown in FIG.

The multiplex transmission line 4 (serial transmission line) is connected to the line driver/receiver 200,
Line driver/receiver 200 outputs data signals to multiplex transmission line 4 and receives channel count pulses and data signals from multiplex transmission line 4 . Connected to the line driver/receiver 200 are a channel counter 21 that inputs channel count pulses, and a serial/parallel converter 22 that converts received data from serial data to parallel data. The serial/parallel converter 22 is an addressable gate 201
is connected to the data storage device 28 via the data storage device 28, and the received data is stored in addresses that differ one bit at a time. Data storage device 28 is a storage unit.
RAM281, RAM282, RAM283,
It consists of RAM 284, which are 1-bit RAMs that are accessed at the same address. each
The RAM further includes multiplexers 285, 28
6,287,288, address bus 11 of sequence controller 1, channel/
It is accessed from both address buses 291 on the address conversion device 29 side. RAM selection circuit 206
The RAM 281, 282, 28
3,284 are selected in sequence. In other words, there are 4 RAMs for storing data for all input/output addresses.
It is input from the multiplex transmission line and stored for each channel multiplexing period.
RAM is switched. The double matching circuit 207 has three
It has a function of taking the majority value of the contents of the RAM, and the sequence controller 1 can read the input element data stored in the data storage device 28 as the majority value.

The channel/address conversion device 29 includes a channel/address setting RAM 291, a multiplexer 292, a latch circuit 293, and a gate circuit 294.
It has the function of converting the transmission line channel and the input/output address of the sequence controller. The input/output address of the sequence controller consists of 11 bits, and one address is assigned to each bit of data. Each channel occupies 8 bits of data. Therefore, each channel has eight dedicated input/output addresses per channel. Therefore, channel/address settings
The RAM 291 stores a correspondence table between channel numbers and upper 8-bit input/output addresses.
The upper 8-bit address of the input/output address group exclusive to the channel set in the channel counter 21 is set in the latch circuit 293.
In addition, the channel/address setting RAM 291 is
A RAM that stores whether the channel corresponds to an input address group or an output address group, that is, whether it is an input channel or an output channel.
have. Therefore, this signal is also connected to the latch circuit 2.
93 and is used as a control signal for switching modes between transmission and reception. Eventually, the address signal of the upper 8 bits of the input/output address is output.
That is, in this embodiment, the maximum number of input/output channels is
It is 256. This correspondence table shows the computer 26,
It can be created using the console panel 27. Also, the lower 3 bits of the input/output address are
Sequentially set by clock 205.

On the other hand, the output data from the sequence controller 1 is transmitted via the data line D to the address bus 11.
The data is stored in three RAMs that are not accessed from the multiplex transmission line side at addresses set by . Data is output to the multiplex transmission line as follows. First, channel counter 21
The contents of the memory unit 1 selected at the address corresponding to the channel set to
The signals are sequentially outputted by the clock 205. Next, parallel/serial converter 203
serial data is sent out to multiple transmission lines via line driver/receiver 200.

In the above manner, the channel counter 21
The channel changes cyclically from the zero channel to the set maximum channel, and the channel/address converter 29 sets the upper address of the input/output address corresponding to the set channel at that time. Input data is serial/parallel converter 2
2, and is input to one RAM selected by the RAM selection circuit 206 one bit at a time via the addressable gate 201.

Figure 4 a and b are channel/address settings
3 is a diagram showing a data structure of RAM 291. FIG. Input/output addresses corresponding to channels #0 to #n are sequentially stored. The relative address where the input/output address is stored matches the channel number. Therefore, the channel signal is used as a relative address signal, and it is used as the start address of the table (SRM).
By adding , it is possible to obtain the absolute address that stores the input/output address corresponding to that channel. This absolute address (SRM+#I)
The input/output address of channel #I can be output to the data bus. Further, as shown in FIG. 4b, the input/output mode of channel #I can be accessed by similar processing, and the input/output mode control signal can be output to the data bus.

The input/output address setting device is the computer 26
and a console panel 27. FIG. 5 is a plan view showing the console panel 27. FIG. A keyboard 270 is provided for inputting input/output addresses, an address display section 273 for displaying input/output addresses, and a channel display section 271 for displaying channels.

FIG. 6 is a flowchart showing the processing of the computer 26. In step 100, it is determined whether the selection key 275 has been operated, and if it has been operated, the input mode is converted in step 102. The input mode is a mode that determines whether the value that can be input from the keyboard 270 is an input/output address or a channel, and the selected state of the mode is displayed by lighting on the mode display section 274. In step 104, the numeric keypad 270a
Determine whether the has been manipulated, and if so,
The process moves to step 106, where the current input mode is determined, and the input value is displayed on the display section on the mode side. That is, if it is the input/output address mode, the input/output address display section 2 is displayed in step 108.
The input value is displayed at 73. If the channel mode is selected, the input value is displayed on the channel display section 271 in step 110. Hereinafter, to simplify the explanation, it is assumed that input/output addresses are set based on channels. At step 110,
The first channel number is entered and displayed. The computer steps 100, 112, 116,
120 is executed cyclically and loops until a key is input. Next, when the selection key 275 is operated, the input mode is switched to the input/output address side in steps 100 and 102, and the input/output address corresponding to the channel displayed on the channel display section 271 can be input. The address is displayed on the input/output address display section 273 by operating the numeric keypad 270a. Next, in order to indicate whether the channel is an input channel or an output channel, the input/output mode keys 270b and 270c are operated to set the input/output mode in step 114. This is displayed on the mode display section 276. Next, write key 2
When 70d is operated, it is determined in step 116, and in step 118, the address to be stored is calculated from the channel number, and the address is stored in the RAM.
291 to set the input/output address. Similarly,
Also set the input/output mode. In this way, the input/output address corresponding to the first channel is set. Next, when the update keys 270e and 270f are operated, the display value of the unselected input mode side, that is, the channel, is updated by +1 or -1 in step 122, and the input/output address of the next channel can be set. . Next, enter the input/output address and perform the same operation as above to set the input/output address. In this way, input and output addresses can be set by sequentially changing the numbers for all channels.

The above example explained the setting method based on the channel, but using the input/output address as the reference,
You can also input and set channel numbers sequentially.

〔Effect of the invention〕

The present invention provides a channel/address translation device that includes:
A storage device is used that stores input and output addresses at addresses specified by channel numbers.
Therefore, when a channel signal is input from the address bus of the storage device, the input/output address signal to be stored is output to the data bus, and channel/address conversion can be easily performed. Further, because of the above method, the degree of integration is high and the number of conversion channels in one device can be increased.
In addition, the channel/input/output address conversion device includes
Because the input/output address setting device is connected,
You can easily set and change addresses.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an interface section of a multiplex transmission apparatus according to a specific embodiment of the present invention. FIG. 2 is a block diagram showing the overall configuration of the control system. FIG. 3 is a waveform diagram showing signal waveforms appearing on multiplex transmission lines. FIG. 4 is a structural diagram showing the data structure of the channel/address setting RAM of the embodiment device. FIG. 5 is a plan view showing the console panel of the same embodiment device. 6th
The figure is a flowchart showing computer processing included in the apparatus of the embodiment. P1...Reset pulse, P2, P4 data signal, P6...Channel count pulse, 271...
Channel display section, 272...Data display section, 27
0...Keyboard.

Claims (1)

[Scope of Claims] 1. A multiplex transmission device for a sequence controller, comprising an interface for connecting a time-division multiplex transmission line to which a plurality of transmitter/receiver units are connected and a sequence controller, the interface comprising: , a channel counter connected to the multiplex transmission line and inputting a count pulse for determining a channel for data transmission via the multiplex transmission line; and a buffer disposed between the sequence controller and the multiplex transmission line. a data storage device connected to the address bus of the sequence controller and accessed by specifying an input/output address; and a data storage device that stores the input/output address corresponding to the channel, and connects the address bus to the channel counter. a channel/address translation device for translating input/output addresses with said channel comprising a storage device connected to said address bus for accessing said data storage device; A multiplex transmission device for a sequence controller, comprising: an input/output address setting device that is connected to allow access to the device and sets the input/output address corresponding to the channel to the channel/address conversion device.