JPH0332938B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention connects input/output elements such as limit switches and relays provided in each of a plurality of machine units and a sequence controller via multiple transmission lines. The present invention relates to a multiplex transmission device configured to do so.

In particular, the present invention relates to a multiplex transmission device in which a sequence controller smoothly performs asynchronous operations on multiple transmission lines, eliminates errors in received data, and improves reliability.

[Prior Art] Conventionally, as a system for synchronously controlling a large number of machine units, there has been known a control system that performs time-division control using a sequence controller via a serial transmission path.

This control system consists of a master control unit 3 that controls the channels, as shown in Figure 2.
, a multiplex transmission line 4, a sequence controller 1 that controls each machine unit, a multiplex transmission interface 2 that is an interface between the sequence controller 1 and the multiplex transmission line 4, and a multiplex transmission line 4 connected to each machine unit. It consists of transmitting units 52, 53, receiving units 51, 54, etc. arranged in the machine unit.

The master control unit 3 sequentially outputs a reset pulse P1 and a channel count pulse P6, as shown in FIG. Each transmitting/receiving unit 51 to 54 has a deep switch 531, 511.
etc., and when the value of its channel counter 532, 512 becomes equal to the set channel number, the transmitting/receiving unit specified by that channel number performs multiplex transmission. Data signal P on line 4
2 and P4, and input data signals P2 and P4 from the multiplex transmission line 4.

The reset pulse P1 outputted by the master control unit 3 resets the contents of the channel counters 532, 512 of each transmitting/receiving unit and the channel counter of the multiplex transmission interface 2, and sets the channel number to zero. In addition, the channel count pulse P6 is outputted from the master control unit 3 at a constant cycle, and updates the value of each channel counter by 1.
The used channels of the transmission line are sequentially updated. When the set maximum channel is reached, a reset pulse P1 is outputted, and the transmission line is again time-division multiplexed sequentially starting from the zero channel.

That is, in FIG. 3, the reset pulse P1
The period between the channel count pulse P6 and the channel count pulse P6 constitutes a time-division channel. Similarly, the next channel is between the channel count pulse P6 and the next channel count pulse (not shown) that follows after a certain period of time. Further, there is one multiplexing period between the reset pulse P1 and the next reset pulse (not shown).
For example, data signals P2 and P4 on the channels shown in FIG.
P3 is a check pulse for separating temporally adjacent data signals 2 and P4 within one channel, and P5 is a check pulse for separating channel count pulse P6 and the immediately preceding data signal P4. be.

In this way, the master control unit 3
The channels of the multiplex transmission line 4 are controlled in a time-division manner, and each transmitting/receiving unit 51 to 54 connects the transmission line to the sequence controller 1 via the multiplex transmission interface 2 when a transmission line is set for the channel it has. You can send and receive data. In the above manner, the transmitting unit 52,
53 can output the states of input elements such as limit switches, operation switches, relay contacts, etc. to the sequence controller 1 using the respective channels, and the sequence controller 1
can output signals indicating the operating states of output elements such as lamps and relay coils to the receiving units 51 and 54 using their respective channels.

A conventional multiplex transmission device has the above-described configuration and operation and controls a plurality of machine units by a sequence controller.

[Problems to be Solved by the Invention] The multiplex transmission device is provided with a multiplex transmission interface (hereinafter also simply referred to as an interface) 2, which is an interface between the sequence controller 1 and the multiplex transmission line 4. ing. The sequence controller 1 controls input/output elements by specifying input/output addresses, and the multiplex transmission line 4 collectively transmits data indicating the status of a plurality of input/output elements of the transmitting/receiving units 51 to 54. Each unit transmits on one channel at a time. Normally, an interface is required between the multiplex transmission line 4 and the sequence controller 1.

The conventional interface 2 interrupts the sequence controller 1 when receiving channel data, and the sequence controller 1 sequentially converts the channel data into data at the corresponding input address and inputs it.
Data at corresponding output addresses were sequentially output to the multiplex transmission line 4 in response to an interrupt. Therefore, it took a long time to scan the data of the sequence controller 1, and it was not possible to shorten the channel switching period. Furthermore, the transmitted and received data has no parity bit and is susceptible to noise.

Therefore, the present invention operates the sequence controller asynchronously with respect to the transmission line, and enables high-speed,
By making input/output addresses accessible at all times, the purpose is to facilitate high-speed data transmission and reception, eliminate errors in received data, and improve reliability of the device.

[Means and effects for solving the problems] The present invention provides an interface connecting between the sequence controller and a time-division multiplex transmission line to which a plurality of transmitting and receiving units are connected, and the sequence controller and the multiplex transmission line. A buffer disposed between transmission lines, connected to an address bus of the sequence controller and an address bus of a transmission/reception control device that controls transmission and reception of signals, and configured to receive input/output addresses from the sequence controller and the transmission/reception control device. a data storage device consisting of four or more memory units connected in parallel that can be accessed according to the specifications of The transmission/reception control device transmits and receives channel data between the multiple transmission line and the data storage device by inputting the input/output address to the data storage device and sequentially accessing the channels; and the data storage device. One storage unit constituting the device is controlled so that it can be accessed only by the transmission/reception control device, and the remaining three or more odd number storage units are controlled so that it can be accessed only from the sequence controller, and the time-division multiplexed a memory unit selection device that inputs a reset pulse indicating a channel multiplexing period from the multiplex transmission line and changes the one storage unit each time the reset pulse is input; a majority value calculation device for determining a majority value of the data stored in the three or more odd number of storage units and using the majority value as input data to the sequence controller. This is a multiplex transmission device.

The device of the present invention has a data storage device that stores data of input/output elements of all input/output addresses of a sequence controller and has a buffer function for a transmission path. This data storage device is
It consists of four or more storage units connected in parallel. One of the storage units sends and receives data to and from multiplex transmission lines. Among the other memory units, three or more odd number memory units are separated from the multiplex transmission line and read/written by the sequence controller.

When reading from the sequence controller,
A majority value arithmetic device is provided which uses, as read data, the majority value of the data stored at the input address of each of the three or more odd number storage units to be accessed. The above storage unit selection is configured to be switched in synchronization with the channel multiplexing cycle, and the storage unit selection device has this function. When a sequence controller writes, data is simultaneously output to multiple storage units connected to the sequence controller. The transmission/reception control device outputs data to the multiplex transmission line and inputs data from the multiplex transmission line by accessing the input/output address of one storage unit corresponding to the channel on the multiplex transmission line. A data storage device is provided between the sequence controller and the multiplex transmission line, and the storage unit connected to the sequence controller by the storage unit selection device and the storage unit connected to the multiplex transmission line are different. Therefore, the two are completely separated. Therefore, the sequence controller and the transmission line side can be independently controlled. Data input to a storage unit from multiple transmission lines can be accessed during the next multiplexing cycle when the storage unit is connected to a sequence controller. Since the storage units connected to the multiplex transmission line are switched at each multiplexing cycle, data input from the multiplex transmission line in each different multiplexing cycle is sequentially stored in each storage unit. Therefore, the data read by the sequence controller is the majority value of the data received during a plurality of past multiplex cycles. Therefore, decimal data that differs only during one multiplex cycle is not employed, and errors are removed when the signal is temporarily inverted due to noise or the like. The output from the sequence controller is
Since this is carried out for the remaining plurality of storage units, it is output to the transmission line with a delay of one multiple cycle. In the manner described above, highly reliable, high-speed, and smooth data transmission and reception can be performed.

[Examples] Hereinafter, the present invention will be described in detail based on specific examples.

FIG. 1 is a block diagram showing the configuration of a multiplex transmission interface according to a specific embodiment of the present invention.

FIG. 2 is a block diagram showing the overall configuration of a multiplex transmission device having a multiplex transmission interface 2. As shown in FIG.

The multiplex transmission line 4 (serial transmission line) is connected to the line driver/receiver 200 of the interface 2.
connected to the line driver/receiver
200 outputs the data signal to the multiplex transmission line 4,
Channel count pulses and data signals are received from the multiplex transmission line 4. Connected to the line driver/receiver 200 are a channel counter 21 that inputs channel count pulses, and a serial/parallel converter 22 that converts received data from serial data to parallel data. The serial/parallel converter 22 is connected to the data storage device 28 via the addressable gate 201, and the received data is sent to a physical address (address) of the data storage device 28 that differs by one bit.
is memorized. The data storage device 28 includes a RAM 281 and a RAM 2, which respectively constitute a storage unit.
82, RAM 283, and RAM 284, these RAMs are accessed by the same physical address and input/output 1-bit data. each
The RAM further includes multiplexers 285, 28
6,287,288, address bus 11 of sequence controller 1, channel/
It is accessed from both address buses 291 on the address conversion device 29 side. That is, multiplexers 285 to 288 select one of address bus 11 and address bus 291.

RAM selection circuit 2 which is a storage unit selection device
06, each time a reset pulse is input from the multiplex transmission line 4, the RAMs 281, 282, 283, 2
84 are selected in sequence. In addition, the reset pulse is
As mentioned above, it is periodically output from the master control unit 3 at the beginning of the multiplexing cycle.

That is, accessable through a common input/output address.
There are four RAM (memory units),
Further, the RAM to be connected to the multiplex transmission line 4 is switched every channel multiplexing period (details of switching will be described later).

The double matching circuit (majority value calculation device in the present invention) 207 has a function of taking the majority value of the contents of the three RAMs that are not accessed from the multiplex transmission line 4 side, and the sequence controller 1
reads the data stored in the data storage device 28 as the majority value.

The channel/address conversion device (transmission/reception control device in the present invention) 29 includes a channel/address setting RAM 291, a multiplexer 292, and a latch circuit.
293, consists of a gate circuit 294, and the address of the channel of the multiplex transmission line 4 (i.e., the cumulative value of the channel count pulse P6 (see Fig. 3))
and the input/output address of the sequence controller 1. The input/output address of the sequence controller 1 consists of 11 bits, and can specify 2 ¹¹ =2048 transmitting/receiving units. On the other hand, each channel on the multiplex line 4 exclusively holds 8 bits of data. Therefore, each channel has 8
It has exclusive input/output addresses. Note that the upper 8 bits of the 8 input/output addresses occupied by the 8-bit data in one channel are common, and these are distinguished by the lower 3 bits. Incidentally, FIG. 3 shows one channel of a conventional device, and each channel has 2 bits of data. Also, channel/address settings
The RAM 291 stores a correspondence table between the channel number specified by the cumulative value of the channel count pulse and the upper 8 bits of the input/output address, and stores the 8 input/outputs exclusively occupied by the channel set in the channel counter 21. The upper 8 bits of the input/output address are set in the latch circuit 293 in order to specify addresses all at once. The channel/address setting RAM 291 also has a read/write designation RAM that stores whether the channel corresponds to either the input address group or the output address group, that is, whether it is an input channel or an output channel. are doing. Therefore, this signal also
The signal is output to the latch circuit 293 and used as a control signal R/W for switching modes between transmission and reception.
Eventually, from the latch circuit 293 to the multiplexer 28
The upper 8 bits of the input/output address are output from 5 to 288. That is, in this embodiment, the maximum number of input/output channels is specified by the upper 8 bits of the 11-bit input/output address, so 2 ⁸ =256. This correspondence table shows the computer 26, console panel 2
It can be created using 7. Further, the lower three bits of the input/output address described above are set serially by the clock circuit 205.

On the other hand, the output data from the sequence controller 1 is transmitted via the data line D to the address bus 11.
The data is stored in three RAMs that can be accessed by (not accessed from the multiple transmission line 4 side).

Data is output to the multiplex transmission line 4 as follows. First, channel counter 21
The data of one storage unit in which the input/output address group corresponding to the channel set by is selected is sequentially output to the output shift register 202 via the gate circuit 289 in accordance with the clock circuit 205. Next, this data is output in parallel from the input/output shift register 202 to the parallel/serial converter 203, where it is converted into serial data and sent to the line driver/receiver 203.
The signal is sent out to the multiplex transmission line 4 via.

In the above manner, the channel counter 21
The channel/address converter 29 changes cyclically from the zero channel to the maximum channel.
sets the common upper 8 bits of the 8 input/output addresses corresponding to the channel at that time.

The input data from the multiplex transmission line 4 is serial/
The data is input to the parallel converter 22, and is input to one RAM selected by the RAM selection circuit 206 one bit at a time via the addressable gate 201.

Figure 4 a and b are channel/address settings
3 is a diagram showing a data structure of RAM 291. FIG. Input/output addresses corresponding to channels #0 to #n are sequentially stored. The relative (virtual) address of the table in which input/output addresses are stored matches the channel number. Therefore, by using the channel number as a relative address signal and adding it to the top address (SRM) of the table, it is possible to obtain the absolute (physical cell) address that stores the input/output address corresponding to that channel. This absolute address (SRA+#) allows the input/output address of channel # to be output to the data bus. Also, by referring to the table shown in FIG. 4B, the input/output mode of channel #1 can be accessed and an input/output mode control signal can be output to the data bus. The input/output address setting device is composed of a computer 26 and a console panel 27. FIG. 5 is a plan view showing the console panel 27. FIG. A keyboard 270 is provided for inputting input/output addresses, an address display section 273 for displaying input/output addresses, and a channel display section 271 for displaying channels.

A double matching circuit 207 is provided as a majority value calculation device. The double verification circuit 207 is a RAM
Three output signals selected from 281, 282, 283, and 284 are input, and data accessed by the sequence controller 1 is input.

FIG. 6 shows a specific configuration of the double matching circuit 207. 208 is gate IC (LS151)
It is. A, B, C and D1 (D2 and D4) terminals are
AND gates 209a, 209b, 209c, 2
The output signal of 09d is input. Them
Each AND gate is data of RAM281.
DATA1, RAM282 data DATA2, RAM
283 data DATA3, RAM284 data
DATA4 and an inverted signal of the storage unit selection signal (positive logic) output from the RAM selection circuit 206 are input. Therefore, only the data signals of the RAMs not selected by the RAM selection circuit 206, that is, the RAMs that can be accessed by the sequence controller 1, are sent to the gate ICs 208, A, B, C, etc.
It is input to any three of the D1 terminals, and the remaining one terminal is always at a low level during one multiplexing period. Data terminal DO is at low level, D3, D5, D6,
A high level signal is input to D7.

In this gate circuit LS151, when two or more terminals among A, B, and C are at high level "1", the output of the Y terminal becomes high level "1". Also, A, B,
When only one of the C terminals is at high level "1" and the others are at low level "0", the DATA4 signal is output from the Y terminal. That is, when the DATA4 signal is at a high level "1", a high level "1" signal is output from the Y terminal, and when the DATA signal is at a low level "0", a low level "0" signal is output from the Y terminal. Further, when all terminals A, B, and C are at low level "0", the address becomes 0, and a low level "0" signal is output from the Y terminal regardless of the state of the DATA4 signal. After all, DATA1
When two or more of the ~DATA4 signals become high level, a high level signal is output, and when three or more become low level, a low level signal is output. Considering that a low level signal that has not been accessed is input to any one terminal, the majority value of the three accessed data signals will be output from the Y terminal. The output signal from this Y terminal becomes input data to the sequence controller 1. Naturally, such majority voting circuit can be replaced by other hardware or software.

FIG. 7 is a logic table showing the above logic.

As described above, sequence controller 1
The multiplex transmission line 4 can perform data scanning independently and separately from the multiplex transmission line 4, and therefore the multiplex transmission line 4 can perform transmission at the timing of the conventional multiplex system.

[Effects of the Invention] The present invention has a data storage device that performs a buffering action between a sequence controller and a multiplex transmission line and can be accessed independently by both. Therefore, since the sequence controller can access data independently of the transmission line, high-speed processing can be performed from the perspective of the sequence controller, and since the multiple transmission lines are not synchronized with the sequence controller, it reduces the transmission speed. Never. Furthermore, the data storage device has a plurality of storage units, and provides the sequence controller with a majority value of the output data of each storage unit. Therefore, errors caused by noise can be eliminated and the system can be made highly reliable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a multiplex transmission interface according to a specific embodiment of the present invention. FIG. 2 is a block diagram showing the overall configuration of a control system related to the conventional interface and the present invention. Figure 3 shows
FIG. 2 is a waveform diagram showing waveforms of signals appearing on multiple transmission lines in a conventional control system. Figure 4 shows the channel/address settings of the example device.
FIG. 3 is a structural diagram showing the data structure of RAM. Fifth
The figure is a plan view showing the console panel of the device of the same embodiment. FIG. 6 is a block diagram showing the configuration of the majority value calculation device of the same embodiment. FIG. 7 is a logic diagram explaining the logic.

Claims (1)

[Scope of Claims] 1. A multiplex transmission device for a sequence controller, comprising an interface for connecting a time-division multiplex transmission line to which a plurality of transmitter/receiver units are connected and a sequence controller, the interface comprising: , a buffer disposed between the sequence controller and the multiplex transmission line, the buffer being connected to an address bus of the sequence controller and an address bus of a transmission/reception control device that controls transmission and reception of signals; A data storage device consisting of four or more storage units connected in parallel that can be accessed by specifying input/output addresses from a transmission/reception control device, and a pulse for determining a channel is input from the multiplex transmission line, The input/output address corresponding to the time-division channel is input to the data storage device and the channels are sequentially accessed, thereby transmitting and receiving channel data between the multiplex transmission line and the data storage device. A transmission/reception control device and one storage unit constituting the data storage device are controlled to be accessible only from the transmission/reception control device, and the remaining three or more odd numbered storage units are controlled to be accessible only from the sequence controller. , a storage unit selection device that inputs a reset pulse indicating the multiplexing period of the time-division multiplexed channel from the multiplex transmission line and changes the one storage unit each time the reset pulse is input; and the sequence. a majority value arithmetic device which calculates a majority value of the data stored in the three or more odd number of storage units to be accessed when read from the controller, and uses the majority value as input data to the sequence controller; A multiplex transmission device for a sequence controller, characterized in that: