JPH0148577B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Technical Field of the Invention The present invention relates to a shared control system, particularly a case where a plurality of input/output control devices that share a plurality of input/output devices are shared by a plurality of upper channels. This is related to a shared control method that rejects an input/output request when an input/output device is reserved from another upper channel and an input/output request is made to that input/output device from another upper channel. be.

B. Prior art and its problems In a shared control system in which multiple input/output control devices that share multiple input/output devices are shared by multiple upper channels, a certain input/output device is reserved by a certain channel. If an input/output request is made to the input/output device from another channel while the input/output device is running, it is necessary to perform exclusive control to reject this input/output request.

As a shared control method that performs exclusive control, as shown in FIG. 1, n+1 input/output devices D ₀ , D ₁ . . .
For example, if Dn is shared by two input/output control devices C ₀ and C ₁ , and these input/output control devices are shared by host systems S ₀ and S ₁ equipped with host computers, the input/output control device C There is a method that has a shared memory M that can be accessed from both _C0 and _C1 , and performs exclusive control based on the recorded contents of this memory.

In such a shared control method, a system ID (Identification), which is information for identifying the upper system, is used for each channel path of each upper system.
is set to channel ports A and B of input/output control devices _C0 and _C1 by the command "Set System ID" and is held for each channel route of the input/output control devices. In other words, the input/output controller
The ID of system S ₀ is set to channel port A of C ₀ and channel port A of input/output controller C ₁ , and on the other hand, channel port B of input/output controller C ₀ and channel port of input/output controller C ₁ . The ID of system _S1 is set in B.

For example, when a reserve command for input/output device D ₀ is given to input/output control device C ₀ from system S ₀ , the system ID held in channel port A is transferred to input/output device D ₀ on shared memory M.
Write to the address assigned to . FIG. 2 shows a state in which the system ID has been written to the address assigned to the input/output device _D0 on the shared memory M.

When input/output device D ₀ is reserved by system S ₀ , input/output device D ₀ is reserved by system S ₁ .
When an input/output command is given to channel port B of input/output control device C ₀ , the system ID held in that channel port and the shared memory M corresponding to input/output device D ₀ that made the input/output request are Compare with the system ID written in the address. In this case, since these system IDs do not match, the input/output device D ₀ is deemed unusable and the input/output command is rejected. This exclusive control is performed not only between systems as described above, but also between channel routes (between A and B).
But it is done.

In the conventional shared control method that performs such exclusive control, the shared memory M is connected to the input/output control devices _C0 and
In order to share it with _C1 , it is necessary to operate the shared memory M even if any input/output control device is in a power supply state. For this reason, the power supply system in _the conventional shared control system, as _shown in _{FIG .} , must be connected to the shared memory M via a shared power supply line 3 through reverse current prevention diodes 1 and 2, respectively.
As described above, since power must be supplied to the shared memory from two power supply devices, the power supply system becomes complicated.

C. Object and Configuration of the Invention An object of the invention is to provide a shared control system that can simplify the power supply system.

Therefore, the present invention provides a plurality of input/output control devices shared by a plurality of upper channels, a plurality of input/output devices shared by these input/output control devices,
The shared control method includes a shared memory that can be accessed from each of the plurality of input/output control devices, and performs exclusive control based on the recorded contents of the shared memory, the shared memory including the power supply system being Each of the input/output control devices is provided with an internal memory and a detection circuit for detecting the power supply state of the other input/output control device, and the input/output control device is connected to one of the input/output control devices from the upper channel. When an input/output request is received, the shared memory is used if other input/output control devices are in the power supply state based on the information from the detection circuit, and the other input/output control devices are in the power supply state. If the input/output control device does not have the input/output request, exclusive control is performed using only the internal memory of the input/output control device that received the input/output request.

D. Embodiments of the Invention In the following embodiments, for the sake of simplicity, a system including two input/output control devices will be described as an example.

FIG. 4 is a block diagram particularly for explaining the power supply system in one embodiment of the present invention.

The shared memory M, including the power supply system, is assigned to the input/output control device _C0 . This input/output control device C ₀
And the shared memory M is supplied with power from the power supply P ₀ via the power supply line L ₀ . On the other hand, power is supplied to the input/output control device _C1 from the power supply device _P1 via the power supply line _L1 . Each input/output control device has internal memories M ₀ , M ₁ and voltage detection circuits V ₀ ,
V ₁ respectively. The voltage detection circuit V ₀ is connected to the power supply line L ₁ , and the voltage detection circuit V ₁
are connected to the power supply line _L0 , and each detects the power supply state.

In the above power supply system, the power supply
When P ₀ is on, shared memory M and internal memory M ₀ are available, and when power supply P ₁ is on, internal memory M ₁ is available. Furthermore, when both power supplies P ₀ and P ₁ are on, shared memory M and internal memories M ₀ and M ₁ are available for use.

Therefore, in the present invention, during exclusive control,
If only the input/output control device to which the input/output command is given is in the power supply state, exclusive control is performed using its internal memory, and the input/output control device to which the input/output command is given and other input/output control devices are When power is being supplied, exclusive control is performed using shared memory.

FIG. 5 is a block diagram showing an embodiment of the shared control system having the power supply system described in FIG. 4.

For example, host systems S ₀ and S ₁ consisting of host computers share input/output control devices C ₀ and C ₁ , and these input/output control devices are commonly connected input/output devices D ₀ , D ₁ , etc. Assume that the Dn is shared. Channel port A of input/output controller C ₀ and channel port A of input/output controller C ₁ are connected to each channel of system S ₀ to form each channel route. Further, the channel port B of the input/output control device C ₀ and the channel port B of the input/output control device C ₁ are connected to each channel of the system S ₁ to form each channel route.

Each input/output control device includes an internal memory M ₀ and M ₁ , respectively, as explained in FIG. 4, and the shared memory M is assigned to the input/output control device C ₀ . These internal memories M ₀ , M ₁ and shared memory M are as shown in FIG.
Each of the input/output devices D ₀ , D ₁ , . . . has an address corresponding to Dn. The shared memory M also connects to input/output controllers C0 _{and C0} through memory read/write interfaces (not shown), respectively.
Readable and writable from _C1 .

Next, the operation of this embodiment will be explained. Each system
A system ID for identifying the system for each upper channel path of S ₀ and S ₁ is set for each channel route using the command "set system ID". That is, ID "X" of system S 0 is set to channel port A of input/output controller C ₀ and channel port A of input/output controller C ₁ , and on the other hand, ID "X" of system S ₀ is set to channel port A of input/output controller C ₀ and channel port A of input/output controller C 1. The ID "Y" of the system _S1 is set to the channel port B of the input/output control device _C1 .

For example, when a reserve command for input/output device D ₀ is given from system S ₀ to channel port A of input/output controller C ₀ , the input/output controller
The system ID "X" set in channel port A of _C0 is written to the address assigned to input/output device _D0 of internal memory _M0 and shared memory M. Further, from the system S ₁ to the channel port B of the input/output control device C ₀ , the input/output device D ₁
When a reserve command is given to the input/output controller _C0 , the system ID “Y” held in the channel port B of the input/output controller C0 is assigned to the address assigned to the input/output device _D1 of the internal memory _M1 and the shared memory M. written to. If no reserve command is given to the input/output control device C ₁ and its internal memory M ₁ is non-reserved, then the shared memory M, internal memory M ₀ , internal memory
The recorded contents of _M1 are shown in FIGS. 6a, b, and c, respectively. In the figure, non-reserved addresses are shown as blank spaces, but for example, a special ID indicating that they are non-reserved (for example, all 0s) can be written therein.

Exclusive control when an input/output command is given in such a state will be explained below. 7th
The figure is a flowchart showing the operation of exclusive control. For example, assume that an input/output command for input/output device D ₀ is sent from the upper channel of system S ₀ to channel port A of input/output control device C ₀ . Further, at this time, it is assumed that the power supply device P ₁ on the side of the input/output control device C ₁ is turned off, and the input/output control device C ₁ is in a state where power is not supplied. The voltage detection circuit V ₀ on the input/output control device C ₀ side detects this and instructs to use the internal memory M ₀ .
The input/output control device _C0 reads the contents of the address specified by the input/output command (assigned to the input/output device _D1 ) from the internal memory Mo, and determines whether or not it is reserved. in this case,
The system ID “Y” is reserved at that address, and it is determined whether or not this system ID “Y” is the same as the system ID set in the channel route currently being executed, that is, the channel port. Ru. In this case, the channel port being executed is channel port A of the input/output control device Co, and the set system ID is "X", so it is determined that there is a mismatch. As a result, this input/output command will be rejected.

The above has explained an example of exclusive control between channel routes, but as shown in the flowchart in Figure 7, if the specified address is not reserved, the input/output command will be executed, and if the specified address is not reserved, the input/output command will be executed. If the ID matches the system ID set for the channel root being executed, the input/output command will be executed. The operation shown in FIG. 7 may be considered to be performed by a microprogram, for example.

To help understand the operation of this embodiment, the operation of exclusive control between systems will be explained. The recorded contents of shared memory M, internal memories _M0 and _M1 are the sixth
In the state shown in the figure, it is assumed that an input/output command for input/output device D ₀ is transmitted from the upper channel of system S ₁ to channel port B of input/output control device C ₁ . Also, at this time, the power supply device P ₀ on the input/output control device C ₀ side is turned on.
It is assumed that power is being supplied to the input/output control device _C0 . The voltage detection circuit _V1 on the input/output control device _C1 side detects this and instructs to use the shared memory M. The input/output controller _C1 is
The contents of the address specified by the input/output command (assigned to input/output device _D0 ) are read from the shared memory M, and it is determined whether or not it is reserved. In this case, the address has a system
ID “X” is reserved and this system ID
“X” is the currently running channel root, i.e. the system set to the channel port.
It is determined whether it is the same as the ID. in this case,
Since the channel port in execution is channel port B of the input/output control device _C1 , and the set system ID is "Y", it is determined that there is a mismatch. As a result, this input/output command will be rejected.

That is, according to the embodiment, the input/output control device
When power is supplied to both C ₀ and input/output control device C ₁ , exclusive control is performed based on the contents of shared memory M. When the contents of the shared memory M are updated, the internal memory M0 or _M0 of the side belonging to the access route at that time is updated.
Reflect the updated content in _M1 . Furthermore, when power is not supplied to the input/output control device C ₀ or C ₁ on one side, the input/output control device C ₁ or C ₀ on the other side performs exclusive control over at least the input/output control devices. Since there is no need to take this into account, exclusive control is performed using its own internal memory without using the shared memory M.

E Effects of the Invention According to the shared control method of the present invention, the shared memory is assigned to a certain input/output control device, and the power supply to the shared memory is performed by the power supply to this input/output control device, so the power supply The supply system becomes simple.
In order to adopt such a power supply system, each input/output control device must be equipped with an internal memory and voltage detection circuit, but since these components are inexpensive, the overall control system costs less than conventional systems. It has the advantage of being inexpensive.

[Brief explanation of drawings]

Figure 1 is a block diagram of the conventional shared control system, Figure 2 is a diagram showing the recorded contents of the shared memory, Figure 3 is a diagram showing the power supply system of the conventional shared control system, and Figure 4 is a diagram showing the power supply system of the conventional shared control system.
The figure shows the power supply system of the shared control method of the present invention.
FIG. 5 is a block diagram of an embodiment of the present invention, FIG. 6 is a diagram showing recorded contents of the shared memory and internal memory, and FIG. 7 is a diagram showing a flowchart of exclusive control operation. In the figure, S ₀ and S ₁ are systems, A and B are channel ports, C ₀ and C ₁ are input/output control devices, M is shared memory, M ₀ and M ₁ are internal memories, and D ₀ , D ₁ ...Dn indicates an input/output device, V ₀ and V ₁ indicate a voltage detection circuit, P ₀ and P ₁ indicate a power supply device, and L ₀ and L ₁ indicate a power supply line, respectively.

Claims (1)

[Claims] 1 A plurality of input/output control devices shared by a plurality of upper channels, a plurality of input/output devices shared by these input/output control devices, and a shared memory accessible from each of the plurality of input/output control devices. The shared control method performs exclusive control based on the recorded contents of the shared memory, wherein the shared memory is assigned to any of the input/output control devices including the power supply system, and the shared memory is controlled by the input/output control device. Each is equipped with an internal memory and a detection circuit that detects the power supply status of other input/output control devices.
When an input/output request is made to a certain input/output control device from an upper channel, based on information from the detection circuit, if the other input/output control device is in the power supply state, the shared memory is used, and the other input/output control device uses the shared memory. A shared control method characterized in that when the input/output control device is not in a power supply state, exclusive control is performed using only the internal memory of the input/output control device that has received the input/output request.