JPH0153514B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a bipolar transistor in which elements are separated by a thick oxide film.

Generally, an integrated circuit has a plurality of circuit elements formed on a single semiconductor substrate so as to be electrically insulated and separated from each other. As this isolation method, a method of forming an isolation oxide film has been widely used in recent years because it enables high-speed integration and reduction of various parasitic capacitances.

Figure 1 shows a conventional integrated circuit device (IC) like this.
Figure 2 shows a plan view of an npn transistor used in the 1990s, and a cross-sectional view of the device.

The n and n ⁺ layers 1 as contact layers and the P diffusion layer 2 as a base layer are formed in an island-like region on the main surface of a P-type silicon substrate surrounded by a thick oxide film 100 formed for isolation. Further, an n ⁺ diffusion layer 3 as an emitter layer is formed in this order, and an electrode wiring 7 made of Al or the like is formed on the element surface via a base contact 4, an emitter contact 5, and a collector contact 6. It is connected. Here, the distance D ₁ between the emitter diffusion layer 3 and the oxide film 100 in the direction of the extension line connecting the center of the base contact 4 and the center of the emitter contact 5,
Also, the distance D ₂ between the emitter diffusion layer 3 and the oxide film 100 in the direction perpendicular to the above (see FIG. 1) influences the junction yield of the transistor. The stress caused by a thick insulating film like the isolation oxide film 100 is large as described in Applied Physics Vol. 39 (1970) P551; Yasuo Nakai and Masaaki Watanabe "Interfacial Stress of Semiconductor-Insulating Film", and this is the cause. As shown in Figure 3,
When 500 transistors are connected in parallel, the yield of transistor junctions, which is considered good if there is no leakage at the junction, decreases. However, the stress is 100% of the oxide film
It is concentrated at the interface between the P diffusion layer 2 and the P diffusion layer 2, and the junction yield improves when the emitter region 3 (P-n ⁺ junction) is slightly separated from the oxide film 100. Here, the stress at the corner of the silicon island (indicated by A in FIG. 1) is maximum. In order to improve the bonding yield, D ₁ and D ₂ can be increased, but on the other hand, the base area 1 increases, resulting in a decrease in frequency characteristics due to an increase in capacitance and a decrease in integration density due to an increase in area. .

Therefore, the present invention has been made with the object of improving the transistor junction yield without significantly increasing the base area.

As mentioned above, stress is concentrated at the corners, so if D ₁ >10 μm is set to reduce the influence of the corners, the stress will be reduced only from the sides as shown in FIG. 3, and the bonding yield will improve.

Therefore, in a transistor in which the collector contact 6, the base contact 4, and the emitter contact 5 are arranged in this order in a straight line, D ₁ = D ₂ , which has been generally used until now, becomes as shown in FIG. to D ₁ > D ₂ (D ₂ should be the same size as before)
By doing so, we were able to reduce the influence of corner stress and improve bonding yield.

Here, the ratio of D ₁ /D ₂ varies depending on the use of the transistor, and the leakage current level may be slightly higher for large current operation, but for devices that require high-speed operation, D should be as low as possible. ₁ /D ₂ is 1
It should be close to 1.2, which improves the transistor junction yield without significantly increasing the base area. On the other hand, for low current operation with a low leakage current level and severe conditions, D ₁ /D ₂ should be as large as possible and limited to about 2.0 in order to improve the transistor junction yield without significantly increasing the base area.

Generally, the ratio of D ₁ /D ₂ is about 1.5, which has a wide range of use.

Another application of the present invention is an integrated injection logic circuit (IIL) in which the inactive region is formed of a thick oxide film.
I ² L is a low current operation and leakage current is severely limited.

In FIG. 5, the collector layer 20 corresponds to the emitter diffusion layer in the above example, and the junction yield here is
Affects IC yield. here as before
It is also possible to simply increase the ratio of D ₁ /D ₂ to improve the yield. However, in order to prevent the negative effect of an increase in the base area, as shown in FIG.
It is desirable to increase the ratio of D ₁ /D ₂ because it has advantages such as increased injector efficiency and reduced effective base resistance, and can also improve yield.

I mentioned above about npn transistors, but pnp
Of course, it can be applied to transistors.

According to the present invention, in the distance between the emitter diffusion (collector diffusion in I ² L) region and the isolation oxide film,
By setting the ratio of D ₁ /D ₂ to 1.2 to 2.0, it is possible to reduce stress from corners and improve transistor junction yield without significantly increasing the base area.

Furthermore, in I ² L, the above conditions can be satisfied without increasing the base area by forming injectors on both sides.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a conventional transistor, FIG. 2 is a cross-sectional view of FIG. 1, FIG. 3 is a diagram showing the relationship between distance D ₂ and transistor junction yield, and FIG. A plan view showing an embodiment in which the present invention is applied to a transistor, and FIGS. 5a and 5b are a plan view and a sectional view showing an embodiment in which the present invention is applied to an I ² L. DESCRIPTION OF SYMBOLS 1... Collector layer, 2... Base layer, 3... Emitter layer, 20... I ² L collector layer, 100...
...Separation oxide film.

Claims (1)

[Claims] 1. A first region of a first conductivity type formed on the main surface of a semiconductor substrate and surrounded by an oxide film, a second region of a second conductivity type formed within this first region, and a second region of a second conductivity type formed within this first region; a third region of the first conductivity type formed within the second region;
Contacts are formed in the second and third regions and are aligned with each other, and the distance D ₁ in the linear direction between the oxide film and the third region is The distance D ₂ between the linear direction and the perpendicular direction is D ₂ ≦6μm and 1.2≦
A semiconductor integrated circuit device characterized in that D ₁ /D ₂ ≦2.0. 2. The method according to claim 1, wherein the first region includes a fourth region of the second conductivity type separated from the second region between the second region and the oxide film. Semiconductor integrated circuit device.