JPH0454983B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device in which I ² L and a linear circuit consisting of a normal bipolar circuit coexist.

[Technical background of the invention and its problems]

I ² L consists of an inverter consisting of a so-called reverse structure vertical transistor in which the emitter and collector are arranged in the opposite way from a normal bipolar transistor, and a lateral transistor whose collector is the base of this inverter and which is complementary to the vertical transistor. It is a logic element having an injector. This I ² L is attracting attention because it can operate at high speed with low power consumption and has a structure suitable for high integration, and it is also known that it can be easily integrated on the same chip at the same time as other bipolar transistors. ing.

By the way, when forming only I ² L on the chip,
If element characteristics are not taken into consideration, element isolation between I ² L is unnecessary, and the structure shown in FIG. 1 is used, for example.

1 in Figure 1 is an N ⁺ type silicon substrate, and this
An emitter region 2 of an NPN vertical transistor is formed on an N ⁺ type silicon substrate 1 and is made of an N-type epitaxial layer and also serves as a base region of a PNP lateral transistor. This emitter region 2 is common to all circuits. This emitter area 2 contains an injector area 3 and a PNP.
Base regions 4 of NPN transistors, which also serve as collector regions of the transistors, are formed respectively.
In this base region 4, collector regions 5 ₁ and 5 ₂ of NPN transistors are formed. An injector electrode is formed on the injector region 3, a base electrode is formed on the base region 4 and serves as an input, and a collector electrode is formed on the collector regions 5 ₁ and 5 ₂ as an output. The emitter region 2, injector region 3, base region 4, and collector regions 5 ₁ and 5 ₂ constitute the main part of I ² L. Furthermore, in the emitter region 2,
N ⁺ type high concentration impurity region 6 surrounding the main part of I ² L
is formed.

The above-mentioned I ² L has the following drawbacks. That is, in order to operate the NPN vertical transistor in the reverse direction, the N ⁺ type high concentration impurity region 6 is used to reduce the base current of the NPN transistor and increase the current amplification factor. is difficult. Furthermore, since fractional carriers are likely to accumulate in the emitter region 2, this is an obstacle to further speeding up.

In order to eliminate the above drawbacks, a structure is known in which the I ² L gate is surrounded by an oxide film 7 instead of the N ⁺ type high concentration impurity region 6 in FIG. 1, as shown in FIG. 2. .

With this structure, current does not leak in the lateral direction of the I ² L gate, sufficient electrical isolation is achieved between adjacent gates, and at the same time the base current is reduced, increasing the upward current amplification factor. be able to. Also, the emitter of the NPN transistor
At the same time as the base capacitance is reduced, the accumulation of minority carriers on the sides of the base region 4 is reduced, so that the switching speed becomes faster.

By the way, the structure shown in FIGS. 1 and 2 has the disadvantage that the range of application of the circuit structure is extremely limited because a linear circuit consisting of ordinary bipolar transistors cannot be formed at the same time.

That is, in order to form I ² L and a linear circuit on the same chip, I ² L consisting of an NPN vertical transistor and a PNP lateral transistor is required.
To explain this, some parts of the surface of the P-type silicon substrate
After forming an N ⁺ type buried region and growing an N type epitaxial layer, a P ⁺ type isolation region is formed to align the N type epitaxial layer linearly with the island region where ^I2L is formed. It is necessary to separate it into island areas where circuits are formed.

FIG. 3 shows an island region where I ² L is formed in a semiconductor device having such a structure.

Reference numeral 11 in FIG. 3 is a P-type silicon substrate, and an N ⁺ type buried region 12 is selectively formed in this P-type silicon substrate 11. On the substrate 11 on which the N ⁺ type buried region 12 is formed, there are an emitter region 13 and an injector region 1 of an NPN transistor made of an N type epitaxial layer, as shown in FIG.
4. A base region 15 and collector regions 16 ₁ and 16 ₂ of a PNP transistor are formed, and an oxide film 17 surrounds these. The linear circuit is formed in an island region separate from the island region shown in FIG. 3 and separated by a P ⁺ type isolation region (not shown) that reaches the substrate 11.

However, as shown in Figure 3, it is a composite integrated circuit that integrates I ² L and linear circuits on the same chip.
In a semiconductor device having a structure in which the I ² L gate is surrounded by a dielectric material, the following new disadvantages arise in terms of the I ² L design margin.

In I ² L that coexists with the linear circuit described above,
The emitter potential is not biased by the metal wiring, but by the N ⁺ type buried region 12. However, the sheet resistance value of the N ⁺ type buried region 12 is usually relatively high, 10 to 20Ω/□.
When I ² L gates are integrated on a large scale, the emitter current of each gate causes the N ⁺ type buried region 12
A potential gradient occurs. For this reason, a difference occurs in the emitter potential between each gate, and an equal injector current is not injected into each gate, resulting in a disadvantage that malfunctions are likely to occur. If an attempt is made to solve these drawbacks by increasing the impurity concentration of the N ⁺ type buried region 12 to lower the resistance, the defect density of the N type epitaxial layer formed on this region will increase, and the I ² This is not an effective solution for reducing the yield of L gates.

As mentioned above, the phenomenon in which the emitter potential is mixed is more or less an unavoidable problem when integrating I ² L gates, but as shown in Figure 3,
This is more noticeable when the I ² L gate is surrounded by a dielectric.

On the other hand, even in a semiconductor device in which I ² L and linear circuits coexist, the I ² L gate is surrounded by an N ⁺ type high concentration impurity region as shown in Fig. 1, instead of a dielectric as shown in Fig. In the case of biasing the emitter potential, since the sheet resistance of the N ⁺ -type high concentration impurity region is usually as small as several Ω/□ or less, it is difficult for the emitter potential to be biased.

However, with a structure in which the I ² L gate is surrounded by an N ⁺ type high concentration impurity region, it is difficult to increase the current amplification factor as described in the explanation of Fig. 1, and minority carriers are generated in the emitter region. However, this does not solve the problem of easily accumulating data, which becomes an impediment to speeding up. Furthermore, the area of the isolation region between the I ² L gates increases, and the degree of integration of I ² L decreases.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device that can inject an equal injector current to each gate of ^I2L that coexists with a linear circuit, and can achieve high performance. It is something to do.

[Summary of the invention]

A semiconductor device of the present invention includes a semiconductor substrate of a first conductivity type, a buried region of a second conductivity type selectively formed in the semiconductor substrate, and a second conductivity type buried region formed electrically isolated on the substrate. In a semiconductor device comprising a plurality of island-shaped semiconductor layers having conductivity types, and a plurality of I ² L gates and linear circuits respectively formed in different island-shaped semiconductor layers, at least one of the I ² L gates is provided. The device is characterized in that it is surrounded by a dielectric material and a second conductivity type high concentration impurity region having a lower sheet resistance than the electrically buried region is formed under the dielectric material.

In the above-described semiconductor device, the emitter potential of the I ² L vertical transistor is biased by the second conductivity type high concentration impurity region, but since this region has a low resistance, potential gradients are unlikely to occur. Therefore, a difference in emitter potential between each gate is unlikely to occur, and an equal injector current is injected into each gate.

In the present invention, it is desirable that the sheet resistance of the second conductivity type high concentration impurity region is 10Ω/□ or less. This means that when the sheet resistance exceeds 10Ω/□,
This is no different from the case where the layer that substantially biases the emitter potential is only the buried region of the second conductivity type.
This is because the emitter potential difference increases, making malfunctions more likely to occur. In order to make the effects of the present invention effective, the sheet resistance of the second conductivity type high concentration impurity region needs to be smaller than the sheet resistance of the second conductivity type buried region.

[Embodiments of the invention]

Examples of the present invention will be described below along with the manufacturing method shown in FIGS. 4a to 4c.

First, Sb was selectively diffused into a P-type silicon substrate 21 to form an N ⁺ type buried region 22 having a sheet resistance of 10 to 20 Ω/□. Next, an N-type epitaxial layer (PNP) with a thickness of 2 to 3 μm and a specific resistance of 1 to 2 Ωcm is
Also serves as the base region of the lateral transistor
Emitter region of NPN vertical transistor)
23 was formed. Subsequently, the P-type impurity is selectively diffused to reach the substrate 21 (not shown).
A P ⁺ -type isolation region was formed, and the N-type epitaxial layer (emitter region) 23 was separated into an island region where I ² L was formed and an island region where a linear circuit was formed. Next, phosphorus or arsenic is selectively diffused into the I ² L gate isolation region of the island region where I ² L is formed, and N ⁺ type high concentration impurity with a depth of 2 to 3 μm and a sheet resistance of 5 to 6 Ω/□ is applied. A region 24 was formed. At the same time, a collector contact region of a vertical NPN transistor was formed in the island region where a linear circuit (not shown) is to be formed (as shown in FIG. 4a).

Next, according to a selective oxidation method, an oxide film 25 having a thickness of 1 to 1.5 μm was formed in the I ² L gate isolation region (as shown in FIG. 4B).

Next, P-type impurities were selectively diffused to form an injector region 26 and a base region 27 of an NPN transistor which also serves as an emitter region of the PNP transistor. At the same time, a P-type base region was also formed in the region where the linear circuit was to be formed. Subsequently, N-type impurities were selectively diffused to form collector regions 28 ₁ and 28 ₂ of NPN transistors in the base region 27. At the same time, an N ⁺ emitter region was also formed in the region where the linear circuit would be formed. Next, CVD-SiO ₂ film 29 is applied to the entire surface.
After depositing contactor holes 30... Subsequently, an Al film was deposited on the entire surface and then patterned to form an injector electrode 31, a base electrode 32, and collector electrodes 33 ₁ and 33 ₂ .
At the same time, each electrode of the linear circuit was also formed. Through the above steps, a semiconductor device in which I ² L and a linear circuit coexist was manufactured (as shown in FIG. 4c).

The above semiconductor device has an oxide film 25 for the I ² L gate.
The structure is such that an N ⁺ -type high concentration impurity region 24 is formed under this oxide film 25 .

According to the above semiconductor device, the potential of the emitter region 23 of the NPN transistor is biased by the N ⁺ type high concentration impurity region 24;
Since the sheet resistance of this N ⁺ -type high concentration impurity region 24 is as small as 5 to 6 Ω/□, potential drift is unlikely to occur due to the emitter current of each I ² L gate. Therefore, a difference in potential between the emitter regions 23 of each gate is unlikely to occur, an equal injector current is injected into each gate, and good operating characteristics are exhibited. Also, I ² L
Of course, since the gate is surrounded by the oxide film 25, the current amplification factor is improved and the speed is increased.

It should be noted that forming the N ⁺ -type high concentration impurity regions 24 so as to surround each I ² L gate is desirable in terms of biasing the emitter potential, but is not desirable in terms of high integration. Therefore, it may be formed to surround a plurality of I ² L gates in consideration of device characteristics and high integration. For example, if the N ⁺ type high concentration impurity region 24 is formed under the wiring region that occupies most of the I ² L region, the effects of the present invention can be sufficiently obtained without impairing the high degree of integration.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a semiconductor device that can inject an equal injector current into each gate of I ² L that coexists with a linear circuit and can achieve high performance.

[Brief explanation of the drawing]

Figures 1 and 2 are cross-sectional views showing conventional I ² L;
FIG. 3 is a cross-sectional view of a conventional semiconductor device in which I ² L and a linear circuit coexist, ^and FIGS. FIG. 3 is a cross-sectional view showing the manufacturing process. 21...P type silicon substrate, 22...N ⁺ type buried region, 23...N type epitaxial layer (emitter region), 24...N ⁺ type high concentration impurity region, 2
5... Oxide film, 26... Injector region, 27
... Base region, 28 ₁ , 28 ₂ ... Collector region, 29 ... CVD-SiO ₂ film, 30 ... Contact hole, 31 ... Injector electrode, 32 ...
Base electrode, 33 ₁ , 33 ₂ ... collector electrode.

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type; a buried region of a second conductivity type selectively formed in the semiconductor substrate;
A plurality of island-shaped semiconductor layers having a second conductivity type formed electrically separately on the substrate, and a plurality of I ² L gates and linear circuits respectively formed in different island-shaped semiconductor layers. In the semiconductor device,
A semiconductor device characterized in that at least one of the I ² L gates is surrounded by a dielectric material, and a second conductivity type high concentration impurity region having a lower sheet resistance than the buried region is formed under the dielectric material. 2. The semiconductor device according to claim 1, wherein the second conductivity type high concentration impurity region has a sheet resistance of 10Ω/□ or less. 3. The semiconductor device according to claim 1 or 2, wherein the second conductivity type high concentration impurity region is an N type high concentration impurity region.