JPH0154673B2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a pointer type electronic timepiece.

[Conventional technology]

Conventionally, pointer type electronic watches have been constructed as shown in FIG. 1 is a crystal resonator, 2 is an oscillation circuit, 3 is a frequency dividing circuit, 4 is a drive pulse forming circuit, 5 and 6 are step motor drive buffers, and 7 is a step motor.

Details of portions 4 to 7 in FIG. 1 are shown in FIG. 2.
8 is a data signal, 9 is a clock signal, 11 is a delay type flip-flop serving as a holding circuit, 12 is an inverter, 13 and 14 are NAND gates, 15,
16 is an inverter, 17 and 18 are drive buffers,
19 is a step motor. 11 flip-flops, 12 inverters, 13 and 14
A drive pulse for the step motor is output from a drive pulse forming circuit consisting of a NAND gate and 15 and 16 inverters. In flip-flop No. 11, a data signal is written while CL is at H level, so that D=Q. is an output that is complementary to Q. While CL is at level, it is in a hold state, and Q has a function that does not change.

A time chart of the circuit shown in FIG. 2 is shown in FIG. NAND gates 13 and 14 receive the data signal 8 and the output of the flip-flop 11, and output a driving pulse when both input signals match the H level. When the phases of the input signals of the NAND gates 13 and 14 match, the phase of the data signal D changes, and the period of the hold state from when the flip-flop 11 writes this phase-changed D until the phase of the output Q changes. be. Therefore, NAND
Drive pulses having a pulse width of 1/2 the period of the clock signal appear alternately from the gates 13 and 14.

[Problem that the invention seeks to solve]

The data signal 8 and clock signal 9 in FIG. 2 are respectively supplied from the frequency divider circuit 3 in FIG. 1, but since the state of the frequency divider circuit is not determined when the power is turned on, The potential level of CL cannot be determined either. Further, the potential level of the signal held by flip-flop 11 is also undefined, and the potential levels of Q and Q cannot be determined. Therefore, when the power is turned on, D is at H level,
If Q goes to L level and goes to H level, the inputs of NAND gate 14 both go to H level, and if D goes to L level and Q goes to H level, then the input to NAND gate 13 goes to Both become H level, L level is output from one of the NAND gates, and the motor drive current continues to flow from 17 to 18 or from 18 to 17. This phenomenon is canceled when the crystal oscillator starts oscillating, CL is inverted from L level to H level, a data signal is written to flip-flop 11, Q is inverted, and D=Q. . That is, as shown in FIG. 3, when the flip-flop 11 is in the write state, D=Q, and the inputs of the NAND gates 13 and 14 are out of phase, so that both outputs become H level. However, once this phenomenon occurs, the motor drive current flows, causing the voltage across the battery to drop due to the internal resistance of the battery. If this falls below the oscillation start voltage, oscillation cannot be started forever, so the potential level of CL remains at the L level and does not change, and the flip-flop 11 does not enter the write state, so the motor drive current continues to flow. , the battery will discharge in a short period of time.
This would result in extremely serious defects.

Whether or not this phenomenon occurs is determined by the relationship between the time constants of the drive pulse forming circuit of the integrated circuit for electronic watches, but it is especially dangerous for integrated circuits that suppress the gain of the oscillation circuit in order to reduce current consumption. . In the circuits of conventional pointer-type electronic watches, no measures have been taken to prevent such phenomena.

The present invention eliminates the above drawbacks and aims to initialize the potential level of the motor drive pulse forming circuit when power is turned on.

[Means for solving problems]

The pointer type electronic timepiece of the present invention includes a power supply battery, an oscillation circuit, a frequency dividing circuit that divides the output of the oscillation circuit to form a clock signal and a data signal, and a clock signal that outputs the data when the clock signal is at a predetermined potential level. A holding circuit that writes and holds a signal, a first gate circuit that receives a first output signal of the holding circuit and an inverted signal of the data signal to detect phase matching, and the first output signal have a complementary relationship. a second gate circuit that inputs the second output signal of the data signal and the data signal to detect a phase match; A pointer type electronic timepiece comprising a buffer circuit which receives a drive pulse output from the first or second gate circuit that detects phase matching of input signals and supplies a drive current between two terminals of a step motor. an initial stage that includes a time constant circuit consisting of a resistor and a capacitor, and fixes the clock signal to the holding circuit at the predetermined potential level for a predetermined period based on the time constant of the time constant circuit from the time when the battery is powered on; The device is characterized in that it comprises a setting means, and the holding circuit writes the data signal during the predetermined period so that the input signals of the first and second gate circuits are out of phase.

〔Example〕

FIG. 4 shows an embodiment of the present invention. Figure 4 is the second
A time constant circuit consisting of 20 resistors and 21 capacitors, which are examples of a time constant circuit, and an initial setting circuit consisting of 22 NAND gates are added to the circuit configuration shown in the figure. In a time constant circuit, when the power is turned on, the potential at the connection point between the resistor and capacitor is
Transition occurs from V _SS =L level to _VDD =H level.
This transition period is determined based on the time constants of the resistor and capacitor. During a predetermined period based on the CR time constant after the power is turned on, one input of the NAND gate 22 is at the L level, so the output is at the H level regardless of the presence or absence of the clock signal 9, and the CL supplied to the flip-flop 11 is The potential level of is fixed at H level for a predetermined time.

This flip-flop 11 is in a data signal write state when CL is at H level, and outputs the written data signal as it is. Therefore, during the predetermined period, the input data signal becomes the Q output as it is, and D=Q. That is, when the power is turned on, the flip-flop 11 is not in a hold state, and the write output state is maintained, so that the potential level inside the flip-flop is determined. During this period, D=Q with no phase change delay occurring between the data signal and Q. NAND gate 13,
14 outputs an L level drive pulse when both inputs match the H level. However, when the flip-flop 11 is in the write state and D=Q, one of the inputs of the NAND gates 13 and 14 goes high.
When the output is at the L level, the other one is always at the L level, so the output will not be at the L level. NAND gate 13,
If the output of step motor 14 remains at H level, the outputs of buffers 17 and 18 are both at H level, no current flows to step motor 19, and the battery voltage rapidly drops below the oscillation start voltage. Nothing happens that makes it impossible to start oscillation.

FIG. 6 shows another embodiment of the present invention, which will be described below with reference to FIG. FIG. 6 shows the circuit configuration of FIG. 5 with the addition of a differentiating circuit consisting of 23 to 32 circuit elements and a power-on initial setting circuit. This separate circuit is provided not for driving the motor, but for outputting a rate measurement signal for the electronic timepiece. Electronic watches with a two-hand display (hand movement cycle of 10 to 20 seconds) with a logical adjustment function are often equipped with one to shorten the rate measurement time. In order to initialize the potential level of the drive buffer 18 to H level, it is necessary that both of the two inputs of the NAND gate 29 become H level. For this reason, the CL of 26 flip-flops also has CL of 32.
A NAND gate and differentiating circuits 30 and 31 are added to remove the uncertainty of the clock signal 23 at power-on.

[Effects of the Invention] The initial determination circuit according to the present invention can be applied not only to the embodiments but also to complex output circuits having pulse width control. This is achieved using a simple circuit configuration in which the CL signal of the flip-flop in the final stage of the output circuit is generated by combining the clock signal of the frequency divider circuit and the output of the time constant circuit, so there is no increase in cost due to an increase in the chip size of the integrated circuit. rare. In addition, since initialization can be achieved without resetting the frequency dividing circuit, and without resetting the frequency dividing circuit, there is no need to worry about chattering caused by mechanical vibration of the battery. It can provide an extremely practical circuit. The practical effects of the present invention are significant in that the battery consumption caused by continuous current to the motor, which conventionally had the danger of occurring when the power is turned on, can be prevented by circuit means, and the reliability of the pointer-type electronic timepiece is improved. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the circuit configuration of a conventional pointer type electronic timepiece. FIG. 2 is a circuit diagram of a drive pulse forming circuit for a conventional pointer type electronic timepiece. Third
The figure is a time chart showing the operation of the drive pulse forming circuit of FIG. 2. FIG. 4 is a circuit diagram showing an embodiment according to the present invention. FIG. 5 is a circuit diagram showing another embodiment according to the present invention. DESCRIPTION OF SYMBOLS 1... Crystal resonator, 2... Oscillation circuit, 3... Frequency dividing circuit, 4... Drive signal forming circuit, 5, 6... Step motor drive buffer, 7... Step motor, 8... Data signal, 9...Clock signal, 1
0...Inverter, 11...Delay type flip-flop, 12...Inverter, 13, 14...
NAND gate, 15, 16...Inverter, 1
7, 18...Step motor drive buffer, 19
... Step motor, 20 ... Resistor, 21 ... Capacitor, 22 ... NAND gate, 23 ... Clock signal (separate system), 24 ... Data signal (separate system), 25 ... Inverter, 26 ... Delay Type flip-flop, 27...NOR gate, 2
8...Inverter, 29...NAND gate, 3
0...Resistor, 31...Capacitor, 32...
NAND gate.

Claims (1)

[Claims] 1. A power supply battery, an oscillation circuit, a frequency dividing circuit that divides the output of the oscillation circuit to form a clock signal and a data signal, and a holding device that writes and holds the data signal when the clock signal is at a predetermined potential level. a first circuit that detects phase matching by inputting a first output signal of the holding circuit and an inverted signal of the data signal;
a gate circuit; a second gate circuit that inputs a second output signal having a complementary relationship with the first output signal and the data signal to detect a phase match; and a holding circuit that writes the data signal whose phase has changed. During this period, the input signals of the first or second gate circuit match in phase, and in response to the drive pulse output from the first or second gate circuit that detects this, a drive current is generated between the two terminals of the step motor. The pointer type electronic watch includes a time constant circuit consisting of a resistor and a capacitor, and the pointer type electronic watch includes a time constant circuit consisting of a resistor and a capacitor, and the pointer type electronic watch includes a time constant circuit that supplies power to the holding circuit for a predetermined period based on the time constant of the time constant circuit from the time when the power of the battery is turned on. initial setting means for fixing the clock signal at the predetermined potential level, and during the predetermined period, the holding circuit writes the data signal so that the input signals of the first and second gate circuits are out of phase. A pointer type electronic watch characterized by: