JPH0160966B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvements in automatic gain control circuits suitable for transmission of digital baseband signals over telephone subscriber lines.

[Conventional technology and its problems]

Automatic gain control circuits used in baseband transmission have important roles such as compensating for losses occurring in transmission lines and absorbing time fluctuations in losses due to temperature fluctuations, etc., and are usually required to have the following characteristics. That is, (1) there is a sufficient gain variable range (usually 40~
(50dB required), (2) Transient response speed is sufficiently fast (usually 100ms
(3) The gain does not fluctuate due to changes in the input pulse density, (4) The gain does not fluctuate due to momentary interruption surges, (5) The gain setting does not shift due to various noises, etc.

A conventionally known automatic gain control circuit will be explained. Automatic gain control circuits include peak detection type, power detection type, etc., but since the peak detection type is common in baseband transmission, the peak detection type will be explained here.

FIG. 1 is a circuit diagram of a main part of a conventional automatic gain control circuit using an analog control method. In FIG. 1, 1 is a variable gain amplifier, the gain of which decreases or increases as the control signal d increases or decreases. 2 is a peak level detection circuit, 3 is an error amplifier, and 4 is a reference voltage generation circuit. The peak level detection circuit 2 includes a diode 5, resistors 6 and 7, and a capacitor 8. Figure 2 is × in Figure 1
This is an operation time chart showing input signals or output signals at the points indicated by marks.

In the operation of such a circuit, first, a pulse signal train input signal a whose level has decreased due to loss during passage through a transmission line is input to the variable gain amplifier 1. This input signal a is converted into a control signal d by the variable gain amplifier 1.
It is amplified by the gain determined by , and becomes the output signal b.
The signal level of this output signal b is the voltage c of the capacitor 8.
If it is larger, the capacitor 8 is charged through the diode 5 and the resistor 6, and the voltage c increases. Correspondingly, the output voltage of the error amplifier 3 increases and the gain of the variable gain amplifier 1 decreases. On the other hand, when the signal level of the output signal b is lower than the voltage c, the diode 5 is cut off, and the output signal b of the variable gain amplifier 1 does not affect the state of the peak level detector 2.

In this state, the charge held in the capacitor 8 is discharged through the resistor 7 with a time constant determined by the capacitor 8 and the resistor 7, and the voltage c of the capacitor 8 gradually decreases. As a result, the control signal d of the variable gain amplifier 3 decreases, and the gain of the variable gain amplifier 1 increases.

Thus, the circuit shown in FIG. 1 operates as an automatic gain control circuit. However, when using this as an automatic gain control circuit for baseband transmission, it is necessary to satisfy item (3) of the requirements for the automatic gain control circuit, so the resistance value of the resistor 7 is usually The discharge time constant determined by the capacitance of the capacitor 8 is set to a large value of about 1000 time slots, and is designed so that the detected signal level can be maintained for a long time. At the same time, the charging time constant determined by the resistance value of resistor 6 and the capacity of capacitor 8 is usually set to a small value of about 0.5 to 2 time slots, and when the pulse density decreases, the signal peak level is detected with a small number of input pulses. Design so that it can be done.

However, in this way, the automatic gain control circuit is
If the constants of each part are determined to satisfy the conditions in item (3), the ``transient response speed must be sufficiently fast'' in item (2) above, and the gain should not fluctuate due to momentary interruption surges in item (4) above. ” has the disadvantage that it is difficult to satisfy the condition. That is, since the peak level detection circuit 2 has a long discharge time constant, once it is overcharged for some reason, it takes a very long time to return to the normal state. This state occurs when the peak value holding capacitor 8
This is the case when a relatively high level signal is input when the output signal b is in a discharged state, and a large level is generated in the output signal b, or when a surge input occurs.

FIG. 3 is a circuit configuration diagram of a main part of a conventional automatic gain control circuit using a digital control type. In FIG. 3, numeral 9 denotes a variable gain amplifier whose gain is variable by setting a switch, and the circuit system is normally selected so that the change in gain is logarithmically proportional to the switch control input l. Further, 10 is a voltage comparator. There are examples of using an AD converter in this part, but using an AD converter increases the circuit scale and is not suitable for use in a general automatic gain circuit, so here we will use an example using the voltage comparator 10. shows. In FIG. 3, 4 is a reference voltage generation circuit for the voltage comparator 10, 12, 13
is an AND gate, 14 is a frequency division counter, 15
is an up-down counter. Let the number of stages of the counter 14 be "N". Further, the number of stages of the up-down counter 15 is assumed to be "±M". Further, 1 is a clock signal. FIG. 4 is a diagram showing the relationship between the gain control signal l and the gain of the variable gain amplifier 9 shown in FIG. The vertical axis shows the gain in dB, and the horizontal axis shows the switch control input state number of the gain control signal l.

FIG. 5 is an operation time chart showing input signals, output signals, etc. at the points indicated by crosses in FIG. 3.

With such a circuit configuration, when the signal level of the output signal g of the variable gain amplifier 9 becomes equal to or higher than the reference signal level from the reference voltage generation circuit 4, a pulse signal is input to the down side input of the up/down counter 15, and the up/down counter 15 receives the pulse signal. The down counter 15 counts down and the gain of the variable gain amplifier 9 decreases. Furthermore, if the signal level of the output signal g of the variable gain amplifier 9 does not reach the reference signal level from the reference voltage generation circuit 4 for more than N clocks, the counter 14 overflows and a pulse is applied to the up input of the up/down counter 15. is input, the up-down counter 15 counts up, and the gain of the variable gain amplifier 9 increases. With this operation, it operates as an automatic gain control circuit. The operation of this circuit basically exhibits characteristics equivalent to those of the analog-controlled automatic gain control circuit shown in FIG. but,
This circuit has the following advantages due to digitization. In other words, (1) the capacitor for maintaining the peak level, which is indispensable in analog-controlled automatic gain control circuits, is no longer required, making it suitable for IC implementation; (2) analog-controlled automatic gain control circuits require It is difficult to hold the gain, but when using a digital method, it can be easily done by cutting off the control input of the up-down counter. (3) Since the gain is set by switching, accurate It has the advantage of being able to set the gain and widening the gain variable range.

Although the conventional digitally controlled automatic gain control circuit has these advantages, its operating principle is equivalent to that of the analog system, and the first requirement for the automatic gain control circuit, which was a problem in the case of the analog control system, has not been solved. The problem of reconciling the conditions stated in paragraphs (2) and (4) still has unresolved drawbacks.

The present invention improves this point, and aims to provide an automatic gain control circuit that has high-speed convergence, high stability, and is suitable for baseband signal transmission over telephone subscriber lines. .

[Means for solving problems]

The present invention provides a switching type variable gain amplifier with 2 ^N0 gain states (N ₀ is a positive integer), performs control to compare the output of this variable gain amplifier with a reference level, and performs control every time. Then, based on the comparison result, add 2 ^N0 /2 ⁿ = 2 ^N0-n (n = 1 to N ₀ ; n indicates the number of control operations) to the gain state that gave this output (if the output is lower than the reference level) The present invention provides an automatic gain control circuit that sets the gain state to give the output closest to the reference level within the _N0th control by subtracting (if the output is lower than the reference level) or subtracting (if the output is higher than the reference level).

[Effect]

When a variable gain amplifier is started up, the gain of the amplifier is not constant.

The variable gain amplifier at this time is controlled by the control value read from the ROM.

This ROM has a control function whose upper address is the previous control output, and the result of comparing the output level of the variable gain amplifier with the reference level is reset by a flip-flop every control cycle input, and the output value is the lower address. Output value is memorized.

This control output value is determined by the following: n _N = n _N-1 −2 ^N0-N or n _N = n _N-1 +2 N0-N, where the number of times of control is N and N ₀ is the gain setting value of ^{the variable} gain amplifier. Since it is stored, the output level of the variable gain amplifier is controlled by adding or subtracting from the previous control value and performing a binary search. Therefore, it is possible to quickly converge to the reference level.

In addition, when it is detected that it has converged to the reference level, the output of the latch circuit can be fixed,
Even if it is not fixed, there is very little variation within the reference level range.

In addition, this invention is applied to highly stable subscriber lines, and once the gain fluctuation at startup is converged, there is almost no large fluctuation in the input signal thereafter, and the operation quickly follows large level fluctuations in the input signal. There is little need to do so.

〔Example〕

An embodiment of the present invention will be described based on the drawings.

FIG. 6 is a block diagram of essential parts of an embodiment of the present invention. In FIG. 6, numeral 17 is a switching type variable gain amplifier having a finite number of gain states ^2N0 , and its gain is logarithmically proportional to the state of the digital input signal u for gain control. The output of the variable gain amplifier 17 is led to an input level determination circuit 18 and also to a compared input terminal of the voltage comparator 10. A reference voltage generation circuit 4 is connected to a comparison input terminal of the voltage comparator 10.

The output of this voltage comparator 10 is led to the set terminal of a set-reset flip-flop 21 (hereinafter referred to as "flip-flop"). The output of this flip-flop 21 is ROM (Read
Only Me-mory) 22 address input. The read data of this ROM 22 is led to a latch circuit 23. The output of the latch circuit 23 is led to the control terminal of the variable gain amplifier 17 and also to the address terminal of the ROM 22. Further, clock signals are led to the reset terminals of the latch circuit 23 and the flip-flop 21, respectively.

This example shows a case where the gain state of the variable gain amplifier 17 is 2 ⁵ (N ₀ =5), and the switch control signal u from the latch circuit 23 to the variable gain amplifier 17 is It shows the case.

FIG. 7 is an operation time chart showing input signals or output signals at the points indicated by crosses in FIG. 6.

The characteristic operation of the present invention will be explained using such a circuit configuration. Now, the initial gain of the variable gain amplifier 17 is set in the first control. That is, the contents of the latch circuit 23 are n ₁ =2 ^{5 -1} =16. (Figure 7 u). The input signal f is amplified by this variable gain amplifier 17 with an initial gain Gn ₁ to obtain an amplifier output signal g. This output signal g is compared with the reference level p from the reference voltage generation circuit 4 by the voltage comparator 10 (FIG. 7g), and it is detected that the output signal g is smaller than the reference level p. At this time, flip-flop 21 is not set.

Note that when the peak level of the output signal g exceeds the reference level p, the flip-flop 21 is set by the comparison output t, and the output r of the flip-flop 21 becomes logic "1".

The address of the ROM 22 is specified by the output r of the flip-flop 21 and the contents of the latch circuit 23. In this state, the clock signal s is input, and information instructing the next gain state is latched from the ROM 22 to the latch circuit 23.

That is, the ROM 22 and the latch circuit 23 constitute a sequencer, and when the clock signal s is applied, the read content v of the ROM 22 is transferred to the latch circuit 2.
It is latched at 3. At the same time, the flip-flop 21 is reset and the second control is completed.

Here, the address is specified by the output u of the latch circuit 23 and the output r of the flip-flop 21.
The contents of the ROM 22 will be explained. Now, it is assumed that the gain state set in the N-th control is _no . At this time, the output u of the latch circuit 23 is nN _-1 , and if the output signal g at the gain G( _nN-1 ) at this time is greater than the reference level p and the flip-flop 21 is set, the ROM 22 The contents of the specified address are n _N = n _N-1 -2 ^N0-N , and if the output signal g is smaller than the reference level p and the flip-flop 21 is not set,
The contents of the designated address of the ROM 22 are n _N =n _N-1 +2 ^N0-N . That is, the signal r becomes instruction information for adding or subtracting the change from the previous state.

Therefore, in this embodiment, in the second control, the output r of the flip-flop 21 is logic "0" and the output u of the latch circuit 23 is n ₁ =16, so the content read from the ROM 22 is n ₂ =16+2 ^5-2 =16+2 ³ =24.

Similar operations are repeated thereafter. This gain state n ₂
With a gain G(n ₂ ) in the variable gain amplifier 17
Since the output g of has a peak level smaller than the reference level p, the output r of the flip-flop 21 is set to logic "1", and in the third control, n ₃ = 24-2 ^5-3 = 24-4 = 20. The gain control state is changed from the ROM 22 to the latch circuit 23.
is latched to. By performing the control in this manner, in this embodiment, the fifth control quickly converges to the gain G(n ₅ ) (n ₅ =21) where the reference level p is the output signal n.

After this, the output of the ROM 22 is alternately switched by the flip-flop 21 by the clock s, so
The ROM 22 also outputs "21" and "22" alternately. In this case, since the control inputs are alternated, the gain of the variable gain amplifier 17 will also vary, but this is within the reference level, and this level variation can be absorbed by the subsequent circuit.

This operation is shown in the time chart of FIG.

Furthermore, the convergence at _n5 can be detected by the monitoring circuit 25, as will be described later, and the convergence operation can be terminated by cutting off the clock signal and fixing the output of the latch circuit.

The output level determination circuit 18 is a circuit for determining whether the finally determined gain of the variable gain amplifier 17 is appropriate by monitoring the peak level of the output signal g of the variable gain amplifier 17. be. This determination circuit 18 has the purpose of detecting an erroneous gain setting when noise is superimposed on the input signal f during the gain selection operation and an erroneous gain state is set, and is preferably added in practice.

Note that the above example shows an example where N ₀ = 5 and the output signal g converges to the reference level p at the fifth control, but by adding the output signal level monitoring circuit 25, the output signal level is within a certain range. It is preferable that the gain control operation be terminated by monitoring whether the gain has been reached, stopping the clock signal s based on this monitoring output, and fixing the latch contents of the latch circuit 23.

〔Effect of the invention〕

As explained above, the automatic gain control circuit of the present invention adds or subtracts half of the previous control value to the previous state of the amplifier gain depending on the output level. , level fluctuations at startup can be quickly converged to the reference level, gain can be easily maintained, gain selection control is performed by switching, and accurate gain control is possible, and the gain does not fluctuate due to instantaneous power outage surges. Effects can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the main parts of a conventional example using an analog control system. FIG. 2 is an operation time chart showing the input signals or output signals at the points indicated by crosses in FIG. 1. FIG. 3 is a configuration diagram of the main parts of a conventional example using a digital control system. FIG. 4 is an operational characteristic diagram of the variable gain amplifier shown in FIG. 3. FIG. 5 is an operation time chart showing input signals or output signals at the points indicated by crosses in FIG. 3. FIG. 6 is a block diagram of essential parts of an embodiment of the present invention. FIG. 7 is an operation time chart showing the input signals or output signals at the points indicated by the x marks in FIG. 6. Figure 8 is a time chart of the output of the ROM in Figure 6. 1, 9, 17...Variable gain amplifier, 2...Peak level detection circuit, 3...Error voltage generation circuit, 4
...Reference voltage generation circuit, 5...Diode, 6,
7... Resistor, 8... Capacitor, 10... Voltage comparator, 12, 13... AND gate, 14... Counter, 15... Up/down counter, 18...
Output level determination circuit, 21...set reset flip-flop, 22...ROM, 23...latch circuit, 25...monitoring circuit.

Claims (1)

[Scope of Claims] 1. In a gain control circuit comprising a variable gain amplifier 17 whose gain changes according to a digital control input, and a comparator 10 that compares the output signal of this amplifier with a reference level, the output of this comparator a flip-flop 21 which is set by the controller and reset every control cycle; and a memory circuit 2 which uses the output of this flip-flop and the digital control input signal as address inputs.
2, and a latch circuit 23 that latches successive outputs of this storage circuit for one control period and applies them to the digital control input, the storage circuit having a memory represented by the immediately preceding digital control input and the state of the flip-flop. At two addresses in the circuit, when the output of the variable gain amplifier above exceeds the reference level, n _N = n _N-1 −2 ^N0-N when it falls below the reference level, n _N = n _N-1 +2 ^N0-N (However, N indicates the number of times of control, and _N0 is the gain setting value of the variable gain amplifier.) An automatic gain control circuit characterized in that digital control input values are written respectively.