JPH0223103B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an AIS detection circuit that can reliably detect an all "1" AIS signal.

Prior Art and Problems In the PCM multiplex transmission system, demultiplexing is performed on the receiving side. For example, as shown in Figure 1, demultiplexing devices 1 to 3 sequentially separate upper groups into lower groups. be done. In such a configuration, for example, if a failure occurs in the upper group demultiplexer 1, the lower group demultiplexers 2 and 3 become out of synchronization, and as the synchronization continues, the demultiplexers 2 and 3 become out of synchronization. 2 and 3 will output an alarm signal. In this case, an alarm signal is sent from a multiplexer/demultiplexer in a lower group that is not the faulty device, so maintenance to search for the faulty device is not easy.

Therefore, when a failure occurs in the demultiplexer 1, an AIS signal of all "1" is sent to the demultiplexers 2 and 3 of the lower group, and the demultiplexer 2 and 3 of the lower group
3 is generally configured so that by detecting this AIS signal, it is determined that there is a failure in the upper group device, and no alarm signal is sent out even if the synchronization continues. Therefore, it is necessary to detect this AIS signal as quickly as possible, distinguish between a failure in the own device and a failure in the upper group device, and control whether or not to send out an alarm signal.

In order to detect this AIS signal, it is sufficient to detect a signal that is all "1", but depending on the data, it may correspond to all "1", or
The PCM signal is transmitted in a frame structure, and the frame signal has "1" and "0" inserted alternately, but the "0" of this frame signal becomes "1" due to a transmission error etc. Since the signal may be reversed, the AIS signal could not be detected unless it was monitored to see that "1" continued for a considerable period of time.

OBJECT OF THE INVENTION An object of the present invention is to enable an AIS signal to be detected reliably in a relatively short period of time. Examples will be described in detail below.

Embodiment of the Invention FIG. 2 is a block diagram of a main part of an embodiment of the present invention, in which 4 is a conversion circuit that performs bipolar/unipolar conversion and extraction of clock signal b, and 5 is a converted unipolar PCM signal a. 6 is a separation device; 7 is a monitoring circuit that monitors synchronization and outputs an alarm signal when out-of-synchronization continues;
AIS to detect whether PCM signal a is an AIS signal
This is a detection circuit. When this AIS detection circuit 8 detects an all "1" AIS signal sent from the upper group device, it adds the detection signal c to the synchronization circuit 5 and prohibits the sending of an alarm signal to the monitoring circuit 7 in the event of synchronization loss. In addition, all "1" AIS signals are sent to the lower group devices as they are.

FIG. 3 is a block diagram of the aforementioned AIS detection circuit 8, which is composed of a "0" detection section 10, a counter 11, a timer 12, and a determination section 13. P.C.M.
The detection unit 10 detects “0” of the signal a, the counter 11 counts it, and the content of the count is sent to the determination unit 1.
In addition to step 3, it is determined whether the signal is an AIS signal or not. When it is determined to be an AIS signal, the detection signal c
Output.

For example, as shown in Fig. 4, the normal PCM signal is one in which "1" and "0" are inserted alternately as a frame signal in each frame F, and therefore for a period T of at least seven frames. “0”
When counting, even if the data is all "1", three "0" will be included. Also, even if a frame signal "0" is inverted to "1" due to a transmission error, normally all three "0" frame signals will not be inverted to "1", so the AIS signal If not, the count content of the counter 11 will be 2 or more. On the other hand, since the AIS signal is all "1" including bits corresponding to the frame signal, it does not contain "0". Therefore, the count content of the counter 11 becomes 0. Note that "1" may be inverted to "0" due to some kind of error, so the determination unit 13 determines that it is an AIS signal even if the count content of the counter 11 is 1. Therefore, the AIS signal can be detected reliably.

The timer 12 is used to set the count period T of the counter 11, and the count contents for each count period T are added to the determination section 13 to determine whether or not it is an AIS signal.

Note that since the PCM signal has been converted into a unipolar signal, it can also be configured to count "0" by inputting it to the counter 11 via an inverter.

Effects of the Invention As explained above, the present invention detects a "0" signal in which "1" and "0" are inserted alternately in each frame, and is counted by the counter 11, and the counting period T
is set to have a period of at least 7 frames by the timer 12, and the determining unit 13 determines that it is an AIS signal when the count content of the counter 11 is 1 or less. Under normal conditions, the frame signal has "0". Therefore, by counting the "0" signals over a period T of at least seven frames, for example, in the case of all "1" data, one "0" in the frame signal is determined to be "0" due to a bit error. Even if the signal becomes "1", it will include two "0"s, so the count content of the counter 11 will be 2, and the determination unit 13 can determine that it is not an AIS signal.

In addition, in the AIS signal from the upper group side device, all bits corresponding to the frame signal are “1”, so 1
Even if one "0" is included due to a bit error, the count content of the counter 11 will be 1 or less, so the determining section 13 will determine that it is an AIS signal.

Therefore, there is an advantage that the AIS signal can be distinguished from the data and the AIS signal can be detected reliably and at high speed.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a demultiplexing device on the receiving side of multiplexed PCM signals, FIG. 2 is a block diagram of main parts of an embodiment of the present invention, and FIG. 3 is a block diagram of an AIS detection circuit of an embodiment of the present invention. FIG. 4 is an explanatory diagram of a frame signal. 4 is a conversion circuit, 5 is a synchronization circuit, 6 is a separation device,
7 is a monitoring circuit, 8 is an AIS detection circuit, 10 is “0”
In the detection section, 11 is a counter, 12 is a timer, and 13 is a determination section.

Claims (1)

[Claims] 1. An AIS detection circuit that sends all "1" AIS signals to the lower group device when a failure occurs in the upper group device that performs demultiplexing, and detects the AIS signal with the lower group device. ``0'' detects the ``0'' signal of the frame signal in which ``1'' and ``0'' are inserted alternately in each frame.
a detection unit; a counter that counts the “0” signal detected by the “0” detection unit for a period of at least seven frames; a timer that sets a count period between the seven frames of the counter; and count contents of the counter. An AIS detection circuit comprising: a determination unit that determines that the AIS signal is the AIS signal when is 1 or less.