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JPH0227817B2 - - Google Patents
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JPH0227817B2 - - Google Patents

Info

Publication number
JPH0227817B2
JPH0227817B2 JP59054910A JP5491084A JPH0227817B2 JP H0227817 B2 JPH0227817 B2 JP H0227817B2 JP 59054910 A JP59054910 A JP 59054910A JP 5491084 A JP5491084 A JP 5491084A JP H0227817 B2 JPH0227817 B2 JP H0227817B2
Authority
JP
Japan
Prior art keywords
brazing
gold
ceramic substrate
layer
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59054910A
Other languages
Japanese (ja)
Other versions
JPS60198761A (en
Inventor
Juzo Shimada
Kazuaki Uchiumi
Masanori Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP59054910A priority Critical patent/JPS60198761A/en
Publication of JPS60198761A publication Critical patent/JPS60198761A/en
Publication of JPH0227817B2 publication Critical patent/JPH0227817B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465Application of solder

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はパツケージ基板における入出力電気接
続ピンを接着する方法に係り、更に具体的にいえ
ば多層セラミツク基板の接続ピンを基板に結合さ
せるための接合手段に係る。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for bonding input/output electrical connection pins on a package substrate, and more specifically, for bonding connection pins of a multilayer ceramic substrate to the substrate. This relates to the joining means.

(従来技術) 最近のコンピユータシステム等の高密度小型
化、高速化およびパフオーマンス化に対して実装
レベルにおけるパツケージ基板の要求はますます
きびしいものになつてきている。具体的にはパツ
ケージ基板において配線密度を高め信号線幅を微
細化すること、信号線導体の抵抗値を下げるこ
と、絶縁材料の誘電率を下げること等が要求され
ており、これに応えるようなパツケージ基板技術
が開発されてきた。例えばアルミナグリーンシー
トを用いた多層セラミツク基板ガラスセラミツク
グリーンシートを用い900℃程度で焼結出来、金
および銀−パラジウム系導体が使える低温焼結多
層セラミツク基板、またセラミツク基板上へスパ
ツタ蒸着等の薄膜技術を用いたパツケージ基板、
更には有機絶縁材料(ポリイミド等)を用い薄膜
導体と組み合せたパツケージ基板等々がある。こ
のような高密度化、微細化された実装基板上へ
は、超LSIチツプが多数実装されることになり、
したがつて、基板外部と電気的に接続するための
入出力端子数は極めて多くなつてくる。そのため
入出力端子を多層基板裏面にピンで形成する技術
が開発されている。
(Prior Art) With the recent miniaturization, high-density, and high-speed performance of computer systems, the requirements for package boards at the mounting level are becoming increasingly strict. Specifically, there are demands for increasing wiring density and miniaturizing signal line widths on package boards, lowering the resistance value of signal line conductors, and lowering the dielectric constant of insulating materials. Package board technology has been developed. For example, multilayer ceramic substrates using alumina green sheets, low-temperature sintered multilayer ceramic substrates that can be sintered at around 900℃ using glass ceramic green sheets, and gold and silver-palladium conductors can be used, and thin films such as spatter deposition on ceramic substrates. Package board using technology,
Furthermore, there are package substrates made of organic insulating materials (polyimide, etc.) in combination with thin film conductors. Many VLSI chips will be mounted on such high-density, miniaturized mounting boards.
Therefore, the number of input/output terminals for electrical connection to the outside of the board becomes extremely large. Therefore, a technology has been developed in which input/output terminals are formed using pins on the back surface of a multilayer board.

この多層セラミツク基板に接続ピンを取り付け
る従来技術としては、例えばアルミナ多層基板に
おいて銀ろうを用いてコバールは4・2アロイ等
の材質の接続ピンを取り付けていた。第1図は、
従来方法を説明するための図であり、アルミナグ
リーンシートに形成したモリブデン又はタングス
テン等の導体パツドおよびスルーホール中の導体
を1500℃以上の温度で還元雰囲気中で焼結したの
ちのセラミツク基板1およびモリブデン又はタン
グステン等の導体2が示されている。この導体パ
ツド部分にメツキによりニツケル層3を形成し、
次に、コバール又は4・2アロイの接続ピン5を
銀ろう4により取り付けている。銀ろうの組成
は、一般にはAg60mol%−Cu40mol%の共晶合
金が使われており融点は779℃であり、ろう付け
処理温度は810℃程度であり、モリブデン等の導
体の酸化を防ぐために水素還元雰囲気中で行なわ
れる。次に基板に取り付けられた接続ピンおよび
導体が劣化しないように金メツキ処理される。第
2図には、金層6が形成された接続ピン付き基板
を示す。本方法はろう付け処理温度が高く、基板
上に形成した微細薄膜パターン等は、この温度に
加熱することは難かしく、一方あらかじめピンを
基板に取り付けたのち信号線等の微細薄膜パター
ンを形成する場合においても、ピン付き基板上へ
各種パターンを形成する際の精度が悪くなり、作
業性も低下する。また有機絶縁フイルム(ポリイ
ミド等)を用いて多層セラミツク基板上へパター
ンを形成するパツケージ技術の場合でも同様であ
る。更にろう付け後接続ピンおよび導体パツド部
を金メツキする工程が含まれ作業性が悪い。
As a conventional technique for attaching connection pins to this multilayer ceramic substrate, for example, connection pins made of a material such as Kovar 4.2 alloy were attached to an alumina multilayer substrate using silver solder. Figure 1 shows
This is a diagram for explaining a conventional method, and shows a ceramic substrate 1 and a ceramic substrate after conductor pads made of molybdenum or tungsten formed on an alumina green sheet and conductors in through holes are sintered in a reducing atmosphere at a temperature of 1500°C or higher. A conductor 2, such as molybdenum or tungsten, is shown. A nickel layer 3 is formed on this conductor pad part by plating,
Next, connecting pins 5 made of Kovar or 4.2 alloy are attached using silver solder 4. The composition of silver solder is generally a eutectic alloy of 60 mol% Ag - 40 mol% Cu, with a melting point of 779°C and a brazing temperature of about 810°C. It is carried out in a reducing atmosphere. The connection pins and conductors attached to the board are then gold-plated to prevent deterioration. FIG. 2 shows a substrate with connection pins on which a gold layer 6 is formed. This method requires a high brazing temperature, and it is difficult to heat fine thin film patterns formed on the substrate to this temperature.On the other hand, pins are attached to the substrate in advance and then fine thin film patterns such as signal lines are formed. Even in this case, the accuracy when forming various patterns on the pin-equipped substrate deteriorates, and the workability also deteriorates. The same applies to packaging technology in which a pattern is formed on a multilayer ceramic substrate using an organic insulating film (polyimide or the like). Furthermore, it involves a step of gold plating the connection pins and conductor pads after brazing, resulting in poor workability.

次に処理温度を低げるためにろう材としてAu
−Sn又はAu−Si、Au−Sn−Pd、Au−Sn−Ag
等が検討された。具体的な一例を第3図および第
4図に示す。第3図においてはセラミツク基板1
1の表面にモリブデン層12を付着させ、該モリ
ブデン層上にメツキ法等の手段によりニツケルの
被膜13を形成する。次に該ニツケル被膜上に金
ペーストにより金の被膜14を形成し熱処理によ
り金・ニツケル固溶体を形成している。続いて金
メツキ17を施した接続ピン16をAu−Snろう
材15により結合している。この方法において
金・ニツケル固溶体を形成する際には約700℃の
温度で水素還元中で行なつている。また第4図に
おいてはセラミツク基板21の表面にモリブデン
層22を付着させ、該モリブデン層上にニツケル
被膜23を形成し、該ニツケル被膜上へ障壁用の
金被膜24を形成している。該金被膜上にはSn
ゲツタリング金属のソースとして働く第族の金
属層25で被覆されたのち、金メツキ28を施し
た接続ピン27をAu−Snろう材26により結合
されている。これらの方法においては、いずれも
中間層として金属を形成しなければならずコスト
的にも不利である。また接続ピンを取り付けるパ
ツド部分には、あらかじめモリブデンパツドを形
成しておかなければならず工程的にもコスト的に
も不利であり、さらにろう付け等の熱処理に際し
てもモリブデンの酸化を防ぐために水素還元雰囲
気で行なわなければならなかつた。さらに、モリ
ブデンパツドとセラミツク基板との密着性をもた
せるためにガラスフリツト等の添加物をモリブデ
ンペースト中に含めねばならず、導体抵抗も高く
なる問題があつた。
Next, in order to lower the processing temperature, Au was used as a brazing material.
−Sn or Au−Si, Au−Sn−Pd, Au−Sn−Ag
etc. were considered. A specific example is shown in FIGS. 3 and 4. In Fig. 3, the ceramic substrate 1
A molybdenum layer 12 is attached to the surface of the substrate 1, and a nickel coating 13 is formed on the molybdenum layer by a plating method or the like. Next, a gold coating 14 is formed on the nickel coating using gold paste, and a gold/nickel solid solution is formed by heat treatment. Subsequently, connection pins 16 coated with gold plating 17 are connected using Au--Sn brazing material 15. In this method, the gold-nickel solid solution is formed at a temperature of about 700°C under hydrogen reduction. Further, in FIG. 4, a molybdenum layer 22 is attached to the surface of a ceramic substrate 21, a nickel film 23 is formed on the molybdenum layer, and a gold film 24 for a barrier is formed on the nickel film. On the gold coating, Sn
After being coated with a group metal layer 25 serving as a source of gettering metal, a connecting pin 27 plated with gold 28 is bonded by an Au--Sn brazing material 26. In all of these methods, metal must be formed as an intermediate layer, which is disadvantageous in terms of cost. In addition, a molybdenum pad must be formed in advance on the pad where the connecting pin is attached, which is disadvantageous in terms of process and cost.Furthermore, during heat treatment such as brazing, hydrogen is used to prevent molybdenum from oxidizing. It had to be done in a reducing atmosphere. Furthermore, in order to provide good adhesion between the molybdenum pad and the ceramic substrate, additives such as glass frit must be included in the molybdenum paste, resulting in the problem of increased conductor resistance.

(発明の目的) 本発明の目的は、このような従来の欠点を除去
せしめ、従来の銀ろう材を用いる方法よりも低温
(400℃以下)で、しかも中性雰囲気で熱処理が出
来、また他の従来法で示したような障壁用の金被
膜を施さず、更にはピン取り付け部分のモリブデ
ンパツドを形成しない、非常に単純な構造をも
ち、作業性およびコスト的に有利でしかも十分な
ピン接着強度を有するろう付け方法を提供するこ
とにある。
(Objective of the Invention) The object of the present invention is to eliminate such conventional drawbacks, to enable heat treatment at a lower temperature (400°C or less) and in a neutral atmosphere than the conventional method using silver brazing material, and to It has a very simple structure that does not require gold coating for barriers as shown in the conventional method of An object of the present invention is to provide a brazing method having adhesive strength.

(発明の構成) すなわち本発明セラミツク基板上のろう付けす
る部分にチタンの膜を形成する工程と該チタン膜
上にパラジウム金属層を形成する工程と、ろう材
により入出力電気接続ピンをパラジウム金属層上
にろう付けする工程とを有することを特徴とする
ろう付け方法である。
(Structure of the Invention) That is, a step of forming a titanium film on the part to be brazed on the ceramic substrate of the present invention, a step of forming a palladium metal layer on the titanium film, and a step of forming a palladium metal layer on the input/output electrical connection pin using a brazing material. This is a brazing method characterized by comprising a step of brazing on the layer.

(実施例) 以下本発明を実施例に基づいて詳細に説明す
る。
(Examples) The present invention will be described in detail below based on Examples.

第5図〜第8図は本発明のろう付け方法を示す
図であり第9図は実施例において作製したピン付
きセラミツク基板の模式図である。第5図に示す
ように多層セラミツク基板31のセラミツク表面
上に金属の薄板をエツチング等の手段により形成
したろう付け部分の空いているマスク32を重ね
合わせる。多層セラミツク基板31はアルミナグ
リーンシートを用い導体としてモリブデン又はタ
ングステン等を印刷し積層プレス後1500℃以上の
水素還元雰囲気中で焼結したものでもよく、ある
いはホウケイ酸鉛系結晶化ガラスとアルミナから
出来ているガラスセラミツクグリーンシートを用
い導体として金、銀、銀−パラジウム系、金−白
金系、銀−白金系等を印刷し、積層プレス後1000
℃以下の酸化性雰囲気中で焼結したいわゆる低温
焼結多層セラミツク基板等でもよい。ここでは銀
−パラジウムを用いた後者の基板を用いた。次に
チタン被膜を形成した。第6図に示すように、セ
ラミツク基板に重ね合わされたマスクの上からス
パツタリングにより300Å〜1000Åの厚さのチタ
ン膜33を形成する。第6図で形成したチタン膜
の上から続けて周期律表の第族の金属の中から
パラジウム層34を第7図に示すように形成す
る。パラジウム層はチタン薄膜形成と同様のスパ
ツタリングにより1000Å〜3000Åの厚さになるよ
うに形成した。スパツタは10-5torr以下にした
後、Arガスを10-2torr程度まで導入して行つた。
第8図にはチタン薄膜、パラジウム金属の膜を形
成したのちマスクを除去したときの断面図を示
す。第8図からわかるように本方法ではセラミツ
ク基板表面に直接にチタン膜が形成されておりこ
の点が他の方法と大きく異なつている特徴の一つ
である。このようにして得られた金属パツド部を
有するセラミツク基板を金80%錫20%の重量比の
合金ろう材35がそれぞれ1〜3mg程度取付けら
れた複数のコバール又は4・2アロイ等の材質の
入出力電気接続用ピン36上に置き、第族金属
であるパラジウム層上に結合させる。第9図には
以上の方法により取り付けられた接続ピン付き多
層セラミツク基板の模式図を示してあるが、金属
製ピン36の表面にはメツキ等により形成した金
の被膜層37がコートしてある。ろう付けを行な
う処理温度としては、金80%錫20%の重量比の合
金ろう材の融点が280℃であることから、300℃〜
450℃の温度範囲で10〜30分間行なつた。パラジ
ウム層は金−錫ろう材の錫のゲツタリングを引き
起こし、金の錫に対する見かけの割合を多くする
ことになり、したがつて冷却後又はろう材の凝縮
後にろう付けした結合部分の融点を上昇する効果
がある。このことは、ピン取り付け後の熱サイク
ルを加える工程を有する場合に対して有効であ
る。また接続ピンに施した金被膜層においても、
ろう付け処理の際、金被膜層が金−錫ろう材と共
に一部融けることになり金−錫ろう材中の割合が
増加し結合部分の融点を上昇させ同様の効果が得
られる。本方法によりろう付けした入出力電気接
続ピンと多層セラミツク基板との接着強度は4.0
Kg/mm2以上を示し、実装基板の入出力ピンとして
十分な強度を示す。
5 to 8 are diagrams showing the brazing method of the present invention, and FIG. 9 is a schematic diagram of a ceramic substrate with pins produced in an example. As shown in FIG. 5, a mask 32 with a blank area for brazing, which is formed by etching a thin metal plate, is placed on the ceramic surface of a multilayer ceramic substrate 31. The multilayer ceramic substrate 31 may be made of an alumina green sheet printed with molybdenum or tungsten as a conductor, laminated and pressed, and then sintered in a hydrogen reducing atmosphere at 1500°C or higher, or made of lead borosilicate crystallized glass and alumina. Gold, silver, silver-palladium, gold-platinum, silver-platinum, etc. are printed as conductors using glass-ceramic green sheets.
A so-called low-temperature sintered multilayer ceramic substrate sintered in an oxidizing atmosphere at temperatures below 0.degree. C. may also be used. Here, the latter substrate using silver-palladium was used. Next, a titanium film was formed. As shown in FIG. 6, a titanium film 33 having a thickness of 300 Å to 1000 Å is formed by sputtering on the mask superimposed on the ceramic substrate. Continuing on from the titanium film formed in FIG. 6, a palladium layer 34 is formed from among the metals of the group of the periodic table, as shown in FIG. The palladium layer was formed to a thickness of 1000 Å to 3000 Å by sputtering similar to that used for forming the titanium thin film. After reducing the sputtering temperature to below 10 -5 torr, Ar gas was introduced to about 10 -2 torr.
FIG. 8 shows a cross-sectional view when the mask is removed after forming a titanium thin film and a palladium metal film. As can be seen from FIG. 8, in this method, a titanium film is formed directly on the surface of the ceramic substrate, and this is one of the features that is significantly different from other methods. The ceramic substrate having the metal pad portion obtained in this way is then coated with a plurality of materials such as Kovar or 4.2 alloy, each having about 1 to 3 mg of alloy brazing filler metal 35 with a weight ratio of 80% gold and 20% tin. It is placed on pins 36 for input/output electrical connections and bonded onto a layer of palladium, which is a group metal. FIG. 9 shows a schematic diagram of a multilayer ceramic substrate with connecting pins attached by the above method, and the surface of the metal pin 36 is coated with a gold film layer 37 formed by plating or the like. . The processing temperature for brazing is 300°C to 300°C, since the melting point of an alloy brazing filler metal with a weight ratio of 80% gold and 20% tin is 280°C.
It was carried out for 10-30 minutes at a temperature range of 450°C. The palladium layer causes gettering of the tin in the gold-tin brazing material, increasing the apparent ratio of gold to tin and thus increasing the melting point of the brazed joint after cooling or condensation of the brazing material. effective. This is effective in cases where there is a step of applying a thermal cycle after attaching the pin. In addition, the gold coating layer applied to the connection pins also
During the brazing process, the gold coating layer partially melts together with the gold-tin brazing material, increasing the proportion of gold-tin in the brazing material and raising the melting point of the bonded portion, producing the same effect. The adhesive strength between the input/output electrical connection pins brazed using this method and the multilayer ceramic substrate is 4.0.
Kg/mm 2 or more, indicating sufficient strength as input/output pins for mounting boards.

(発明の効果) 以上の如く、本発明のろう付け方法を採用する
ことにより、ろう付け処理を400℃以下という極
めて低温で、しかも中性雰囲気中で行なうことが
出来、セラミツク基板表面にピンパツド用の厚膜
金属(モリブデン、タングステン、金、銀、銀−
パラジウム等)層をあらかじめ形成する必要がな
く、また障壁用の金被膜も施さない単純な構造を
もつた十分な接着強度を有するピン付き基板を得
ることが出来るようになつた。さらに本発明の方
法はピンパツドの金属層を形成する際にエツチン
グ等の湿式工程を経ないためにセラミツクに対す
る悪影響は全く与えず信頼性の高いピン付き基板
を提供することが出来、また作業性およびコスト
的にも有利となり、ピン付け後の熱サイクルに対
しても十分に強いピン付け基板を得ることが出来
るようになつた。
(Effects of the Invention) As described above, by adopting the brazing method of the present invention, the brazing process can be performed at an extremely low temperature of 400°C or less and in a neutral atmosphere, and pin pads can be formed on the surface of the ceramic substrate. thick film metals (molybdenum, tungsten, gold, silver, silver)
It has now become possible to obtain a pinned substrate with sufficient adhesive strength that has a simple structure that does not require the prior formation of a layer (such as palladium) and does not require a gold coating for a barrier. Furthermore, since the method of the present invention does not involve wet processes such as etching when forming the metal layer of the pin pad, it does not have any adverse effects on the ceramic and can provide a highly reliable substrate with pins. It has become advantageous in terms of cost, and it has become possible to obtain a pinned board that is sufficiently strong against thermal cycles after pinning.

さらにスパツタリングでなく、適時蒸着、メツ
キ、スクリーン印刷などの膜形成手段を用いるこ
とができる。
Furthermore, instead of sputtering, film forming means such as timed vapor deposition, plating, and screen printing can be used.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第4図は、従来のピン付けセラミツク
基板を示した図であり、第5図〜第8図は本発明
の方法を示す図であり、第9図は本発明の方法に
より作製したピン付き基板の模式図である。 図において、1,11,21,31……セラミ
ツク基板、2,12,22……厚膜導体パツド
層、3,13,23……ニツケル層、4……銀ろ
う、5,16,27,36……金属ピン、6,1
7,28,37……金被膜層、14……金被膜、
15,26,35……金−錫ろう、24……金被
膜、25……第族金属層、32……マスク、3
3……チタン膜、34……パラジウム金属膜。
1 to 4 are diagrams showing conventional pinned ceramic substrates, FIGS. 5 to 8 are diagrams showing the method of the present invention, and FIG. 9 is a diagram showing the method of the present invention. FIG. 2 is a schematic diagram of a pin-equipped board. In the figure, 1, 11, 21, 31... Ceramic substrate, 2, 12, 22... Thick film conductor pad layer, 3, 13, 23... Nickel layer, 4... Silver solder, 5, 16, 27, 36...Metal pin, 6,1
7, 28, 37... Gold coating layer, 14... Gold coating,
15, 26, 35... Gold-tin wax, 24... Gold coating, 25... Group metal layer, 32... Mask, 3
3...Titanium film, 34...Palladium metal film.

Claims (1)

【特許請求の範囲】 1 セラミツク基板に金属製接続ピンをろう材に
よりろう付けする方法であつて、セラミツク基板
上のろう付けする部分にチタン膜を形成する工程
と、該チタン膜上にパラジウム金属膜を形成する
工程と、ろう材により接続ピンを該パラジウム金
属層上にろう付けする工程とを有することを特徴
とするろう付け方法。 2 ろう材は金−錫ろう材である特許請求の範囲
第1項記載のろう付け方法。
[Scope of Claims] 1. A method of brazing metal connection pins to a ceramic substrate using a brazing material, which includes the steps of forming a titanium film on the part to be brazed on the ceramic substrate, and depositing palladium metal on the titanium film. A brazing method comprising the steps of forming a film and brazing a connecting pin onto the palladium metal layer using a brazing material. 2. The brazing method according to claim 1, wherein the brazing material is a gold-tin brazing material.
JP59054910A 1984-03-22 1984-03-22 Soldering method Granted JPS60198761A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59054910A JPS60198761A (en) 1984-03-22 1984-03-22 Soldering method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59054910A JPS60198761A (en) 1984-03-22 1984-03-22 Soldering method

Publications (2)

Publication Number Publication Date
JPS60198761A JPS60198761A (en) 1985-10-08
JPH0227817B2 true JPH0227817B2 (en) 1990-06-20

Family

ID=12983753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59054910A Granted JPS60198761A (en) 1984-03-22 1984-03-22 Soldering method

Country Status (1)

Country Link
JP (1) JPS60198761A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004034450A1 (en) * 2002-10-11 2004-04-22 Tm Tech Co., Ltd. A sputtering apparatus having enhanced adhesivity of particles and a manufacturing method thereof
WO2004055873A1 (en) * 2002-12-14 2004-07-01 Tm Tech Co., Ltd. Thin film forming apparatus
CN113242650B (en) * 2021-05-20 2022-04-15 上海望友信息科技有限公司 Spraying graph generation method and system, electronic equipment and storage medium

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4824009A (en) * 1981-12-31 1989-04-25 International Business Machines Corporation Process for braze attachment of electronic package members

Also Published As

Publication number Publication date
JPS60198761A (en) 1985-10-08

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