JPH0231502B2 - - Google Patents
Info
- Publication number
- JPH0231502B2 JPH0231502B2 JP59054911A JP5491184A JPH0231502B2 JP H0231502 B2 JPH0231502 B2 JP H0231502B2 JP 59054911 A JP59054911 A JP 59054911A JP 5491184 A JP5491184 A JP 5491184A JP H0231502 B2 JPH0231502 B2 JP H0231502B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- pin
- palladium
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/66—Conductive materials thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明はパツケージ基板におけるピン取り付け
構造および取り付け方法に係り、更に具体的にい
えば多層セラミツク基板の接続ピン取り付け構造
および該ピンを基板に結合させるための接合手段
に係る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a pin attachment structure and attachment method on a package substrate, and more specifically, a connection pin attachment structure for a multilayer ceramic substrate and a connection pin to the substrate. It relates to a joining means for
(従来技術)
最近のコンピユータシステムの高密度小型化、
高速化および高パフオーマンス化に対して実装レ
ベルにおけるパツケージ基板への要求はきびしい
ものになつてきている。具体的にはパツケージ基
板において配線密度を高め信号線幅を微細化した
り、信号線導体の抵抗値を下げること、絶縁材料
の誘電率を下げること、等が要求されており、こ
れに応えるようなパツケージ基板技術が開発され
てきた。例えばアルミナグリーンシートを用いた
多層セラミツク基板、ガラスセラミツクスグリー
ンシートを用い900℃程度で焼結でき、Auおよび
Ag−Pd導体が使える多層セラミツク基板、また
セラミツク基板上へスパツタ、蒸着等の薄膜技術
を用いたパツケージ基板、更には有機絶縁材料
(ポリイミド等)を用い薄膜導体と組み合せたパ
ツケージ基板等々がある。このように高密度化、
微細化された実装基板上へは超LSIチツプが多数
実装されることになり、したがつて、基板外部と
電気的に接続するためのI/O端子数は極めて多
くなつてくる。そのためI/O端子を多層基板裏
面にピンで形成する技術が開発されている。(Prior art) Recent computer systems have become more compact and dense,
The requirements for package substrates at the mounting level are becoming stricter in order to achieve higher speeds and higher performance. Specifically, there are demands for higher wiring density on package boards, smaller signal line widths, lower resistance values of signal line conductors, and lower dielectric constants of insulating materials. Package board technology has been developed. For example, multilayer ceramic substrates using alumina green sheets, glass ceramic green sheets can be sintered at around 900℃, and Au and
There are multilayer ceramic substrates that can use Ag-Pd conductors, package substrates that use thin film techniques such as sputtering and vapor deposition on ceramic substrates, and package substrates that use organic insulating materials (polyimide, etc.) in combination with thin film conductors. In this way, densification,
A large number of VLSI chips will be mounted on a miniaturized mounting board, and as a result, the number of I/O terminals for electrical connection with the outside of the board will become extremely large. Therefore, a technique has been developed in which I/O terminals are formed using pins on the back surface of a multilayer substrate.
この多層セラミツク基板に接続ピンを取り付け
る従来技術としては、例えばアルミナ多層基板に
おいて銀ろうを用いてコバール又は4・2アロイ
等の材質の接続ピンを取り付けていた。第1図
は、従来方法を説明するための断面図であり、ア
ルミナグリーンシートに形成したモリブデン又は
タングステン等の導体パツドおよびスルーホール
中の導体を1500℃以上の温度で環元雰囲気中で焼
結したのちのセラミツク基板1およびモリブデン
又はタングステン等の導体2が示されている。こ
の導体パツド部分にメツキによりニツケル層3を
形成し、次に、コバール又は4・2アロイの接続
ピン5を銀ろう4により取り付けている。銀ろう
の組成は、一般にはAg60mol%−Cu40mol%の
共晶合金が使われており融点は779℃であり、ろ
う付処理温度は810℃程度であり、モリブデン等
の導体の酸化を防ぐために水素還元雰囲気中で行
なわれる。次に基板に取り付けられた接続ピンお
よび導体が劣化しないように金メツキ処理され
る。第2図には、金層6が形成された接続ピン付
き基板の断面図を示す。本方法はろう付け処理温
度が高く、基板上に形成した微細薄膜パターン等
は、この温度に加熱することは難かしく、一方あ
らかじめピンを基板に取り付けたのち信号線等の
微細薄膜パターンを形成する場合においても、ピ
ン付き基板上へ各種パターンを形成する際の精度
が低くなり作業性が悪くなる。また有機絶縁フイ
ルム(ポリイミド等)を用いて多層セラミツク基
板上へパターンを形成するパツケージ技術の場合
でも同様である。更にろう付け後接続ピンおよび
導体パツド部を金メツキする工程が含まれ作業性
が悪い。 As a conventional technique for attaching connection pins to this multilayer ceramic substrate, for example, connection pins made of a material such as Kovar or 4.2 alloy were attached to an alumina multilayer substrate using silver solder. Figure 1 is a cross-sectional view for explaining the conventional method, in which conductor pads made of molybdenum or tungsten formed on an alumina green sheet and conductors in through holes are sintered in an annular atmosphere at a temperature of 1500°C or higher. The resulting ceramic substrate 1 and conductor 2, such as molybdenum or tungsten, are shown. A nickel layer 3 is formed on this conductor pad portion by plating, and then a connecting pin 5 of Kovar or 4.2 alloy is attached using silver solder 4. The composition of silver solder is generally a eutectic alloy of 60 mol% Ag - 40 mol% Cu, with a melting point of 779°C and a brazing temperature of about 810°C. It is carried out in a reducing atmosphere. The connection pins and conductors attached to the board are then gold-plated to prevent deterioration. FIG. 2 shows a cross-sectional view of a substrate with connection pins on which a gold layer 6 is formed. This method requires a high brazing temperature, and it is difficult to heat fine thin film patterns formed on the substrate to this temperature.On the other hand, pins are attached to the substrate in advance and then fine thin film patterns such as signal lines are formed. Even in this case, the accuracy when forming various patterns on the pin-equipped substrate becomes low, resulting in poor workability. The same applies to packaging technology in which a pattern is formed on a multilayer ceramic substrate using an organic insulating film (polyimide or the like). Furthermore, it involves a step of gold plating the connection pins and conductor pads after brazing, resulting in poor workability.
次に処理温度を低げるためにろう材としてAu
−Sn又はAu−Si、Au−Sn−Pd、Au−Sn−Ag
等が検討された。具体的な一例を第3図および第
4図に示す。第3図においてはセラミツク基板1
1の表面にモリブデン層12を付着させ、該モリ
ブデン層上にメツキ法等の手段によりニツケルの
被膜13を形成する。次に該ニツケル被膜上に金
ペーストにより金の被膜14を形成し熱処理によ
り金・ニツケル固溶体を形成している。続いて金
メツキ17を施した接続ピン16をAu−Snろう
材15により結合している。この方法において
金・ニツケル固溶体を形成する際には約700℃の
温度で水素還元中で行なつている。また第4図に
おいてはセラミツク基板21の表面にモリブデン
層22を付着させ、該モリブデン層上にニツケル
被膜23を形成し、該ニツケル被膜上へ障壁用の
金被膜24を形成している。該金被膜上にはSn
ゲツタリング金属のソースとして働く第族の金
属層25で被覆したのち、金メツキ28を施した
接続ピン27をAu−Snろう材26により結合し
ている。これらの方法においてはいずれも中間層
として金属を形成しなければならずコスト的にも
不利である。また接続ピンを取り付けるパツド部
分には、あらかじめモリブデンパツドを形成して
おかなければならず工程的にもコスト的にも不利
であり、さらにろう付け等の熱処理に際してもモ
リブデンの酸化を防ぐために水素還元雰囲気で行
なわなければならなかつた。さらにモリブデンパ
ッドとセラミツク基板との密着性をもたせるため
にガラスフリツト等の添加物をモリブデンペース
ト中に含めねばならず、導体抵抗も高くなる問題
があつた。 Next, in order to lower the processing temperature, Au was used as a brazing material.
−Sn or Au−Si, Au−Sn−Pd, Au−Sn−Ag
etc. were considered. A specific example is shown in FIGS. 3 and 4. In Fig. 3, the ceramic substrate 1
A molybdenum layer 12 is attached to the surface of the substrate 1, and a nickel coating 13 is formed on the molybdenum layer by a plating method or the like. Next, a gold coating 14 is formed on the nickel coating using gold paste, and a gold/nickel solid solution is formed by heat treatment. Subsequently, connection pins 16 coated with gold plating 17 are connected using Au--Sn brazing material 15. In this method, the gold-nickel solid solution is formed at a temperature of approximately 700°C under hydrogen reduction. Further, in FIG. 4, a molybdenum layer 22 is attached to the surface of a ceramic substrate 21, a nickel film 23 is formed on the molybdenum layer, and a gold film 24 for a barrier is formed on the nickel film. On the gold coating, Sn
After being coated with a group metal layer 25 serving as a source of gettering metal, a connecting pin 27 plated with gold 28 is bonded by an Au--Sn brazing material 26. In all of these methods, metal must be formed as an intermediate layer, which is disadvantageous in terms of cost. In addition, a molybdenum pad must be formed in advance on the pad where the connecting pin is attached, which is disadvantageous in terms of process and cost.Furthermore, during heat treatment such as brazing, hydrogen is used to prevent molybdenum from oxidizing. It had to be done in a reducing atmosphere. Furthermore, in order to provide good adhesion between the molybdenum pad and the ceramic substrate, additives such as glass frit must be included in the molybdenum paste, resulting in the problem of increased conductor resistance.
(発明の目的)
本発明の目的は、このような従来の欠点を除去
せしめ、従来の銀ろう材を用いる方法よりも低温
(400℃以下)でしかも中性雰囲気で熱処理がで
き、また他の従来法で示したような障壁用の金被
膜を施さず、非常に単純な構造をもち、作業性お
よびコスト的に有利でしかも十分なピン接着強度
を有するピン付基板およびその製造方法を提供す
ることにある。(Object of the invention) The object of the present invention is to eliminate such conventional drawbacks, to enable heat treatment at a lower temperature (400°C or less) and in a neutral atmosphere than the conventional method using silver brazing material, and to be able to perform heat treatment in a neutral atmosphere. To provide a substrate with pins and a method for manufacturing the same, which does not require a gold coating for a barrier as shown in conventional methods, has a very simple structure, is advantageous in terms of workability and cost, and has sufficient pin bonding strength. There is a particular thing.
(発明の構成)
すなわち本発明は基板上に直接形成されたクロ
ム金属層および該クロム金属層上に形成されたパ
ラジウム金属層と、該パラジウム金属層上にろう
材を介して金属製ピンが形成されたことを特徴と
するピン付基板および基板上にクロム金属の膜を
形成する工程と該クロム金属膜上にパラジウム金
属膜を形成する工程と、ドライフイルムをラミネ
ートし、露光、現像を行なう工程と前記パラジウ
ム金属層とクロム金属層をエツチングする工程
と、ろう材により接続ピンをパラジウム金属層上
にろう付けする工程を有することを特徴とするピ
ン付基板の製造方法である。(Structure of the Invention) That is, the present invention includes a chromium metal layer formed directly on a substrate, a palladium metal layer formed on the chromium metal layer, and a metal pin formed on the palladium metal layer via a brazing material. A step of forming a chromium metal film on a substrate with pins and a substrate, a step of forming a palladium metal film on the chromium metal film, and a step of laminating a dry film, exposing it, and developing it. A method of manufacturing a pin-equipped substrate is characterized by comprising the steps of etching the palladium metal layer and the chromium metal layer, and brazing the connecting pins onto the palladium metal layer using a brazing material.
(実施例)
以下本発明を実施例に基づいて詳細に説明す
る。(Examples) The present invention will be described in detail below based on Examples.
第5図〜第11図は本発明の製造方法を示す図
であり第12図は実施例において作製した本発明
のピン付基板の模式図である。第5図に示すよう
に多層セラミツク基板31のセラミツク表面上に
クロムの薄膜32を被覆する。多層セラミツク基
板31はアルミナグリーンシートを用い導体とし
てモリブデン又はタングステンを印刷し積層プレ
ス後1500℃以上水素還元雰囲気中で焼結したも
の、あるいはガラスセラミツクグリーンシートを
用い導体として金、銀−パラジウム、金−白金、
銀−白金、銀等を印刷し積層プレス後1000℃以下
酸化性雰囲気中で焼結した、いわゆる低温焼結セ
ラミツク基板等が使用できる。この実施例では後
者の銀−パラジウムを印刷した低温焼結セラミツ
ク基板を用いた。一方クロム薄膜はスパツタリン
グにより500Å〜2000Åの厚さに形成した。次に
第6図の周期律表第族の金属のなかでパラジウ
ム層33を第5図に示したクロム薄膜上に形成す
る。パラジウム層はクロム薄膜形成と同様スパツ
タリングにより500〜2000Åの厚さに形成した。
スパツタリングは10-5torr以下にした後Arガスを
導入し10-2torr程度にして行なつた第6図で薄膜
形成したセラミツク基板にドライフイルム(デユ
ポン製。商品名リストン)34を第7図のように
ラミネートしたのちピンパツドパターンのマスク
を重ね合せて紫外光により露光し現像してピンパ
ツドパターン以外を洗い流す。第8図には露光、
現像して残つたピンパツド部の重合レジスト層3
5を示す。次にパラジウム金属のエツチング工程
であり第9図に示すようにFeCl3系のエツチヤン
トによりパラジウム層をエツチングにより取り除
きパツド部分を残す。第10図においてはクロム
層をエツチングにより取り除いた図を示すが、ク
ロムのエツチングに際してのエツチヤントは
AlCl3、HClを含んだ水溶液を用いた。第11図
には、ドライフイルム層を除去したセラミツク基
板上にクロム層およびパラジウム層を形成した構
造体を示す。ドライフイルム層の除去は熱処理に
より燃焼させて行なつた。このようにして得られ
た金属パツド部を有するセラミツク基板をAu80
%Sn20%の重量比の合金ろう材36を各ピン当
り1〜3mg程度取り付けた多数のコバール又は
4・2アロイの接続ピン37上に置き、第族金
属であるパラジウム層上に結合させる。第12図
には以上の方法により取り付けられたピン付基板
の模式図を示してあるが、接続ピン37の表面に
はメツキ等により形成した金属がコートしてあ
る。ろう付けを行なう処理温度としてはAu80%
Sn20%の重量比の合金ろう材の融点が280℃で
あり300℃〜450℃の温度範囲で10〜30分間行なつ
た。パラジウム層はAu−Snろう材のSnのゲツタ
リングを引き起こし、AuのSnに対する見かけの
割合を多くすることになり、したがつて冷却後又
はろう材の凝縮後にろう付けした結合部分の融点
を上昇される効果がある。このことはピン取り付
け後の熱サイクルを加える工程を有する場合に対
し有効である。また接続ピンに施した金属におい
てもろう付け処理の際、金属がAu−Snろう材と
共に融けることになりAu−Snろう材中のAuの割
合が増加し融点を上昇させ同様の効果が得られ
る。ろう付けした接続ピンのセラミツク基板との
接着強度は4.0Kg/mm2以上を示し、実装基板の
I/Oピンとして十分な強度を示した。 5 to 11 are diagrams showing the manufacturing method of the present invention, and FIG. 12 is a schematic diagram of a substrate with pins of the present invention produced in an example. As shown in FIG. 5, a thin chromium film 32 is coated on the ceramic surface of a multilayer ceramic substrate 31. As shown in FIG. The multilayer ceramic substrate 31 is made of an alumina green sheet printed with molybdenum or tungsten as a conductor, laminated pressed and then sintered in a hydrogen reducing atmosphere at 1500°C or higher, or a glass ceramic green sheet with gold, silver-palladium, or gold printed as a conductor. -Platinum,
A so-called low-temperature sintered ceramic substrate, which is printed with silver-platinum, silver, etc., laminated and pressed, and then sintered in an oxidizing atmosphere at 1000° C. or lower, can be used. In this example, a low-temperature sintered ceramic substrate printed with the latter silver-palladium was used. On the other hand, the chromium thin film was formed by sputtering to a thickness of 500 Å to 2000 Å. Next, a palladium layer 33, which is a metal of group 3 of the periodic table shown in FIG. 6, is formed on the chromium thin film shown in FIG. The palladium layer was formed to a thickness of 500 to 2000 Å by sputtering, similar to the formation of the chromium thin film.
Sputtering was carried out at a temperature of 10 -5 torr or less, and then Ar gas was introduced at a temperature of about 10 -2 torr. A dry film (manufactured by Dupont, trade name Riston) 34 was applied to the ceramic substrate on which the thin film was formed as shown in Fig. 6. After laminating as shown above, a pin pad pattern mask is placed on top of the other, exposed to ultraviolet light, developed, and the parts other than the pin pad pattern are washed away. Figure 8 shows exposure,
Polymerized resist layer 3 on the pin pad portion remaining after development
5 is shown. Next is the palladium metal etching step, as shown in FIG. 9, where the palladium layer is removed by etching using an FeCl 3 -based etchant, leaving a pad portion. Figure 10 shows the chromium layer removed by etching, but the etchant used when etching the chromium is
An aqueous solution containing AlCl 3 and HCl was used. FIG. 11 shows a structure in which a chromium layer and a palladium layer are formed on a ceramic substrate from which a dry film layer has been removed. The dry film layer was removed by burning through heat treatment. The ceramic substrate with the metal pad portion thus obtained was made of Au80.
An alloy brazing filler material 36 having a weight ratio of %Sn20% is placed on a number of Kovar or 4.2 alloy connecting pins 37 with approximately 1 to 3 mg of each pin attached, and bonded to a layer of palladium, which is a group metal. FIG. 12 shows a schematic diagram of a board with pins attached by the above method, and the surface of the connection pin 37 is coated with metal formed by plating or the like. The processing temperature for brazing is 80% Au.
The melting point of the alloy brazing filler metal with a weight ratio of 20% Sn is 280°C, and the test was carried out at a temperature range of 300°C to 450°C for 10 to 30 minutes. The palladium layer causes gettering of Sn in the Au-Sn filler metal, increasing the apparent ratio of Au to Sn and thus increasing the melting point of the brazed joint after cooling or condensation of the filler metal. It has the effect of This is effective in cases where there is a step of applying a thermal cycle after attaching the pin. Also, when the metal applied to the connecting pin is brazed, the metal melts together with the Au-Sn brazing material, increasing the proportion of Au in the Au-Sn brazing material and raising the melting point, producing the same effect. . The adhesion strength of the brazed connection pins to the ceramic substrate was 4.0 Kg/mm 2 or more, indicating sufficient strength as I/O pins on a mounting board.
(発明の効果)
以上の如く、本発明のピン付基板の構造および
製造方法を採用することにより、ろう付け処理を
400℃以下と低温で、中性雰囲気中で行なうこと
が出来、セラミツク基板表面にピンパツド用の厚
膜金属(モリブデン、タングステン、金、金−白
金等)層をあらかじめ形成する必要がなく、また
障壁用の金被膜も施さない単純な構造をもつた十
分な接着強度を有するピン付基板を得ることが出
来るようになつた。さらに本発明により作業性お
よびコスト的にも有利となり、ピン立て後の熱サ
イクルに強いピン付基板を得ることが出来るよう
になつた。(Effects of the Invention) As described above, by adopting the structure and manufacturing method of the pin-equipped substrate of the present invention, the brazing process can be easily performed.
It can be carried out in a neutral atmosphere at a low temperature of 400℃ or less, and there is no need to previously form a thick metal layer (molybdenum, tungsten, gold, gold-platinum, etc.) for pin pads on the surface of the ceramic substrate, and there is no need to form a barrier layer. It has now become possible to obtain a pin-equipped substrate with a simple structure that does not require any additional gold coating and has sufficient adhesive strength. Further, the present invention is advantageous in terms of workability and cost, and it has become possible to obtain a pin-equipped substrate that is resistant to thermal cycles after pin-setting.
また金属膜形成方法はスパツタリングの他に蒸
着、メツキ、スクリーン印刷など適時使用でき
る。 In addition to sputtering, metal film forming methods such as vapor deposition, plating, and screen printing can be used as appropriate.
第1図〜第4図は、従来のピン付セラミツク基
板の構造を示した図であり、第5図〜第11図は
本発明の製造工程を示す図であり、第12図は本
発明の製造方法により作製したピン付基板の模式
図である。
図において1,11,21,31……セラミツ
ク基板、2,12,22……厚膜導体パツド層、
3,13,23……ニツケル層、4……銀ろう、
5,16,27,37……接続ピン、6……金
層、14……金被膜、15,26,36……Au
−Snろう、17,28,38……金メツキ層、
24……金被膜、25……パラジウム層、32…
…クロム被膜、33……パラジウム被膜、34…
…ドライフイルム、35……重合レジスト層。
Figures 1 to 4 are diagrams showing the structure of a conventional ceramic substrate with pins, Figures 5 to 11 are diagrams showing the manufacturing process of the present invention, and Figure 12 is a diagram showing the manufacturing process of the present invention. FIG. 2 is a schematic diagram of a pin-equipped substrate manufactured by the manufacturing method. In the figure, 1, 11, 21, 31...ceramic substrate, 2, 12, 22...thick film conductor pad layer,
3, 13, 23...nickel layer, 4...silver wax,
5, 16, 27, 37... Connection pin, 6... Gold layer, 14... Gold coating, 15, 26, 36... Au
-Sn wax, 17, 28, 38...gold plating layer,
24... Gold coating, 25... Palladium layer, 32...
...Chromium coating, 33... Palladium coating, 34...
...Dry film, 35...Polymerized resist layer.
Claims (1)
ム金属層上に形成されたパラジウム金属層と、パ
ラジウム金属層上にろう材を介して金属製ピンが
形成された構造をもつことを特徴とするピン付基
板。 2 基板上にクロム金属の膜を形成する工程と、
クロム金属膜上にパラジウム金属膜を形成する工
程とドライフイルムをラミネートし、露光、現像
をする工程と前記パラジウム金属層とクロム金属
層をエツチングする工程と、ろう材により接続ピ
ンをパラジウム金属層上にろう付けする工程を有
することを特徴とするピン付基板の製造方法。[Claims] 1. A structure in which a chromium metal is formed directly on a substrate, a palladium metal layer is formed on the chromium metal layer, and a metal pin is formed on the palladium metal layer via a brazing material. A board with pins. 2. Forming a chromium metal film on the substrate;
A step of forming a palladium metal film on the chromium metal film, a step of laminating the dry film, exposing and developing it, a step of etching the palladium metal layer and the chromium metal layer, and a step of attaching the connecting pin onto the palladium metal layer using a brazing material. 1. A method for manufacturing a board with pins, the method comprising the step of brazing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59054911A JPS60198762A (en) | 1984-03-22 | 1984-03-22 | Pinned substrate and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59054911A JPS60198762A (en) | 1984-03-22 | 1984-03-22 | Pinned substrate and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60198762A JPS60198762A (en) | 1985-10-08 |
| JPH0231502B2 true JPH0231502B2 (en) | 1990-07-13 |
Family
ID=12983780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59054911A Granted JPS60198762A (en) | 1984-03-22 | 1984-03-22 | Pinned substrate and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60198762A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4824009A (en) * | 1981-12-31 | 1989-04-25 | International Business Machines Corporation | Process for braze attachment of electronic package members |
-
1984
- 1984-03-22 JP JP59054911A patent/JPS60198762A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60198762A (en) | 1985-10-08 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |