JPH0228255B2 - - Google Patents
Info
- Publication number
- JPH0228255B2 JPH0228255B2 JP60030161A JP3016185A JPH0228255B2 JP H0228255 B2 JPH0228255 B2 JP H0228255B2 JP 60030161 A JP60030161 A JP 60030161A JP 3016185 A JP3016185 A JP 3016185A JP H0228255 B2 JPH0228255 B2 JP H0228255B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- layer
- sio
- type
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
- H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
Landscapes
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係り、特にFETのＴ型
ゲート近傍の新規構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a novel structure near the T-type gate of an FET.
半導体素子として半導体基板にオーミツクに接
続されたソース電極及びドレイン電極と制御電極
を有する電界効果トランジスタ（FET）が知ら
れている。このFETのゲートは低抵抗で且つ短
ゲート長であることが高周波動作の点から望まし
い。
A field effect transistor (FET) having a source electrode, a drain electrode, and a control electrode ohmicly connected to a semiconductor substrate is known as a semiconductor element. From the viewpoint of high frequency operation, it is desirable that the gate of this FET has low resistance and a short gate length.
そこで第４図に示されたように短ゲート長でし
かも断面積が大きいＴ型ゲートが知られている。 Therefore, as shown in FIG. 4, a T-type gate is known which has a short gate length and a large cross-sectional area.
第４図ではリセス１０を設けたｎ型GaAs活性
層３上に例えばアルミニウムからなるＴ型ゲート
１２、更に該ゲートの保護、配線形成のために
CVD法による例えばSiO2からなる絶縁層１６が
設けられている。このようなＴ型ゲートのFET
ではチヤネル部以外のＴ型ゲート下の絶縁層部は
その面積及び該絶縁層の材質によつてはゲート容
量が無視できない。例えばSiO2の場合は比誘電
率は3.8でありエア約１に対して大きいのでその
傾向が高い。
In FIG. 4, a T-type gate 12 made of aluminum, for example, is placed on an n-type GaAs active layer 3 provided with a recess 10, and is further provided for protection of the gate and wiring formation.
An insulating layer 16 made of, for example, SiO 2 is provided by a CVD method. This type of T-gate FET
The gate capacitance of the insulating layer portion under the T-shaped gate other than the channel portion cannot be ignored depending on the area and the material of the insulating layer. For example, in the case of SiO 2 , the dielectric constant is 3.8, which is larger than that of air, which is about 1, so this tendency is high.
上記問題点は本発明によれば基板上に形成され
た電界効果トランジスタの断面形状Ｔ型ゲート電
極を含んでなる半導体装置において、該電界効果
トランジスタのチヤネル部以外の該Ｔ型ゲート電
極と該基板との間にエアギヤツプを設けたことを
特徴とする半導体装置によつて解決される。
According to the present invention, in a semiconductor device including a T-shaped gate electrode of a field effect transistor formed on a substrate, the T-shaped gate electrode other than the channel portion of the field effect transistor and the substrate The problem is solved by a semiconductor device characterized in that an air gap is provided between the two.
すなわち、本発明によればSiO2等からなる絶
縁層部を空間（エアギヤツプ）にすることによつ
てゲート容量を小さくすることに寄与するもので
ある。
That is, the present invention contributes to reducing the gate capacitance by creating a space (air gap) in the insulating layer portion made of SiO 2 or the like.
以下本発明の実施例を面に基づいて説明する。 Embodiments of the present invention will be described below based on aspects.
第１図は本発明の実施例を示す断面図である。 FIG. 1 is a sectional view showing an embodiment of the present invention.
第１図によればGaAs基板２上にリセス１０を
設けたｎ型GaAs活性層３、更に該ｎ型GaAs活
性層３上にアルミニウムからなるＴ型ゲート１
２、及びCVD法によるSiO2からなる絶縁層１６
が設けられている。ｎ型GaAs活性層３表面とＴ
型ゲート１２の表面にはCVD法により形成され
たSi3N4からなる保護膜２３が形成されており、
またチヤネル部以外のＴ型ゲート１２下には空間
（エアギヤツプ）１７が形成されている。このエ
アギヤツプは例えばSiO2そのものよりも比誘電
率が小さくなるのでSiO2等の絶縁層形成に伴な
うゲート容量増加を抑制するものである。 As shown in FIG. 1, an n-type GaAs active layer 3 with a recess 10 provided on a GaAs substrate 2, and a T-type gate 1 made of aluminum on the n-type GaAs active layer 3.
2, and an insulating layer 16 made of SiO 2 by CVD method
is provided. n-type GaAs active layer 3 surface and T
A protective film 23 made of Si 3 N 4 is formed on the surface of the mold gate 12 by a CVD method.
Further, a space (air gap) 17 is formed below the T-shaped gate 12 in areas other than the channel portion. Since this air gap has a dielectric constant lower than that of SiO 2 itself, for example, it suppresses an increase in gate capacitance due to the formation of an insulating layer of SiO 2 or the like.
以下、本発明に係るＴ型ゲートを有するFET
の製造方法を第２Ａ図から第２Ｃ図及び第１図を
用いて説明する。 Below, FET having a T-type gate according to the present invention
The manufacturing method will be explained using FIGS. 2A to 2C and FIG. 1.
第２Ａ図に示すようにGaAs基板２上にｎ型
GaAs活性層３を形成し、次にこの第１及び第２
のレジスト層４，５を形成する。レジスト層５の
感度はレジスト層４の感度より高いものを用い
る。 As shown in Figure 2A, an n-type
A GaAs active layer 3 is formed, and then this first and second
resist layers 4 and 5 are formed. The sensitivity of the resist layer 5 is higher than that of the resist layer 4.
レジスト層４，５を形成した後、電子ビームに
より該レジスト層４，５を露光し現像する。その
後残存したレジスト層４をマスクとしてウエツト
エツチングによりリセス１０を形成する。第２Ａ
図のレジスト層４，５は現像後の残存レジスト層
である。 After forming the resist layers 4 and 5, the resist layers 4 and 5 are exposed to an electron beam and developed. Thereafter, a recess 10 is formed by wet etching using the remaining resist layer 4 as a mask. 2nd A
Resist layers 4 and 5 in the figure are resist layers remaining after development.
次に第２Ｂ図に示すように、レジスト層４及び
５をマスクとして真空蒸着法によりアルミニウム
１１を蒸着させる。 Next, as shown in FIG. 2B, aluminum 11 is deposited by vacuum deposition using the resist layers 4 and 5 as masks.
次に第２Ｃ図に示すようにリフトオフにより１
部のアルミニウム１１、レジスト層４，５を除去
しアルミニウムからなるＴ型ゲート電極１２を形
成する。Ｔ型ゲート電極１２とｎ型GaAs活性層
３との間には空間（エアギヤツプ）１５が形成さ
れる。 Next, as shown in Figure 2C, 1
The aluminum 11 and the resist layers 4 and 5 are removed to form a T-shaped gate electrode 12 made of aluminum. A space (air gap) 15 is formed between the T-type gate electrode 12 and the n-type GaAs active layer 3.
次に第１図に示すように減圧CVD法により窒
化シリコン層（Si3N4層）２３をｎ型活性層及び
Ｔ型ゲート電極１２の表面に約数100Åの厚さに
形成する。その後、例えば常圧CVD法により二
酸化シリコン層（SiO2層）１６を形成する。該
SiO2層１６の形成は常圧のCVD法によつて行な
われているため減圧CVD法に比しSiO2の形成の
ための平均自由工程が小さくなるため第２Ｃ図の
空間１５にSiO2が深く入り込まずゲート電極１
２下のSiO2界面２２迄しかSiO2の成長がなされ
ず空間１７が形成される。 Next, as shown in FIG. 1, a silicon nitride layer (Si 3 N 4 layer) 23 is formed to a thickness of about 100 Å on the surfaces of the n-type active layer and the T-type gate electrode 12 by low-pressure CVD. Thereafter, a silicon dioxide layer (SiO 2 layer) 16 is formed by, for example, atmospheric pressure CVD. Applicable
Since the formation of the SiO 2 layer 16 is carried out by the normal pressure CVD method, the mean free path for forming SiO 2 is smaller compared to the reduced pressure CVD method, so that SiO 2 is not deposited in the space 15 in FIG. 2C. Gate electrode 1 without going deep
SiO 2 grows only up to the SiO 2 interface 22 below 2, and a space 17 is formed.
このようにしてチヤネル部を除いたＴ型ゲート
電極と基板との間に空間を設けたFETが形成さ
れる。 In this way, an FET is formed in which a space is provided between the T-shaped gate electrode and the substrate excluding the channel portion.
第３Ａ図から第３Ｃ図は本発明をGaAsT型ゲ
ートMESFETに用いた場合の製造方法を説明す
るための工程断面図である。 FIGS. 3A to 3C are process cross-sectional views for explaining a manufacturing method when the present invention is used in a GaAsT type gate MESFET.
第３Ａ図に示すように、GaAs基板２上にリセ
ス１０を設けたｎ型GaAs活性層３を形成し、例
えばAu／AuGeからなるソース電極１３とドレ
イン電極１４を形成し、次に、ソース電極１３と
ドレイン電極１４との間にＴ型ゲート２を形成す
る。 As shown in FIG. 3A, an n-type GaAs active layer 3 with a recess 10 is formed on a GaAs substrate 2, a source electrode 13 and a drain electrode 14 made of, for example, Au/AuGe are formed, and then a source electrode 13 and a drain electrode 14 are formed. A T-shaped gate 2 is formed between the drain electrode 13 and the drain electrode 14.
次に第３Ｂ図に示すように、常圧CVD法によ
つてSiO2層１６を形成する。この工程によつて
Ｔ型ゲートと基板間に本発明特有の空間（エアギ
ヤツプ）１７が形成される。このSiO2層１６の
形成前に第１図で説明したように例えばSi3N4層
２３を減圧CVD法で形成してもよい。その後
SiO2層１６にコンタクトホール１８を形成し例
えばAu／Pt／Tiからなる配線１９を設けGaAsT
型ゲートMESFETが完成する。 Next, as shown in FIG. 3B, a SiO 2 layer 16 is formed by atmospheric pressure CVD. Through this step, a space (air gap) 17 unique to the present invention is formed between the T-shaped gate and the substrate. Before forming this SiO 2 layer 16, for example, a Si 3 N 4 layer 23 may be formed by low pressure CVD as explained in FIG. 1. after that
A contact hole 18 is formed in the SiO 2 layer 16, and a wiring 19 made of, for example, Au/Pt/Ti is formed in the GaAsT layer 16.
Type gate MESFET is completed.
以上説明したように、本発明によればFETに
おけるＴ型ゲートと基板間に空間を設けることに
よつて絶縁層形成に伴なうゲート容量の増加を約
１／４に低減し得る。
As explained above, according to the present invention, by providing a space between the T-type gate and the substrate in the FET, the increase in gate capacitance caused by the formation of the insulating layer can be reduced to about 1/4.
第１図は本発明の一実施例を示す断面図であ
り、第２Ａ図から第２Ｃ図は第１図に示した実施
例の製造方法を説明するための工程断面図であ
り、第３Ａ図から第３Ｃ図は本発明をGaAsT型
ゲートMESFETに用いた場合の製造方法を説明
するための工程断面図であり、第４図は従来の技
術を説明するための断面図である。
２……GaAs基板、３……ｎ型GaAs活性層、
４……第１のレジスト層、５……第２のレジスト
層、１０……リセス、１１……アルミニウム、１
２……Ｔ型ゲート、１３……ソース電極、１４…
…ドレイン電極、１５……空間、１６……絶縁層
（SiO2層）、１７……空間、１８……コンタクト
ホール、１９……配線、２３……保護膜（Si3N4
層）。
FIG. 1 is a sectional view showing one embodiment of the present invention, FIGS. 2A to 2C are process sectional views for explaining the manufacturing method of the embodiment shown in FIG. 3C are process cross-sectional views for explaining a manufacturing method when the present invention is used in a GaAsT gate MESFET, and FIG. 4 is a cross-sectional view for explaining a conventional technique. 2...GaAs substrate, 3...n-type GaAs active layer,
4... First resist layer, 5... Second resist layer, 10... Recess, 11... Aluminum, 1
2...T-type gate, 13...source electrode, 14...
... Drain electrode, 15 ... Space, 16 ... Insulating layer (SiO 2 layer), 17 ... Space, 18 ... Contact hole, 19 ... Wiring, 23 ... Protective film (Si 3 N 4
layer).
Claims (1)
断面形状Ｔ型ゲート電極を含んでなる半導体装置
において、 該電界効果トランジスタのチヤネル部以外の該
Ｔ型ゲート電極と該基板との間に空間を設けたこ
とを特徴とする半導体装置。[Scope of Claims] 1. A semiconductor device comprising a T-shaped gate electrode with a cross section of a field effect transistor formed on a substrate, wherein the T-shaped gate electrode other than the channel portion of the field effect transistor and the substrate A semiconductor device characterized in that a space is provided between the semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60030161A JPS61190985A (en) | 1985-02-20 | 1985-02-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60030161A JPS61190985A (en) | 1985-02-20 | 1985-02-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61190985A JPS61190985A (en) | 1986-08-25 |
| JPH0228255B2 true JPH0228255B2 (en) | 1990-06-22 |
Family
ID=12296030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60030161A Granted JPS61190985A (en) | 1985-02-20 | 1985-02-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61190985A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4700462A (en) * | 1986-10-08 | 1987-10-20 | Hughes Aircraft Company | Process for making a T-gated transistor |
| JPH02126628A (en) * | 1988-11-07 | 1990-05-15 | Canon Inc | Alignment device and its alignment method |
| US5139968A (en) * | 1989-03-03 | 1992-08-18 | Mitsubishi Denki Kabushiki Kaisha | Method of producing a t-shaped gate electrode |
| JP3093487B2 (en) * | 1992-10-28 | 2000-10-03 | 松下電子工業株式会社 | Semiconductor device and manufacturing method thereof |
| JP3170141B2 (en) * | 1993-07-27 | 2001-05-28 | 株式会社東芝 | Semiconductor device |
| JP2000138237A (en) * | 1998-11-02 | 2000-05-16 | Nec Corp | Semiconductor device having photosensitive organic film and method of manufacturing the same |
| KR100574911B1 (en) * | 1999-01-18 | 2006-04-28 | 삼성전자주식회사 | Method for forming conductive wiring layer of semiconductor device |
-
1985
- 1985-02-20 JP JP60030161A patent/JPS61190985A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61190985A (en) | 1986-08-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |