JPH0239863B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the structure of a vertical transistor.

Transistors also have a monolithic structure, and it has become common for multiple transistors to be mounted on a semiconductor substrate at the same time. In this case, of course, the vertical transistor has better characteristics than the horizontal transistor because the emitter-base junction does not appear on the semiconductor surface. However, because of the structure of monolithic vertical transistors, a part of the collector region is exposed on the semiconductor surface, when used at a relatively high voltage, an inversion layer is formed on the surface of the base region between this region and the emitter region. This has the disadvantage that leakage current can cause malfunction of the circuit.

FIG. 1 is a sectional view of a vertical pnp transistor having a conventional structure, and the drawbacks mentioned above will be explained in detail below with reference to this diagram. Since the manufacturing process of this transistor is well known, it will be briefly explained. An N-type first buried layer (layer resistance ~
After forming 20Ω/□) 2, a P-type second buried layer (layer resistance ~200Ω/
□) After forming 3, grow an N-type epitaxial layer 4 (specific resistance 1 to 20 Ωcm, thickness 10 to 20 μm). By forming a cylindrical or rectangular cylindrical P-type diffusion region 5 so as to reach the second buried layer 3 from the surface, one division 4 ₁ is created in the N-type epitaxial layer 4 . This partition 4 ₁ is the substrate 1
Both are completely separate. This is one unit of the vertical pnp transistor, and the diffusion region 5 and second buried layer 3 are integrally connected to form the collector region of the transistor. N-type region 4 surrounded by this region
₁ is the base area. Thereafter, a P type emitter region 6 and an N ⁺ type base electrode 7 are formed by a well-known method,
Aluminum wirings 9, 10, and 11 are provided in the emitter region 6, base electrode 7, and collector region 5, respectively. In the PNP transistor formed in this manner, a parasitic MOS effect may occur between the emitter region 6 and the collector region portion ₅₁ adjacent thereto. Even if there is no gate on the insulating thin film 8, a current flows between the collector and the emitter due to the influence of some charge on the thin film ₈ , depending on the thin film formation conditions, the surface impurity concentration of the base region 41, etc. Furthermore, although the emitter region 6 and the collector region portion 5 ₂ facing each other via the base electrode are separated by an n-type region, if the spacing is close in some cases, a small leakage current may flow as a lateral transistor.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a vertical transistor that operates stably even when used at a relatively high collector voltage.

In the present invention, one p-type region 12 is newly provided between the emitter region 6 and the base electrode 7, and the aluminum wiring (other metal may be used) of the emitter electrode 9 is extended to connect it adjacent to the emitter electrode 9. It is characterized in that the insulating thin film 8 on a part of the surface of the n-type region 4 ₁ in the range up to the collector region 5 ₁ and the p-type region 12 is completely covered with a metal having the same potential as the emitter region.

The present invention will be explained in detail below with reference to the drawings. FIG. 2 is a sectional view of a transistor according to an embodiment of the present invention, which corresponds to a conventional structure. Identical parts are designated by the same reference numerals as in FIG. The process of creating one section ₄₁ in the N-type epitaxial layer 4 is the same. However, a p-type region 12 is separately provided between the base electrode 7 and the emitter electrode 6. Although this region is not shown in the cross-sectional view of FIG. 2, it is connected to the adjacent collector region portion ₅₁ within the main surface of the epitaxial layer 4 facing the semiconductor substrate. This connection may optionally be annular or angular with the emitter region 6 as its center. Further, the electrode of the emitter region 6 has the shape of an extraction electrode 13, and is insulated over the entire surface of a region that is surrounded by the P-type region 12 and the collector region portion ₅₁ , and further divides the section ₄₁ in the epitaxial layer. Cover the membrane 8. This structure provides a MOS transistor structure in which the emitter region 6 is the source, and the collector region ₅₁ and the p-type region 12 are the drain. Here, the drain voltage becomes the voltage applied to the collector wiring 11 of this transistor. However, since the metal film of the emitter extraction electrode 13 corresponding to the MOS gate has the same potential as the drain, it does not operate as a MOS transistor at all, and therefore the parasitic MOS effect of the conventional structure does not occur.

As is clear from the above description, even when a high collector voltage is applied to the vertical transistor according to the present invention, leakage current between the collector region ₅₁ and the emitter does not occur except due to manufacturing defects, and mobile ions from the outside do not occur. Or it is completely unaffected by electromagnetic fields from other sources. Further, almost no current flows between the collector region 5 ₂ and the emitter as a lateral transistor. Therefore, it can operate stably even at high temperatures when a relatively high voltage is applied. Emitsuta・
Since there is a highly concentrated P-type diffusion region between the base terminals, there is also the advantage that the breakdown voltage against static electricity is increased. Although the present invention has been described with respect to a pnp transistor as an example, it goes without saying that it can also be applied to an npn transistor.

[Brief explanation of drawings]

FIG. 1 is a schematic sectional view of a conventional monolithic vertical PNP transistor, and FIG. 2 is a schematic sectional view of a vertical transistor showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type first buried layer, 3... P-type second buried layer, 4... N-type epitaxial layer, 4 ₁ ... Base region, 5... P P-type diffusion region, 5 ₁ , 5 ₂ ...P-type diffusion region, 6...
Emitter region, 7... Base electrode, 8... Insulating thin film, 9, 10, 11... Electrode wiring, 12... P-type diffusion region, 13... Emitter extraction electrode.

Claims (1)

[Claims] 1 The buried layer of the first conductivity type separated from the semiconductor substrate is located between the semiconductor substrate of the first conductivity type and the epitaxial layer of the second conductivity type formed on the substrate. The buried layer is formed such that its peripheral end overlaps with the cylindrical or rectangular cylindrical region of the first conductivity type formed perpendicularly from the surface of the epitaxial layer, so that the buried layer becomes integrated with the region. constitutes the collector region of the transistor, and the part of the epitaxial layer separated by this collector region is used as a base region, and there is a substantial gap between the emitter region formed in the base region and the buried layer. In the semiconductor device having a vertical transistor having a transistor function, the first region is shallower than the cylindrical or rectangular cylindrical region.
a conductive type additional region is formed in a part of the base region so as to cooperate with a part of the cylindrical or rectangular cylindrical region to surround the emitter region in a planar manner;
A base electrode for the base region is formed on the opposite side of the additional region from the emitter region, and an extraction electrode connected to the emitter electrode for the emitter region is formed on the additional region and the cylindrical or rectangular cylindrical region. 1. A semiconductor device characterized in that an insulating film is formed so as to cover the entire surface of an insulating film on a base region surrounded by a part of the base region.