JPH088262B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device, and more specifically, to a semiconductor in which another conductivity type (N type) epitaxial layer is grown on one conductivity type (for example, P type) substrate. The present invention relates to a semiconductor device such as a linear IC in which a vertical transistor (PNP transistor) having a triple diffusion structure collector of one conductivity type is incorporated in a substrate.

[Conventional technology]

Some transistors incorporated in a semiconductor device such as a linear IC have a triple diffusion structure in which the control of the base width is easy and the frequency characteristics are good.

A conventional example of a semiconductor device incorporating the vertical PNP transistor having the triple diffusion structure will be described with reference to FIGS.

In the figure, (1) is a semiconductor substrate in which an N ^- type epitaxial layer (3) is grown on a P-type substrate (2). (4) is an N ⁺ type buried layer formed between the substrate (2) and the epitaxial layer (3) of the semiconductor substrate (1), and (5) is a buried layer (4) of the epitaxial layer (3). ) P ⁺ type buried layer formed on the
(6) is a P-type collector region formed by diffusing impurities on the buried layer (5) of the epitaxial layer (3), and (7) is formed by diffusing impurities inside the collector region (6). An N-type base region (8) is a P-type emitter region formed by diffusing impurities in the base region (7).
(9) is a vertical PNP transistor (1 consisting of the collector region (6), the base region (7) and the emitter region (8)
0) P-type isolation region formed on the outer periphery of
Reference numeral (11) is an N ⁺ type parasitic stopper region formed in a portion surrounding the transistor (10) inside the isolation region (9), and a collector region (6) is formed by interposing this high concentration layer, The formation of a parasitic transistor of PNP structure consisting of the epitaxial layer (3) and the isolation region (9) is suppressed. (12) is an oxide insulating film formed on the surface of the semiconductor substrate (1), (13)
(14) shows a base electrode (7) and an emitter region (8) of the oxide insulating film (12), which has a window opened and a base electrode and an emitter electrode formed by depositing Al on the opening ( Reference numeral 15) is a bias electrode which is formed by opening a portion of the oxide insulating film (12) corresponding to the collector region (6) and the parasitic stopper region (11), and is formed by Al vapor deposition over both openings. is there.

The bias electrode (15) will be specifically described.
The parasitic stopper region (11) is bias-connected to the collector region (6) having a high potential with respect to the potential of the P-type substrate (2), that is, the P-type isolation region (9),
It is pulled up to the same high potential as the collector region (6). Higher potential is preferable for the parasitic stopper region (11),
The emitter region (8) is more effective. However, the problem with the parasitic transistor effect is that the vertical PNP
Since the transistor (10) is ON, the potentials of the emitter region (8) and the collector region (6) are similar, and even if the collector region (6) is connected, there is not much difference in effect. Absent. As shown in FIG. 5, the electrical connection between the parasitic stopper region (11) and the collector region (6) is made by using the oxide insulating film (12) (not shown in FIG. 5) on the surface of the semiconductor substrate (1). A junction portion (a) (hatched portion in the figure) is formed in a portion corresponding to the collector region (6), while a bias electrode (15) is formed in a portion near the junction portion (a) corresponding to the parasitic stopper region (11). ) Is formed and a bias electrode (15) is deposited by Al vapor deposition or the like across both the joints (a) and (b). .

[Problems to be Solved by the Invention]

In the semiconductor device described above, a high-concentration parasitic stopper region (11) is provided on the outer periphery of the transistor (10) inside the isolation region (9) in order to suppress the formation of the parasitic transistor as much as possible. . However,
The junction portion (b) of the parasitic stopper region (11) electrically connected through the junction portion (a) of the collector region (6) is located near the junction portion (a), and the junction area is Since it was small and was provided only in a part of the parasitic stopper region (11), there were the following problems. That is, as shown in FIG. 5, the farthest portion (p) farthest from the junction portion (b) with the bias electrode (15) in the parasitic stopper region (11).
Then, due to the resistance of the parasitic stopper region (11) itself, a potential difference is generated between the junction portion (a) and the parasitic transistor, and a leakage current easily flows through the substrate (2). There was a problem that there was room for improvement.

This point will be described in more detail. Farthest part (P)
The equivalent circuit of this structure in the vicinity of is the original PNP transistor (10) having the base electrode (13), the emitter electrode (14) and the collector electrode (15), and the base region (7) of the original PNP transistor (10). And an NPN transistor (Q1) having a collector region (5 and 6) as a base and a buried layer (4), an epitaxial layer (3) and a parasitic stopper region (11) as a collector, and a collector region (5 and 6). As shown in FIG. 7, a PNP transistor Q2 having an emitter as an emitter, a buried layer 4, an epitaxial layer 3 and a parasitic stopper region (11) as a base, and a substrate (2) and an isolation region (9) as a collector. It is composed.

Here, the resistance r represents the resistance from the junction (b) of the bias electrode (15) with the parasitic stopper region (11) to the farthest portion (P).

Here, when the transistor (10) is saturated, that is, when the emitter electrode (14) has a high potential (for example, power supply voltage) and the base electrode (13) has a low potential, the collector electrode (15)
Becomes a high potential, the transistor (Q1) turns on, the base potential of the transistor Q2 is lowered, and a current flows through Q2.

Therefore, the current becomes a leak current from the collector of the transistor (10) to the substrate (2). In order to reduce this leak current, the hFE of the parasitic transistor (Q2) is made small and the high-concentration N-type buried layer (4) and parasitic stopper region (11) are connected to the transistor (1
0) is provided so as to surround the collector region (6) and the parasitic stopper region (11) (transistor (Q2)
Short the emitter and base of the with the bias electrode (15). However, a resistance r occurs at a portion far from the junction (b) between the bias electrode (15) and the parasitic stopper region (11), and the transistor Q2 cannot be completely suppressed.

Therefore, the present invention has been proposed in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of suppressing the formation of a parasitic transistor by a simple means.

[Means for solving the problem]

The technical means for achieving the above object in the present invention is an island formed by surrounding a part of a semiconductor substrate having another conductivity type epitaxial layer grown on one conductivity type substrate with one conductivity type isolation region. In the outer periphery of the triple diffusion structure transistor in which the one conductivity type collector region, the other conductivity type base region, and the one conductivity type emitter region are diffused and formed, the other conductivity type having a high concentration is formed inside the isolation region and surrounding the transistor. And a parasitic stopper region for suppressing the formation of a parasitic transistor is connected to the other conductive type buried layer at the bottom of the transistor, and the collector or emitter region and the parasitic stopper region have the same potential. That the junction of the bias electrode connected to the above with the parasitic stopper region is extended along the parasitic stopper region. It is a semiconductor device according to symptoms.

[Action]

In the semiconductor device according to the present invention, the junction between the bias electrode connecting the emitter region or the collector region and the parasitic stopper region to the same potential and the parasitic stopper region is extended along the parasitic stopper region. In each part of the parasitic stopper region including the farthest part farthest from the junction with the high potential electrode, the potential difference caused by the resistance of the parasitic stopper region with the junction with the high potential electrode is reduced. It is possible to prevent the leakage current from flowing, and it is possible to easily prevent the formation of the parasitic transistor.

〔Example〕

An embodiment of a semiconductor device according to the present invention will be described with reference to FIGS. 1 to 4.

In the semiconductor device of one embodiment shown in FIGS. 1 and 2, (21) is a semiconductor substrate, and a P-type substrate (2
2) An N ^- type epitaxial layer (23) is grown on it. (24) is an N ⁺ type buried layer formed between the substrate (22) and the epitaxial layer (23) of the semiconductor substrate (21), and (25) is a buried layer (24) of the epitaxial layer (23). ) A P ⁺ -type buried layer formed on the top surface, for example, 1 × 10 ¹⁷
It has an impurity concentration of atoms / cm ³ . Reference numeral (26) is a P-type collector region formed by diffusing impurities on the buried layer (25) of the epitaxial layer (23), for example, 1 × 10 ¹⁵ to 1 × 10 ^16.
It has an impurity concentration of atoms / cm ³ . (27) is an N-type base region formed by diffusing impurities in the collector region (26) and has an impurity concentration of, for example, 1 × 10 ¹⁷ atoms / cm ³ . Reference numeral (28) is a P-type emitter region formed by impurity diffusion in the base region (27), for example, 1 × 10 ²⁰ at
It has an impurity concentration of oms / cm ³ . (29) is the collector region (26), the base region (27) and the emitter region (28)
A vertical PNP transistor (30) made of a P-type isolation region formed on the outer periphery, and (31) is an N ⁺ type region formed inside the isolation region (29) surrounding the transistor (30). Of the collector region (26), the epitaxial layer (23) and the isolation region (29) by interposing a high concentration layer having an impurity concentration of, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ in the parasitic stopper region of )
It suppresses the formation of a PNP-structured parasitic transistor. (32) is an oxide insulating film formed on the surface of the semiconductor substrate (21), (33) and (34) are oxide insulating films (3
2) A region corresponding to the base region (27) and the emitter region (28) is opened, and a base electrode and an emitter electrode (35) formed by depositing Al on the junction are formed by an oxide insulating film (32 A region corresponding to the collector region (26) and the parasitic stopper region (31) of (1) is opened, and the bias electrode is formed by Al vapor deposition or the like across both junctions.

The feature of the present invention resides in the lead-out structure of the bias electrode (35) in the parasitic stopper region (31). That is, the parasitic stopper region (31) is bias-connected to the collector region (26) and pulled up to the same high potential as the collector region (26).
The electrical connection with the collector region (26) is
As shown in the figure, the oxide insulating film (3
2) A parasitic stopper region of the oxide insulating film (32) with respect to the junction (a) (hatched portion in the figure) formed in a part corresponding to the collector region (26) (not shown in FIG. 1). (3
The joint (c) (hatched portion in the figure) with the bias electrode (35) is formed over the entire circumference corresponding to 1), and both joints (a) and (c) are closed and both joints ( It is performed by depositing the bias electrode (35) by, for example, Al vapor deposition across a) and c).

As described above, the formation of the joint portion (c) over the entire circumference increases the joint portion area between the parasitic stopper region (31) and the bias electrode (35), and thus is most distant from the joint portion (a). In each part including the farthest part (p), the resistance of the parasitic stopper region (31) itself becomes as small as possible, the potential difference with the junction part (a) can be reduced, and the parasitic transistor is hard to be formed. Therefore, it becomes difficult for leakage current to flow through the substrate (22). According to the experiment result by the applicant, when the junction (c) with the bias electrode (35) is formed over the entire circumference of the parasitic stopper region (31), the farthest portion (p) from the junction (a) is obtained. The resistance value up to
While there was Ω, the present invention product decreased to about 25Ω,
As a result, the leakage current to the substrate (22) was 15 mA in the conventional product, but decreased to 0.1 mA in the product of the present invention.

As in the above-described embodiment, the high potential electrode is the collector electrode, and the parasitic stopper region (31) is connected to the collector region (2
When the bias potential is connected to 6) and the same potential is set, it is possible to adopt a structure like the modification shown in FIGS. 3 and 4. That is, as shown in the figure, the parasitic stopper region (31 ') is formed so as to be joined to the collector region (26) of the transistor (30), and the oxide insulating film (32) (see FIG. 2) is interposed. The bias electrode (35 ') can be applied over the entire circumference without using the parasitic stopper region (3
The outer dimensions of 1 ') can be reduced, and the distance from the joint (a) to the farthest portion (p), in other words, the resistance value is further reduced, and the leakage current to the substrate (22) is greatly reduced. At the same time, the area surrounded by the isolation region (29) can be reduced, and the degree of integration of the semiconductor device can be increased.

In the above embodiment, the junction between the parasitic stopper region and the bias electrode was formed over the entire circumference of the parasitic stopper region. However, the present invention is not limited to this, and is not necessarily the entire circumference. You may make it extend normally.

Further, the present invention is a PNP for an IC using a P-type substrate.
NP for ICs that use N-type substrates for type transistors
Of course, it is applicable to N-type transistors. Further, the parasitic stopper region is not limited to being connected to the collector region as shown in the drawing, and in the case of an N-type parasitic stopper region provided in the P-type isolation region, it is connected to the highest potential region. The control effect of the parasitic transistor is large.

If it is a P-type parasitic stopper region provided in the N-type isolation region, it may be connected to the lowest potential region.

〔The invention's effect〕

According to the semiconductor device of the present invention, the junction between the collector or emitter region of the transistor formed by triple diffusion and the bias electrode of the parasitic stopper region connected to the same potential by the bias electrode is extended along the parasitic stopper region. Therefore, the formation of the parasitic transistor can be suppressed as much as possible, and the leakage current can be significantly reduced, so that a high-quality semiconductor device having high reliability can be provided.

[Brief description of drawings]

1 is a plan view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is an enlarged sectional view taken along line AA of FIG. 1, and FIG.
FIG. 4 is a plan view showing a modification of the present invention, and FIG. 4 is B of FIG.
It is an expanded sectional view which follows the -B line. FIG. 5 is a plan view showing a conventional example of a semiconductor device, and FIG. 6 is an enlarged sectional view taken along the line CC of FIG. FIG. 7 is an equivalent circuit of the semiconductor device shown in FIGS. (21) …… Semiconductor substrate, (22) …… Substrate,
(23) …… Ebiaxial layer, (24) …… Embedded layer, (2
6) …… Collector area, (27) …… Base electrode, (28)
...... Emitter area, (29) …… Isolation area,
(30) ... transistor, (31) (31 ') ... parasitic stopper region, (35) (35') ... bias electrode, (c) ...
... Joint with the bias electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-51-139282 (JP, A) JP-A-61-51842 (JP, A) JP-A-2-36558 (JP, A)

Claims (1)

[Claims] 1. A collector region of one conductivity type and another conductivity type in an island formed by surrounding a part of a semiconductor substrate having an epitaxial layer of another conductivity type grown on a substrate of one conductivity type with an isolation region of one conductivity type. A parasite that suppresses the formation of a parasitic transistor in the outer periphery of a triple diffusion structure transistor in which a base region and an emitter region of one conductivity type are diffused and formed inside the isolation region and surrounding the transistor with a high concentration of another conductivity type. A stopper region is provided by being connected to another conductive type buried layer at the bottom of the transistor, and the parasitic stopper region of the bias electrode connecting the collector or emitter region and the parasitic stopper region to the same potential. A semiconductor device, characterized in that a junction portion with is extended along the parasitic stopper region.