JPH0242263B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a pulse width modulation method using feedback, and in particular to a pulse width modulation method that reduces the burden on a processing device in pulse width modulation by using hardware. It is related to the method.

[Technology background]

Conventionally, in personal computers, the audio cassette interface
Pulse width modulation methods are often used. In this pulse width modulation, the data to be transmitted is parallel-serial converted, the pulse width time is determined, and other calculations associated with the modulation are all performed by a program. The reason for this is that in pulse width modulation, the transmission speed changes depending on the output data to be transmitted, so it is difficult to determine the timing to perform this processing in terms of hardware.

For example, FIG. 1 shows a schematic configuration of a conventional pulse width modulation method, in which data sent in parallel on a data bus 1 is set in a register 2,
The program outputs this one bit at a time and converts it into serial data.The software calculates the pulse width time as described above, outputs the write pulse modulation wave, and converts the level using the level converter 3. After that, write to audio cassette 4,
It was generating a pulse width modulation waveform.

[Conventional technology and problems]

However, if all of the above processing, that is, interface processing, were to be performed within the processing device using software, a considerable amount of processing time would be consumed by the processing device, and other processing would have to be performed. The time I shouldn't have was eaten up,
This results in a decrease in the efficiency of the software or the processing efficiency of the processing device.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems of the pulse width modulation method according to the prior art. It is an object of the present invention to provide a pulse width modulation method using feedback that takes timing, performs parallel-serial conversion of data in hardware, and reduces processing time for interface processing of a processing device.

[Structure of the invention]

To achieve this objective, the pulse width modulation method using feedback in the present invention:
A data parallel-serial conversion circuit, a clock signal, and an output signal of the parallel-serial conversion circuit are input, and when the output signal of the parallel-serial conversion circuit is ``0'', it outputs ``0'', and the parallel-serial conversion circuit outputs ``0''. The output signal of is “1”
a flip-flop circuit whose output is inverted every time the clock signal falls; a first gate to which the output signal of the parallel-to-serial converter circuit and the output signal of the flip-flop circuit are input, and the logical product of these is output; a second gate circuit into which the output signal of the parallel-to-serial conversion circuit and the clock signal are input, and outputs the negation of the former and the AND of the latter;
A third gate circuit is provided to which the output signals of the first gate circuit and the second gate circuit are input, and the logical sum of these is output, and the output signal of the third gate circuit is converted from parallel to serial. It is characterized by providing feedback to the circuit and pulse width modulating the data output in synchronization with the data output.

[Embodiments of the invention]

An embodiment of the present invention will be described based on FIGS. 2 and 3.

FIG. 2 shows an embodiment of an apparatus for realizing the pulse width modulation method of the present invention, and FIG. 3 shows a timing diagram explaining the operation of the apparatus shown in FIG.

In FIG. 2, reference numeral 10 denotes a parallel-to-serial conversion circuit, which converts data sent in parallel on the data bus DB to its output side TD using control signals on control lines cl ₁ , cl ₂ , and cl ₃ . 11 is a JK flip-flop, 12 is an AND gate circuit, 13 is an AND gate circuit with one side having a negative input, 4 is an OR gate circuit, and 15 is a level converter. Clock pulses from a clock generator (not shown) are applied to a circuit comprising the flip-flop and the gate circuit forming a so-called modulation circuit.

In the pulse width modulation method of the present invention, a feedback circuit FB is input from the output side of the OR gate circuit 14 to the transmission clock input of the parallel-to-serial conversion circuit 10. As a result, the data to be transmitted is output at the above timing.

The operation of the apparatus shown in FIG. 2 constructed as above will be explained with reference to the timing diagram shown in FIG. 3.

Data bus on the input side of the parallel-to-serial conversion circuit 10
DB, for example, a parallel data bus consisting of 8 bits
An example will be taken in which data on DB ₀ to DB ₇ is converted to serial data by control signals on control lines cl ₁ to _{cl 3} . The data to be serially converted and output is 1, 0, 1, 0, 0, 0, as shown in Figure 3d.
Suppose that it is 1, 1, 0. Therefore, when data as shown in FIG. 3b is outputted to the output side of the TD of the parallel-to-serial conversion circuit 10 with changes such as 1, 0, 1, 0, 1, 0, the data output becomes JK. Since it is applied to the set input S of the flip-flop 11,
Every time a clock as shown in FIG. By generating an output that divides the clock frequency by 1/2 from the output side of the JK flip-flop 11 at the time of change, the output from the OR gate circuit 14 is converted to the parallel/serial converter circuit 1.
The signal is fed back to the TC terminal of 0, and pulse width modulated data as shown in FIG. 3c is output.

That is, as shown in FIG. 3b, the output TD of the parallel-to-serial conversion circuit 10 changes from H (indicating "1") to L (indicating "0"), but when it is H, the AND gate circuit 1
2 turns on and is L, the AND gate circuit 13
turns on. Therefore, when the clock is L, that is, when "0" is output, the clock is output as is from the AND gate circuit 13, and is transmitted to the level converter 15 via the OR gate circuit 14, or is fed back to the parallel-to-serial converter 10. be done.

When it is H, that is, when "1" is output, the AND gate circuit 12 is turned on, so
The output of the JK flip-flop 11 is output and transmitted to the OR gate circuit 14.

By the way, the output of this JK flip-flop 11 is inverted every time the clock falls when TD of the parallel-to-serial conversion circuit 10 is at H level, so an output is generated with the clock frequency divided by 1/2. Become. Therefore, in Figure 3b
When TD is at the H level, that is, "1", an output obtained by dividing the clock frequency by 1/2 is generated as shown in FIG. 3c.

In this way, from the OR gate circuit 14,
A pulse-modulated output shown in FIG. 3c is generated in accordance with the H and L of TD, that is, "1" and "0".

〔Effect of the invention〕

As described above, in the present invention, a data parallel-to-serial conversion circuit, a flip-flop circuit that divides the clock frequency by 1/2, and a flip-flop circuit that divides the clock frequency by 1/2 can be used. Hardware with a simple configuration, such as a first gate circuit to which the data output from the serial conversion circuit and the output of the flip-flop circuit are input, and a second gate circuit to which the data output from the parallel to serial conversion circuit and the clock are input. By providing the circuit, software processing for interface processing within the processing device can be omitted, and the burden on the processing device can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a pulse width modulation method according to the prior art, FIG. 2 is an embodiment of a device implementing the pulse width modulation method according to the present invention, and FIG. 3 is a timing diagram explaining the operation of the device shown in FIG. 2. , respectively. In the figure, 10 is a parallel-to-serial conversion circuit, 11 is a JK flip-flop, 12 is an AND gate circuit, 13 is an AND gate circuit with negative input, 14 is an OR gate circuit, 15 is a level converter, and DB ₀ to DB ₇ are data buses. , cl ₁ to _{cl 3} are control lines, and FB is a feedback circuit, respectively.

Claims (1)

[Claims] 1. A data parallel-to-serial conversion circuit; a clock signal and an output signal of the parallel-to-serial conversion circuit are input, and when the output signal of the parallel-to-serial conversion circuit is “0”, outputs “0”; and a flip-flop circuit whose output is inverted every time the clock signal falls when the output signal of the parallel-serial conversion circuit is "1"; the output signal of the parallel-serial conversion circuit and the output signal of the flip-flop circuit are inputted. a first gate circuit to which the output signal of the parallel-to-serial conversion circuit and a clock signal are input, and a second gate circuit to which the negation of the former and the logical product of the latter are output. and a third gate circuit is provided to which the output signals of the first gate circuit and the second gate circuit are input, and the logical sum of these is output; A pulse width modulation method using feedback, which is characterized by feeding back to a serial conversion circuit and pulse width modulating the data output in synchronization with the data output.