JPH0257377B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data input device for a logic circuit, and particularly to a data input device for a one-chip microcomputer.

In a one-chip microcomputer, for example, the circuit elements for configuring its arithmetic unit (CPU), memory, input/output unit, etc. are made into a single chip using well-known LSI technology.
Constructed on two semiconductor substrates. This input section is
Usually, the input signal is configured to be input as a binary signal. In this case, the logic threshold voltage at the input section is set to a fixed level of an appropriate value, such as a level for determining the signal level output from a transistor-transistor logic circuit.

However, in order to enable the microcomputer to be used for various purposes, the input section is configured to take various logic threshold voltages, so that the signals output from various signal generators can be used in various ways. It is desirable to be able to input the information. Also, in this case,
A microcomputer configured as an LSI is
It is preferable that the configuration is such that the number of external terminals is not increased.

Therefore, an object of the present invention is to enable an input signal supplied through one external input terminal to be discriminated by two or more types of logic threshold voltages;
Another object of the present invention is to provide a data input device for a logic circuit that can suppress an increase in the number of external terminals.

Hereinafter, the present invention will be explained in detail with reference to the embodiments shown in FIGS. 1 to 3.

FIG. 1 is a circuit block diagram of one embodiment of the present invention.

In the figure, D ₀ to D ₇ are external terminals for signal input of the LSI constituting the microcomputer.

The input terminal of _an input buffer _BP0 composed of inverter circuits _IV10 and _IV20 and the non-inverting input terminal of a comparator _CMP0 are connected to the external terminal D0.

The output terminal of the above input buffer BP ₀ is connected to the address bus via a switch S ₁₀ consisting of an insulated gate field effect transistor (MISFET).
Connected to line _l0 that constitutes BUS.

Similarly, the output terminal of the comparator CMP ₀ is constituted by a MISFET and is connected to the line l ₀ via a switch S ₂₀ .

The input terminal of _an input buffer _BP6 composed of inverter circuits _IV16 and _IV26 and the non-inverting input terminal of a comparator _CMP6 are connected to the external terminal D6. Above input buffer
The output terminals of BP ₆ and comparator CMP ₆ are connected to the data bus BUS via switches S ₁₆ and S ₂₆ , respectively.
The wires that make up the L ₆ are commonly connected.

The inverting input terminals of the comparators CMP ₀ to CMP ₆ are connected to an external terminal D ₇ .

The above external terminal D ₇ also has an inverter circuit.
Input buffer consisting of IV ₁₇ and IV ₂₇
The input terminal of BP ₇ is connected.

The output terminal of the input buffer BP ₇ is connected to the line L ₇ which constitutes the data bus BUS via the switch S ₁₇ .
It is connected to the.

The switches _S10 to _S17 connected to the output terminals of the input buffers _BP0 to _BP7 have their control terminals, ie, gate electrodes, commonly connected to the line _l8 .

Similarly, the above comparators CMP ₀ to CMP ₆
The switches S ₂₀ to S ₂₆ connected to the output terminals of the circuits have their control terminals commonly connected to the line l ₉ .

The lines l ₈ and l ₉ are connected to the output terminals of the decoder circuit DEC to which the output signal of the register RG is supplied.

The register RG has an input terminal connected to the address bus ABUS, a terminal W to which a data read control signal is supplied, and a terminal R to which a reset signal is supplied. The terminals W and R are supplied with the signals from a control circuit (not shown).

In this example, although not particularly limited,
The logic threshold voltages of the input buffers _BP0 to _BP7 are made to match the level for determining the signal level output from a known transistor-transistor logic (TTL) circuit.

In addition, the above input buffer BP ₀ to BP ₇
Each inverter circuit for configuring the
Driving MISFETQ ₁ and enhancement mode
Consists of MISFETQ ₂ . For an inverter circuit as shown, its logic threshold voltage can be changed by changing the relative sizes of the load MISFETQ ₁ and the drive MISFETQ ₂ .

Each of the comparators CMP ₀ to CMP ₆ has a configuration as shown in FIG. 3, for example.

In FIG. 3, the first stage differential amplifier circuit is configured by MISFETQ ₃ to Q ₇ ,
_MISFETQ8 to _Q12 constitute a second stage differential amplifier circuit. In the first stage differential amplifier circuit, although not particularly limited, MISFETQ ₇
is driven by clock pulse CP. As a result, the comparator of FIG. 3 is activated when clock pulse CP is applied.

In addition, in Figures 1 to 3, each
The MISFET is an n-channel type. MISFETs in depression mode like Q ₁ are similar to Q ₂
It is said to have a different symbol from an enhancement mode MISFET such as .

According to the embodiment of FIG. 1, the external terminals D ₀ to
The level of the input signal supplied to D ₇ is determined by the corresponding input buffer BP ₀ to BP ₇ , and the level of the input signal supplied to D 7 is determined by the corresponding input buffer BP ₀ to BP 7.
The levels of the input signals supplied to D ₀ to D ₆ of D ₇ are determined by corresponding comparators CMP ₀ to CMP ₆ , respectively.

The output signals of the input buffers BP ₀ to BP ₇ or the comparators CMP ₀ to CMP ₆ are output from the switches S ₁₀ to S ₁₇ or S ₂₀ to
_S26 is transferred to the internal data bus BUS under switch control according to the microcomputer program.

For example, if the output terminals of a TTL circuit or a circuit (not shown) having similar output characteristics are connected to the external terminals D ₀ to D ₇ , first, the output terminal of a TTL circuit or a circuit (not shown) having output characteristics similar to that is connected to the external terminals D 0 to D ₇ . A data signal is output from a memory or register (not shown) to an address bus ABUS.

Next, a read control signal is supplied to terminal W of register RG. As a result, the data on the address bus is read into the register RG. The decoder circuit DEC is the register RG above.
decodes the output signal of and causes the above line _l8 to go high level.

The high level signal on said line _l8 turns on the switches _S10 to _S17 , so that
The output signals of the input buffers _BP0 to _BP7 are applied to corresponding lines _l0 to _l7 of the data bus BUS.

The signal supplied to the data bus BUS is read into a register or memory (not shown).

Next, a reset signal is supplied to terminal R of the register RG. Accordingly, the decoder circuit
The signal supplied from the DEC to line _l8 is returned to a low level, and the switches _S10 to _S17 are turned off. By turning off the switches _S10 to _S17 , the output terminals of the input buffers _BP0 to _BP7 and the data bus BUS are electrically isolated. This allows the data bus BUS to be controlled by another circuit (not shown). comparator
The output signals of CMP ₀ to CMP ₆ are connected to the data bus BUS.
If the data is to be transferred to a high level, a data signal for setting the line _l9 to a high level may be similarly set in the register RG. In this case, an appropriate bias circuit is provided outside the LSI, and the voltage output from this bias circuit is supplied as a logic threshold voltage to the inverting input terminals of comparators CMP ₀ to CMP ₆ via external terminal D ₇ . It turns out.

Note that the non-inverting input terminals of the comparators CMP ₀ to CMP ₆ are supplied with not only binary signals but also analog signals output from an analog circuit such as a temperature detection circuit using a thermistor. be able to. The LSI microcomputer equipped with the input device shown in FIG. 1 can therefore be used in relatively many applications.

The input device of FIG. 1 requires fewer external terminals, as described above.

FIG. 4 is a circuit diagram of a reference example. In the figure, the external signal input terminal IP has multiple input buffers with different threshold voltages.
The input terminals of V _TH1 to V _THo are commonly connected, and address switches S ₁ to S _o are connected between the output terminals of each input buffer V _TH1 to V _THo and the data bus BUS inside the LSI. is connected. In this reference example, a desired one of the switches _S1 to _S0 is controlled in the same manner as in the previous embodiment. As a result, a signal whose level is determined based on a desired threshold voltage is transferred to the data bus BUS.

FIG. 5 is a circuit diagram of still another reference example, in which comparators CMP ₁ to CMP _o are used in place of input buffers V _TH1 to V _THo of FIG. 4.

According to the reference examples in Figures 4 and 5 above, LSI
There is no need to provide a circuit for forming a threshold voltage outside of the device.

As described above based on the embodiments shown in FIGS. 1 to 3, according to the present invention, the input signals to be discriminated based on the desired threshold voltage are
The input signal can be input to an LSI input pin (external terminal) and read for judgment using two or more types of judgment values, and the terminal for inputting judgment values can be shared with external terminals for other purposes. Therefore, the input pins of the LSI can be made multifunctional without increasing the number of external terminals (pins), and the LSI can be made smaller.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of a data input device for a logic circuit according to an embodiment, Fig. 2 is a circuit diagram of an inverter circuit, Fig. 3 is a circuit diagram of a comparator, and Fig. 4 is a configuration of a reference example. FIG. 5 is a diagram showing the configuration of another reference example. D ₀ ~ D ₇ , IP……Input pin, BP ₀ ~ BP ₇ , V _TH1 ~
V _THo ...Input inverter, S ₁ ~S _o ...Switch, BUS...LSI internal data bus, CMP ₀ ~
CMP _o ……Comparator.

Claims (1)

Claims: 1 first and second external terminals; a first input circuit having a predetermined logic threshold voltage and having an input coupled to said first external terminal to form an output to be supplied to a data bus; a second input circuit having a predetermined logic threshold voltage and having an input coupled to the second external terminal; a logic threshold voltage determined by the voltage supplied to the first external terminal; and an input circuit having a logic threshold voltage determined by the voltage supplied to the first external terminal; a third input circuit coupled to the second input circuit; and an output of the second input circuit provided between the outputs of the second and third input circuits and the data bus and whose operation is controlled by a control signal. or a selection means for supplying the output of the third input circuit to the data bus, a data input device for a logic circuit comprising at least the following: 2. The selection means comprises a switch element provided between the outputs of the second and third input circuits and the data bus, respectively, and switch-controlled by a control signal. A data input device for a logic circuit according to scope 1. 3. The logic according to claim 1 or 2, wherein the third input circuit comprises a comparator circuit that compares the voltage of the first external terminal and the input of the second external terminal. Circuit data input device. 4. The data input device for a logic circuit according to claim 1, wherein the first and second input circuits are comprised of inverter circuits. 5. According to any one of claims 1 to 4, the first to third input circuits and selection means constitute a data input device in a one-chip microcomputer. Data input device for the described logic circuit.