JPH028332B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a move instruction logical comparison instruction processing method, particularly an instruction processing method in a processing device that employs a one-cycle pipeline control method.
The present invention relates to a move instruction logical comparison instruction processing method that can efficiently perform interruption due to exception detection in a logical comparison instruction and correction of the end address and number of remaining bytes due to a mismatch.

[Conventional technology and problems]

Fig. 3 is a diagram showing a comparison between a 2-cycle pipeline and a 1-cycle pipeline, Fig. 4 is an example of a flow development pattern in a move instruction, and Fig. 5 explains problems related to the problems of the present invention. Here is a diagram for.

In a processing device that performs conventional pipeline control,
A two-cycle pipeline, as shown in FIG. 3A, in which an instruction is input once every two cycles, is often used. One flow in a two-cycle pipeline consists of a D stage for decoding instructions, an R stage for reading index bases, etc., an A stage for generating effective addresses, and stages B1 and B2 for searching buffers using generated addresses.
stage, an E1 stage and an E2 stage that execute operations using operand data, a CK stage that checks results, and a W stage that writes to a register.

For such a two-cycle pipeline,
In order to increase the density of the pipeline and improve its performance, a one-cycle pipeline is being considered in which an instruction can be input every cycle. As shown in Figure 3B, one flow of a one-cycle pipeline consists of a D stage for decoding an instruction, an A stage for generating an effective address, a T stage for address translation, and a B stage for searching a buffer. , E which performs an operation using operand data
stage, and a W stage for writing to the register. The present invention is directed to a processing device that employs this one-cycle pipeline control.

By the way, the so-called interruptible move (Move Long) instruction and logical comparison (Compare Logical Long) instruction that process a long number of bytes in one instruction are
Recently, the frequency of use in operating systems and the like has increased, and the processing speed of movement commands in particular has come to have a large impact on performance.
Therefore, in addition to expanding the flow with a normal fetch/store sequence as shown in Figure 4B, if the boundary conditions are good, an 8-byte fetch is executed twice as shown in Figure 4B. It is repeated several times, and then a 16-byte store is executed, making it possible to move 16 bytes in 3 flows, and the second
When the operand is short and the area of the first operand is filled with padding characters, it is considered to increase the speed by performing continuous store-only processing as shown in FIG. 4C.

In the above-mentioned move instructions and logical comparison instructions, when an exception to access occurs, the addresses and data lengths of the first and second operands that have been executed must be corrected and returned to the respective general-purpose registers. Similarly, when a mismatch is detected in a logical comparison instruction, it is necessary to interrupt processing at that byte and correct the address, etc. This process differs depending on the pipeline structure.

FIG. 5A shows a case where an access exception occurs in a two-cycle pipeline. In pipeline processing, it is common to issue an access request for the next process before the previous process is completed, and when an access exception is detected, the next flow is in progress. In contrast, 1 shown in Figure 5B
In the case of a cycle pipeline, three subsequent flows are in progress when an access exception is detected.

Similarly, when a mismatch is detected in a logical comparison instruction, in a two-cycle pipeline, the fifth
Two flows flow as shown in FIG. On the other hand,
In a one-cycle pipeline, four flows flow as shown in FIG. 5D.

In this way, compared to the conventional 2-cycle pipeline, in the 1-cycle pipeline, two extra flows flow, making correction of addresses and byte counts complicated and difficult to implement. There's a problem.

[Means for solving problems]

The present invention aims to solve the above-mentioned problems, and efficiently corrects the address and number of remaining bytes at the time of termination due to exception detection or mismatch in the processing of move or logical comparison instructions, even with one-cycle pipeline control. to provide a means of processing. Therefore, the move instruction logical comparison instruction processing method of the present invention uses two registers that respectively hold the first operand address and second operand address to access the storage device in the move instruction or logical comparison instruction, and It is equipped with two registers that hold the remaining data length of each operand to be processed, an adder that obtains the effective address for each process, and a subtracter that subtracts by the number of bytes to be moved or logically compared. A move instruction logical comparison instruction processing method in a processing device that performs addition and subtraction by the adder and the subtracter simultaneously under control, and generates the number of bytes to be next moved or logically compared from the result. a register indicating the number of bytes to be moved or logically compared per line;
A circuit that adds the number of bytes requested to access each time an access request is issued to the storage control unit corresponding to each operand, and subtracts the number of bytes upon successful completion, and a circuit that holds the output of the circuit and the bytes requested to access. The operand address and data length are corrected based on the byte counter, and the operand address and data length are corrected based on the byte counter.

[Effect]

In pipeline control, in order to determine the processing bytes or expansion pattern of the next flow, control is easier if the operand address or remaining byte length is updated as early as possible in the flow, for example, in the A stage. On the other hand, if an event occurs that interrupts processing midway through, and the operand address and remaining byte length are corrected,
It is easier to calculate the remaining byte length at the end of the flow, and the correction becomes complicated if it is updated at the beginning of the flow. The present invention maintains the number of bytes processed for each pipeline, updates the remaining byte length in the A stage, and calculates the difference between the number of bytes updated in the A stage and the number of correctly executed bytes for each operand. By calculating and holding each value, correction can be made based on this value if necessary. Therefore, even if the operand address and remaining byte length are updated at the beginning of the flow, if an event that interrupts processing occurs midway, it can be easily corrected.

〔Example〕

Hereinafter, embodiments will be described with reference to the drawings.

Figure 1 shows the configuration of one embodiment of the present invention, and Figure 2 shows the configuration of the first embodiment.
5 shows an operation time chart of a logical comparison instruction in the illustrated embodiment.

In Figure 1, 1 and 2 are working address registers, 3 is a base register, 4 is an index register, 5 is a displacement register, and 6 is an address for generating the effective address of an operand based on the contents of registers 1 to 5. 7 is an operand address register, 8 is a buffer, 9 is an operand word register, 10 is a register, 11 is an execution unit (E) that executes instructions.
unit), 12 represents a result register, and 13 represents a register file.

Further, 14 is an adder/subtractor that calculates the number of remaining bytes in the A stage, 15 is a register that holds the remaining number of bytes of the first operand, 16 is a register that holds the remaining number of bytes of the second operand, 1
7 is a register that holds the address to be processed by the first operand; 18 is a register to hold the address to be processed by the second operand; 19 is a length generator that determines the byte length to be processed; 20 is a register that holds the number of bytes to be processed for the first operand; 21 is a register that holds the number of bytes to be processed for the second operand; 22 to 2;
6 is a register that stores the number of bytes to be moved or logically compared for each pipeline; 27 is an adder/subtractor that calculates a correction value for the first operand; 28 is an adder/subtractor that calculates a correction value for the second operand; 2
9 is a byte counter with a correction value for the first operand, 30 is a byte counter with a correction value for the second operand, and 31 is a correction adder/subtracter that calculates the address and data length where processing has been interrupted or mismatched. .

In instruction processing, an effective address is calculated by the address generation circuit 6 in the A stage,
The operand address is stored in the operand address register 7. Address translation is performed based on this address, the operand is fetched, the operation is performed by execution unit 11, and the result is stored in the result register.

In the processing flow for the first operand, the operand address to be processed is stored in the register 17, and the number of bytes remaining for processing the first operand is set in the register 15. Similarly, in the second operand processing flow, the operand address to be processed is stored in the register 18,
The number of bytes remaining to process the second operand is set in register 16. As is well known, in long character movement and long character logical comparison instructions, the lengths of the first and second operands are not necessarily the same.

The length generator 19 determines the number of bytes to be processed for the next flow in accordance with each operand, and outputs the number of bytes to be processed to the register 20 or 21. In the subsequent processing of each operand, register 15
For the value 16 or 16, the value in register 20 or 21 is subtracted by adder/subtractor 14, and the number of remaining bytes is reset in register 15 or 16. Normally, the length generator 19 sets the number of bytes to be processed to 8 or 16 or a fraction thereof, according to the flow expansion conditions explained in FIG.

The number of bytes to be processed is stored in registers 22 to 26, corresponding to each pipeline, and is sequentially shifted to the next register at the end of each stage. .

The byte counter 29 is a counter that holds the difference between the number of bytes updated in the A stage and the number of correctly executed bytes for the first operand. Note that the width of this counter is determined by the length of the pipeline and the number of bytes accessed at one time. The adder/subtractor 27 adds the value of the byte counter 29 and the value of the register 20, adds the number of bytes each time an access is issued in the A stage, and subtracts the value of the register 26 when the process is correctly performed. By doing so, the counter value is decremented by the amount correctly executed in the W stage. In the logical comparison instruction, when a mismatch occurs, instead of subtracting the value of the register 26, a byte number indicating which byte the mismatch occurs is subtracted.

Similarly for the second operand, adder/subtractor 2
8, the calculations are performed sequentially and the results are held in the byte counter 30.

When an access exception or a mismatch is detected, the results of the operand address correction and the remaining byte length by the correction adder/subtractor 31 are used. That is, the first operand address is calculated from the contents of the register 17 by the byte counter 29.
It is found by subtracting the value of . Further, the remaining byte length of the first operand is determined by giving the value of the byte counter 29 to the contents of the register 15. Similarly, for the second operand address, byte counter 3 is calculated from the contents of register 18.
It is obtained by subtracting the value of 0. Also, the second
The remaining operand byte length is determined by adding the value of the byte counter 30 to the contents of the register 16.

FIG. 2 shows a time chart of an example of a processing operation using a logical comparison instruction. The start address of the first operand is a, its data length is l, and the start address of the second operand is b, and its data length is m.

In this example, the contents of both operands are compared in the E stage of the first operand, and the result is sent to the instruction control unit (not shown) in the W stage.
Therefore, the number of bytes processed correctly in that W stage can be found. In the example shown in FIG. 2, a mismatch is detected during the second comparison. When a mismatch is detected, an instruction is issued to stop operand access, and subtraction of the number of bytes processed is inhibited. Addition is performed each time because each operand address and remaining byte length are updated. Therefore, in the subsequent flow of correction, the byte counter (OP
1LC) 29 and byte counter (OP2LC)
30 indicates a non-zero value. If the execution is completed correctly, the values of these byte counters will indicate zero.

In the flow for performing correction, as described above, the second operand address is "OP2A-OP2LC", and the second
The remaining byte length of the operand is “OP2L+OP2
LC", the first operand address is "OP1A-OP
1LC", the remaining byte length of the first operand is "OP1
Each correction result is determined by ``L+OP1LC''.

When an access exception is detected in a move instruction or a logical comparison instruction, control is performed as follows. For example, when an access exception is detected in the second operand, the exception is stored using a flag, prohibiting subsequent subtraction in the W stage of the first operand, and instructing to stop operand access. If this is done, the subsequent processing will be similar to the processing described above.

〔Effect of the invention〕

As explained above, according to the present invention, even in one-cycle pipeline control, the correction of the operand address and the number of remaining bytes when an access exception is detected or a mismatch in a logical comparison instruction is detected. It becomes possible to perform this process easily and efficiently, and it becomes possible to perform efficient pipeline control.

[Brief explanation of drawings]

Figure 1 shows the configuration of one embodiment of the present invention, and Figure 2 shows the configuration of the first embodiment.
The operation time chart of the logical comparison instruction in the illustrated embodiment, FIG.
A diagram showing a comparison with a cycle pipeline, Figure 4 is an example of a flow development pattern in a movement instruction,
FIG. 5 shows a diagram for explaining problems related to the subject of the present invention. In the figure, 6 is an address generation circuit, 7 is an operand address register, 8 is a buffer, 9 is an operand word register, 11 is an execution unit, 12 is a result register, 13 is a register file, 14 is an adder/subtractor, and 15 to 18 are registers. , 19 is a length generator, 20 to 26 are registers, 27 and 28 are adders/subtractors, 29 and 30 are byte counters, and 31 is a correction adder/subtractor.

Claims (1)

[Claims] 1. Two registers that hold the first operand address and second operand address to access the storage device in a move instruction or logical comparison instruction, respectively, and two registers that hold the remaining data length of each operand to be processed. It is equipped with a register, an adder that obtains an effective address for each process, and a subtracter that subtracts by the number of bytes to be moved or logically compared, and by one-cycle pipeline control, the addition by the adder and the subtracter, A move instruction logical comparison instruction processing method in a processing device that performs subtraction simultaneously and generates the next number of bytes to be moved or logically compared from the result, and indicates the number of bytes to be moved or logically compared for each pipeline. register, the first operand and the second
A circuit that adds the number of bytes requested to access each time an access request is issued to the storage control unit corresponding to each operand, and subtracts the number of bytes upon successful completion, and a circuit that holds the output of the circuit and the bytes requested to access. 1. A move instruction logical comparison instruction processing method, comprising: a byte counter indicating a difference between the number of bytes and the number of normally completed bytes, and correcting each operand address and data length based on the byte counter.