JPH0318796B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a burst phase discrimination circuit that discriminates the phase state of a color burst signal whose phase is inverted every horizontal scanning period and which is included in a color video signal based on the PAL (Phase Alternation Line) system. .

The PAL color video signal E _P is given by the following equation.

E _P =Y+(B-Y)sin ωst ±(R-Y)cos ωst...(1) Here, Y is the luminance signal, B and R are the blue and red signals, and ωs is the color subcarrier ( The angular frequency of subcarrier) is approximately 2π [radian] × 4.43
[MHz]. The sign ± in equation (1) means a phase inversion for each horizontal scanning line, and the (RY) component of the carrier color signal has a phase difference of 180° from each other for each horizontal scanning line. It is transmitted by balanced modulation of a color subcarrier signal called cos ωst. Therefore, the color burst signal is required to have information for inverting the phase of the subcarrier of the (RY) component line by line on the image receiving side. Therefore, the color burst signal is switched line by line to a phase of ±135° around the B-Y axis, and the phase-inverted signal is sent out. On the image receiving side, the phase of the subcarrier of the (RY) component is inverted by a burst phase discrimination circuit that discriminates which phase of the color burst signal is within ±135 degrees from the B-Y axis. Normally, this is what is being done.

FIG. 1 is a block diagram showing a conventional example of a burst phase discrimination circuit. In Figure 1, a carrier color signal included in a PAL color video signal is transmitted to burst gate 1 along with a color burst signal.
is supplied to. Also, this burst gate 1
For example, a gate pulse consisting of the output of a gate pulse generator (not shown) configured to delay the horizontal synchronizing signal and output a pulse while the color burst signal is present is also supplied. burst gate 1
For example, it consists of an analog switch circuit that turns on and off in response to this gate pulse, and separates and extracts the color burst signal from the carrier color signal and outputs the PLL.
(Phase Locked Loop) Supply to circuit 2.
In the PLL circuit 2, the color burst signal and
The output of the VCO (voltage controlled oscillator) 3 is supplied to a synchronous detector 4, and a signal corresponding to the difference in frequency and phase between these two signals is output from the synchronous detector 4 and then passed through a low-pass filter 5 to the VCO 3.
is supplied as a control voltage. From this VCO 3, a subcarrier signal sin(ωst+90°)=cos ωst having a phase difference of 90° with respect to a signal sin ωst having an average phase of the color burst signal sin(ωst±135°) is obtained.

The output of the synchronous detector 4 is supplied to a detector 6. The detector 6 is also supplied with a burst gate signal and the output of a T-type flip-flop 7 whose clock input is supplied with the burst gate signal. The detector 6 is configured to generate a pulse when the output of the synchronous detector 4 and the output of the flip-flop 7 match in polarity while the burst gate signal is being output. These burst gate 1, subcarrier signal generator 2 and detector 6
A burst phase discrimination circuit 8 is constructed, and the pulse outputted from the detector 6 is supplied to the reset input terminal of the flip-flop 7 as an output of the burst phase discrimination circuit 8. The Q and output of flip-flop 7 are supplied to PAL switch 9. The PAL switch 9 includes, for example, a phase shifter that shifts the phase of the subcarrier signal cos ωst outputted from the PLL circuit 2 by 180 degrees, and the output of this phase shifter -cos ωst and the subcarrier signal cos by using the Q and output of the flip-flop 7. It is composed of a signal changeover switch circuit that selectively outputs either one of ωst. The output of the PAL switch 9 is supplied as a detection subcarrier signal to an RY demodulator 10 comprising a synchronous detector, a low-pass filter, and the like. The input terminal of the R-Y demodulator 10 has a carrier color signal separated by, for example, a carrier color signal separator (not shown).
A signal (RY) cos ωst is supplied.
This RY demodulator 10 outputs a (RY) signal.

In the above configuration, from the synchronous detector 4,
As shown in the figure, a pulse whose polarity is reversed every 1H (one horizontal scanning period) is output. On the other hand, the burst gate signal is a pulse signal consisting of positive pulses generated with a repetition period of 1H, as shown in FIG. almost match. Further, the output of the flip-flop 7 whose clock input terminal is supplied with the burst gate signal is inverted at the time when the burst gate signal is generated, as shown in FIG. Here, when the polarity of the output of the synchronous detector 4 and the output of the flip-flop 7 is reversed while the burst gate signal is being output,
It is assumed that connections are made between the phase shifter and changeover switch forming the PAL switch 9 so that the subcarrier signal inversion operation by the PAL switch 9 is performed normally. Then,
When the inverting operation of the subcarrier signal by the PAL switch 9 is reversed and erroneous demodulation is performed, the polarities of the output of the synchronous detector 4 and the output of the flip-flop 7 match and are detected during the period when the burst gate signal is output. A pulse is supplied from the circuit 6 to the reset input terminal of the flip-flop 7. As a result, the flip-flop 7 is reset and correct demodulation can be performed from now on.

However, in the conventional burst phase discrimination circuit as described above, the phase of the color burst signal is discriminated by the detection output obtained by synchronously detecting the color burst signal, so the circuit configuration becomes complicated and the PLL circuit 2 becomes complicated. The disadvantage is that the phase of the color burst signal cannot be discriminated until the phase lock state is reached, resulting in a slow response speed.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a burst phase discrimination circuit which has a simple configuration and is capable of responding at high speed.

The burst phase discrimination circuit according to the present invention provides a difference between the signal level of a signal obtained by adding the input and output of a signal delay means for delaying a carrier color signal and a color burst signal for a predetermined time, and the input and output of the signal delay means. The structure is such that the portion corresponding to the color burst signal in the signal corresponding to the comparison result with the signal level of the signal corresponding to the color burst signal is extracted and output as a phase discrimination signal.

Hereinafter, the present invention will be explained in detail with reference to FIGS. 3 to 5.

As shown in FIG. 3, in the burst phase discrimination circuit 8 according to the present invention, a PAL carrier color signal is supplied to a 1H delay circuit 11, an addition circuit 12, and a subtraction circuit 13. The 1H delay circuit 11 consists of, for example, a delay line with a signal delay time of 1H, and the PAL
Outputs a signal obtained by delaying the carrier color signal by 1H. The output of this 1H delay circuit 11 is the output of the adder circuit 1.
2 and the subtraction circuit 13. Addition circuit 12
A signal obtained by adding the input and output of the 1H delay circuit 11 is synthesized. Also, subtraction circuit 1
3, for example, from the carrier color signal to the 1H delay circuit 1
The output of 1 is subtracted, and a signal corresponding to the difference between the input and output of the 1H delay circuit 11 is synthesized. Each output of the addition circuit 12 and subtraction circuit 13 is supplied to a level comparison circuit 14. The level comparison circuit 14 compares the signal levels of each output of the addition circuit 12 and the subtraction circuit 13, and when the signal level of the output of the addition circuit 12 is higher than the signal level of the output of the subtraction circuit 13, the output becomes, for example, a high level. At other times, the output is, for example, at a low level. The output of the level comparison circuit 14 is supplied to one input terminal of a burst gate 15, which is, for example, an AND (logical product) gate. The other input terminal of the burst gate 15 is supplied with a burst gate signal. The pulse output from the burst gate 15 is supplied to the reset input terminal of the flip-flop 7 as a phase discrimination signal.

In the above configuration, along with the PAL carrier color signal
1H delay circuit 11, addition circuit 12 and subtraction circuit 1
Successive color burst signals supplied to 3
The phase during 4H is shown in FIGS. 4A to 4D. As is clear from Figures 4A to 4D, the color burst signal is switched to a phase of ±135° around the BY axis every 1H, and the phase-inverted signal is sent out. In addition, in order to prevent vertical stripe interference, a 1/4 line offset is adopted in which the phase of the subcarrier is shifted by 90° between two consecutive scanning lines in the same field, so the phase of the color burst signal is will be reversed every 2 hours. Therefore, the output of the addition circuit 12 that adds the PAL carrier color signal and the signal obtained by delaying this PAL carrier color signal by 1H, and the output of the subtraction circuit 13 that outputs a signal corresponding to the difference between these two signals. The signals corresponding to the color burst signals are alternately canceled every 1H, and the outputs of the addition circuit 12 and the subtraction circuit 13 become as shown in FIGS. 5A and 5B, respectively. Such an adding circuit 1
The portion corresponding to the color burst signal of the output of the level comparison circuit 14 which compares the signal levels of the respective outputs of the subtraction circuit 13 and the subtraction circuit 13 becomes high level every 2H.
Along with the output of the level comparison circuit 14, the burst gate 15, which is supplied with a burst gate signal consisting of positive pulses generated every 1H as shown in C in the same figure, outputs a positive pulse every 2H as shown in D in the same figure. This will be output as a phase discrimination signal. Therefore, the flip-flop 7 whose reset input terminal is supplied with the output of the burst gate 15
is reset every 2 hours. Also, the clock input terminal of this flip-flop 7 is connected to the clock input terminal C in the same figure.
Since a burst gate signal as shown in FIG. Figure E
It becomes as shown in.

Therefore, the flip-flop 7 is operated so as to normalize the operation of the PAL switch 9, which inverts the subcarrier signal according to the output of the flip-flop 7.
This means that a pulse as a phase discrimination signal can be supplied to the reset input terminal every 2H. Then, even if the inversion operation of the subcarrier signal by PAL switch 9 is reversed, the inversion operation of the subcarrier signal will be returned to normal within 2H.
- Correct demodulation is now performed in the Y demodulator 10.

In this way, the burst phase discrimination circuit according to the present invention calculates the signal obtained by adding the PAL carrier color signal accompanied by the color burst signal and the output of the delay means for delaying this PAL carrier color signal, and the difference between these two signals. Since the phase discrimination signal is generated every 2H according to the phase of the color burst signal while discriminating the phase of the color burst signal based on the corresponding signal, the response is fast with a simple configuration that does not include a synchronous detector etc. You will be able to do this. Further, according to the present invention, the phase of the color burst signal is discriminated by comparing the signal levels of the respective outputs of the adder circuit 12 and the subtracter circuit 13.
Compared to the case where the phase is discriminated by comparing the output level of either one of the output level of 2 and the subtraction circuit 13 with the reference level, the adverse effects such as fluctuations in the reference level due to temperature and changes over time are reduced, and the 1H
This means that the influence of signal delay time errors in the delay circuit 11 is small. In addition, since the 1H delay circuit 11, the addition circuit 12, and the subtraction circuit 13 can be used in common with a circuit for extracting red and blue difference signal components in the PAL color video signal in the PAL _D demodulation method, the 1H delay circuit 11 Since there is no need to separately provide the adder circuit 12 and the subtracter circuit 13, it is possible to expect the effect that the number of parts used in a video playback device or the like can be reduced.

In the above embodiment, the burst gate 15
Although the burst gate 15 is provided after the level comparison circuit 14, the burst gate 15 may be provided before the level comparison circuit 14, or may be provided before the 1H delay circuit 11. However, if the burst gate 15 is provided before the 1H delay circuit 11, the 1H delay circuit 11 etc. cannot be shared with the circuit for extracting the red and blue difference signal components in the PAL _D demodulation system. Further, in the above embodiment, the signal supplied to the clock input terminal of the flip-flop 7 is a burst gate signal, but the clock input terminal of the flip-flop 7 is supplied with a flyback pulse generated in the horizontal deflection coil during the retrace period. A pulse obtained by appropriately limiting the amplitude of the signal may be supplied. Furthermore, in the above embodiment, the phase of the subcarrier signal is inverted by supplying the output of the flip-flop 7 to the PAL switch 9, but when triggered instead of the output of the flip-flop 7, The output of the monostable multivibrator, which is in an inverted state, is switched to PAL switch 9.
The present invention can also be applied to cases where the In such a case, the monostable multivibrator may be triggered by the rising edge of the output pulse of the burst gate 15.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional burst phase discrimination circuit, FIG. 2 is a waveform diagram showing the operation of the circuit in FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the present invention. Figure 4 shows each period during consecutive 4H.
Vector diagram of color burst signal every 1H, 5th
The figure is a waveform diagram showing the operation of the circuit of FIG. 3. Explanation of symbols of main parts, 11...1H delay circuit,
12... Addition circuit, 13... Subtraction circuit, 14...
Level comparison circuit, 15...burst gate.

Claims (1)

[Claims] 1. A burst phase discrimination circuit for discriminating the phase state of a color burst signal in a PAL color video signal in which one of the carrier color signals and a color burst signal are phase-inverted every horizontal scanning period, the circuit comprising: a signal delay means for delaying the color burst signal for a predetermined time; a first signal synthesis means for synthesizing a signal obtained by adding the input and output of the signal delay means; and a difference between the input and output of the signal synthesis means. a second signal synthesizing means for synthesizing signals according to the level; and a level comparing means for comparing the levels between the outputs of the first and second signal synthesizing means and outputting a signal according to the comparison result, A burst phase discrimination circuit characterized in that a portion corresponding to the color burst signal in the output of the comparing means is extracted and outputted as a phase discrimination signal.