JPH0319733B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention periodically selects bits of a predetermined order from each bit of serial data according to a desired compression ratio, and processes the bits as compressed data. The present invention relates to a selection circuit used in cases.

[Conventional technology]

Such compression of serial data is used in various data processing. Conventionally, serial data is converted into parallel data and then sent to a processor such as a microprocessor (hereinafter referred to as CPU), where data is processed in a predetermined order. In addition to periodically selecting bits and editing them, in order to prevent data loss,
Synthesis processing is performed between bits, and predetermined data processing is performed based on these results.

[Problem that the invention seeks to solve]

However, in conventional methods, when the serial data provided is high-speed, high-speed calculations are required for compression processing by the CPU, and the amount of operating load required for this increases, reducing the amount of allowable load that can be allocated to other processing. Therefore, it is necessary to separately install a CPU, etc.
This generally causes the problem that the equipment becomes expensive.

[Means for solving problems]

In order to solve the above-mentioned problem, the present invention is constructed by the following means.

That is, means for generating a plurality of extraction pulses corresponding to a compression ratio for periodically extracting bits of a predetermined order from each bit in accordance with a desired compression ratio based on a clock pulse synchronized with each bit of the serial data; means for generating a plurality of sampling pulses corresponding to each extraction pulse for sampling bits to be synthesized from each bit at a timing different from the extraction pulse based on the clock pulse; and selection means for individually selecting each extraction pulse and the sampling pulse. , holding means for holding the bits to be synthesized from the respective bits until the synthesis is completed according to the sampling pulse selected by the selection means according to the synthesis control signal, and a synthesis unit for synthesizing the held output of the holding means and the serial data. and serial/parallel converting means for sequentially and serially holding the outputs of the synthesizing means in accordance with the extraction pulses selected by the selecting means and transmitting the held contents as parallel data.

[Effect]

Therefore, when the holding means is activated by the synthesis control signal, the synthesis bits from the serial data are held by the holding means until the synthesis is completed, and after this holding output and the serial data are combined, the serial and parallel bits are Since only the bits to be extracted by the conversion means are held sequentially and serially and sent out as parallel data, by giving this to the CPU, the CPU can immediately process the compressed data.

In addition, the order of extracted bits and synthesized bits can be determined freely by setting the selection status of the selection means.
The compression ratio can be arbitrarily selected, and the combining operation can also be stopped using the combining control signal.

〔Example〕

Hereinafter, details of the present invention will be explained with reference to figures showing examples.

Figure 1 is a block diagram, and Figure 2 is a timing chart showing the status of each part in Figure 1. In Figure 1, serial data DT(a) is given, and each bit of this is synchronized. Based on the clock pulse CLK, a pulse generator (hereinafter referred to as PG) 1 using a counter or memory etc. sorts each bit of the serial data DT(a) into a predetermined order according to a desired compression ratio. Extraction pulses P _l to _{P o} are generated for each compression ratio, and are synthesized from each bit of the serial data DT(a) at a timing different from these extraction pulses P _l to _{P o} . For sampling bits, sampling pulses OR _l -OR _o corresponding to each extraction pulse P _l -P _o are generated.

Also, PG1 is the sampling pulse OR _l ~
Reset pulses RS _l -R _o used to clear the contents of the bits held by _{OR o} are also generated in the same way as the sampling pulses OR _l -OR _o .

Each of these pulses P _l ~ P _o , OR _l ~ OR _o , RS _l ~
RS _o is individually selected or prevented from being sent out by selectors (hereinafter referred to as SEL) 2 to 4 controlled by control data DC, and the operating status of PG1 is also regulated by the same data DC. It has become something that is done.

On the other hand, the serial data DT(a) is stored in a D-type flip-flop circuit (hereinafter referred to as FFC) used as a holding means.
5 data input via SEL10 and selected by SEL3.
(b) is applied to the clock input CK, the bits of the serial data DT(a) are sampled and held by the FFC5, and are sent out from the output Q as the holding output (c). This is serial data by OR gate 6 as a synthesis means.
It is combined with DT (a), becomes a combined output (d), and is applied to a serial/parallel converter (hereinafter referred to as S/P) 7 such as a shift register.

Then, the extraction pulse (e) selected by SEL2 is given to the S/P7 as a shift pulse, and each bit of the composite output (d) is sequentially and serially transmitted from the first stage to the last stage of the S/P7. The content held in each stage is stored as parallel data in the CPU 8.
By periodically repeating the above operations, the serial data DT(a) becomes compressed data and is supplied to the CPU 8.

However, when the FFC5 is in the operating state and a synthesis operation is performed, the synthesis control signal SC is "L" (low level), and the reset pulse (g) selected by SEL4 via the OR gate 9 is applied to the FFC5. Since the bits to be synthesized are held by the FFC5 until the synthesis is completed,
The FFC5 is cleared by the reset pulse (g).

Fig. 2A shows the case where the compression ratio is set to 1/1. In this case, SEL2 selects the extraction pulse P _l according to the control data DC, SEL3 and SEL4 stop sending out, and Control signal SC is “H”
(high level), FFC5 maintains a clear state, and hold output (c) is cleared, so serial data DT(a) is output as is through OR gate 6.
(d) and output (d) according to the extraction pulse (e)
Each bit “1” to “12” indicates the contents of S/P7 (f)
As shown in FIG. 2, the data is held in the same order as the serial data DT(a), and a predetermined number of bits among these become serial and parallel data.

Figure 2B shows the case where the compression ratio is set to 1/2, and is the same as above except that extraction pulse P ₂ is selected by SEL2, and the bit of output (d) is changed according to extraction pulse (e). Only "1", "3"..."11" is S/
P7 is held, and these similarly become parallel data.

Figure 2C shows the case where the compression ratio is set to 2/3, and is the same as (A) and (B) except that extraction pulse P ₃ is selected by SEL2, and according to extraction pulse (e),
Output (d) bits “1”, “2”, “4”, “5” ~
Only "10" and "11" are held by the S/P7.

Figure 2D shows the case where the synthesis action is performed in (C), and in this case, SEL3 is the sampling pulse.
OR ₃ is selected, SEL4 selects reset pulse RS ₃ , and the composite control signal SC is "L", and FFC5 is set according to sampling pulse (b).
holds each bit “1” to “12” to “3” and “6” to “12” of the serial data DT(a), and performs sampling to clear the held contents according to the reset pulse (g). The holding output (c) is sent out only from the time when the pulse (b) occurs until the reset pulse (g) occurs, and these outputs are converted into serial data at the OR gate 6.
It is combined with the first extracted bit of DT (a), and each bit of the combined output (d) is "2", "3+4",
``5'', ``6+7'' to ``12+3'', and from these bits ``2'', ``3+4'' to ``9+10'', and ``11'' are sequentially and serially held by the S/P7 according to the extraction pulse (e). This prevents data loss and errors from occurring due to the removal of bits "3", "6" to "12".

Therefore, the CPU 8 does not need to perform compression processing and bit synthesis processing on the serial data DT.
Only the original data processing needs to be performed, reducing calculation speed and operating load, making it possible to use an inexpensive CPU 8, and also allowing it to be used for other required processing. becomes.

On the other hand, other data ODT is also given to SEL10, and if SEL10 is controlled by control data DC and other data ODT is selected, this can be changed.
The serial data DT is held by FFC5 in the same way as above and is combined with the serial data DT.
It becomes possible to freely combine predetermined bits in the data with any other data ODT, which is convenient for image processing and the like.

However, for SEL2 to SEL4, 10, a combination of gates, etc. may be used, a latch circuit or memory, etc. is used for FFC5, the sampling pulse has a pulse width that spans the holding period, and the latch circuit, memory, etc. applied to the enable terminal or chip select terminal or equivalent terminal, and
Generation of reset pulses RS _l to RS _o and SEL
4. It is the same even if OR gate 9 is omitted, and OR gate 9 is omitted.
Other OR circuits may be used as the gate 6,
It can also be used as a memory in the S/P7.

Further, the generation timing of each pulse P _l to P _o and PR _l to OR _o can be determined in various ways depending on the compression ratio and the order of the synthesized bits.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, when data processing is performed after compressing serial data, the CPU only needs to process the data, which reduces the operating load of the CPU and Since high-speed arithmetic processing is not required and the device can be configured at a low cost, it can provide remarkable effects in various applications where serial data is compressed and then fed to the CPU.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention; FIG. 1 is a block diagram, and FIG. 2 is a timing chart showing the status of each part in FIG. 1. 1...PG (pulse generator), 2-4...SEL (selector), 5...FFC (flip-flop circuit),
6, 9...OR gate, 7...S/P (serial to parallel converter), DT...serial data, CLK...clock pulse, SC...combined control signal.

Claims (1)

[Claims] 1. means for generating a plurality of extraction pulses corresponding to the compression ratio for periodically extracting bits of a predetermined order from each of the bits according to a desired compression ratio based on a clock pulse synchronized with each bit of the serial data; means for generating a plurality of sampling pulses corresponding to each of the extraction pulses for sampling a bit to be synthesized from each of the bits at a timing different from the extraction pulse based on a clock pulse; and means for individually selecting each of the extraction pulses and the sampling pulse. a selection means, a holding means for holding a bit to be synthesized from among the bits until the synthesis is completed according to a sampling pulse selected by the selection means according to a synthesis control signal, and a holding output of the holding means and the serial data. and a serial-to-parallel conversion means for sequentially and serially holding the output of the combining means in accordance with the extraction pulse selected by the selecting means and transmitting the held content as parallel data. Characteristic serial data selection circuit.