JPH0326478B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to a semiconductor memory device.
For example, the present invention relates to a technique effective for a semiconductor memory device that detects change timing of an external address signal to define internal operation timing and writes and reads multiple bits of storage information.

[Background technology]

For example, dynamic RAM (random access memory) is described in the May 14, 1979 issue of Mekkei Electronics magazine, pages 90 to 106, "Easy-to-use RAM for small-capacity systems." In addition to the x1 bit configuration, as the usage expands,
Dynamic RMAs have been developed that write/read data signals of multiple bits, such as 4.times.8 bits, in parallel. Furthermore, semiconductor memory devices that operate asynchronously by detecting changes in external address signals and controlling the timing of internal operations have been considered.

In this way, when reading multiple bits,
The inventor's research has revealed that the following problem occurs.

In other words, in order to drive a relatively large load,
A relatively large current flows through the data output buffer that sends out the read signal at the timing of its operation. Therefore, when transmitting data signals such as ×4 or ×8 bits, 4 to 8 output buffers operate simultaneously, which causes large noise (ground potential is high, (The power supply voltage becomes low). It has been discovered that when such noise occurs, the circuit that detects the change timing of the address signal is activated, which may cause the RAM to malfunction.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device in which malfunction of an address signal change detection circuit due to noise generated in a power supply line is prevented.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows. That is, by inhibiting the operation of the circuit that detects the change timing of the address signal at the operation timing of the data output buffer, malfunction thereof is prevented.

〔Example〕

FIG. 1 shows the internal configuration of a dynamic RAM integrated circuit (hereinafter referred to as IC) having a configuration of approximately 32K×9 bits.

In this embodiment, the memory array is divided into two parts, M-ARY1 and M-ARY2, although this is not particularly limited.

And each memory array M-ARY1, M-
In ARY2, nine complementary data line pairs are formed as one set, and are formed to extend vertically in the figure.

In other words, instead of configuring the memory array by dividing it into 9 blocks (mats), 9-bit data is divided into 9 blocks (mats) adjacent to each other in the same memory array.
One address is assigned to each pair of complementary data lines, and they are arranged in order in the horizontal direction in the figure. This was done because if there were nine mats, the mat configuration would be asymmetric on the semiconductor chip, and the layout would have many useless blank spaces. Further, in this embodiment, the reason why the number of bits is x9 is to write/read a data signal consisting of 8 signal bits and 1 redundant bit.

On the other hand, the row address selection line (word line) is
They are formed in common to the memory arrays M-ARY1 and M-ARY2 in the horizontal direction, and are sequentially arranged in the vertical direction in the figure.

The complementary data line pair is connected to the column switch C-
It is selectively connected to nine common complementary data line pairs CD1 and CD2 via SW1 and C-SW2. In the figure, the common complementary data line pair runs in the horizontal direction. This common complementary data line pair CD1, CD2
are connected to the input terminals of main amplifiers MA1 and MA2, respectively.

Sense amplifiers SA1 and SA2 receive minute read voltages on the complementary data line pair of the memory array,
It is brought into operation by the timing signal φpa and amplifies the complementary data line pair to a high level/low level in accordance with the read voltage.

The row address buffer R-ADB receives an m-bit address signal RAD from an external terminal and outputs internal complementary address signals a0 to am-1, 0 to m-.
1 (hereinafter referred to as a0 to am -1. The same applies to the drawings)
is formed and sent to the row address decoder R-DCR.

The row address decoder R-DCR selects one word line in accordance with the address signals a0 to am -1 in synchronization with the word line selection timing signal φx.

The column address buffer C-ADB receives an n-bit address signal CAD from an external terminal.
Internal complementary address signal a0~am-1, 0~n
-1 (hereinafter referred to as a0 to an . The same applies to the drawings)
to form a column address decoder C-DCR
Send to.

Column address decoder C-DCR forms a selection signal synchronized with data line selection timing signal φy in order to select nine complementary data line pairs according to the address signals a0 to an -1.

Column switches C-SW1 and C-SW2 receive the selection signal and connect the nine complementary data line pairs to the corresponding nine common complementary data line pairs.

In the figure, the complementary data line pair and the common complementary data line pair are represented by one line.

The input/output circuit I/O is composed of a main amplifier and data output buffer for reading, and a data input buffer for writing, and when reading, one of the main amplifiers that is activated
The data amplified by MA1 or MA2 is sent to the external terminal.
Send to DR. Furthermore, during a write operation, a write signal from the external terminal DW is supplied to the common complementary data line pair CD1, CD2. In the figure, this write signal path is omitted.

The internal control signal generation circuit TG receives two external control signals (chip select signal) and (write enable signal), and the address signals a0 to am-.
Edge trigger circuit EG receiving 1 and a0~an-1
In response to the address signal change detection signal φ formed by the address signal change detection signal φ, various timing signals necessary for memory operation are formed and sent. Above edge trigger circuit EG
is composed of an exclusive OR circuit that receives each address signal and its delayed signal, and an OR circuit that receives the output signals of these exclusive OR circuits.

The operation of the edge trigger circuit EG of this embodiment is inhibited by a timing signal φdk generated from an operation timing signal φop of a data output buffer among the input/output circuits I/O, as will be described later.

Figure 2 shows one side (left side) of Figure 1 above.
memory array (including redundant array) M-
A circuit diagram of a specific embodiment of the ARY1 side and its selection circuit is shown. In the following description, unless otherwise specified, the MOSFET is an n-channel MOSFET.

In the memory array M-ARY, a pair of rows thereof are shown as a representative, and a switch MOSFET Q1 is connected to a pair of complementary data lines D arranged in parallel.
The input/output nodes of the memory cells constituted by Q5 to Q18 and MOS capacitors are distributed and coupled with a predetermined regularity as shown in the figure.

The precharge circuit PC1, like MOSFETQ14 shown as a representative, has complementary data lines D,
It is composed of a switch MOSFET placed between D.

The sense amplifier SA consists of the representative p-channel MOSFETs Q7 and Q9 and the n-channel MOSFETs.
CMOS (complementary type) consisting of MOSFETQ6 and Q8
(MOS) latch circuit, and its pair of input/output nodes are coupled to the complementary data line D. The above latch circuit includes, but is not limited to, a parallel p-channel MOSFETQ12,
Power supply voltage Vcc is supplied through Q13, and circuit ground voltage Vss is supplied through parallel n-channel MOSFETs Q10 and Q11. These power switch MOSFETQ10, Q11 and
MOSFETs Q12 and Q13 are commonly used for sense amplifiers SA provided in other similar rows.

The gates of the MOSFETs Q10 and Q12 are as follows:
Complementary timing pulses φpa1 and pa1 that activate the sense amplifier SA are applied, and MOSFETQ
Complementary timing pulses φpa2, pa2 delayed from the above-mentioned timing pulses φpa1, pa1 are applied to the gates of Q11 and Q13. The reason for this is
When the sense amplifier SA is operated with a minute read voltage from the memory cell, the drop in the level of the data line is suppressed by a relatively small conductance.
This can be prevented by limiting the current using MOSFETs Q10 and Q12. After increasing the potential difference between the complementary data lines by the amplification operation in the sense amplifier SA, a relatively large conductance is generated.
Turn on MOSFETQ11 and Q13 to speed up their amplification operation. Divided into two stages like this,
By performing the amplification operation of the sense amplifier SA, high-speed reading is performed while preventing the complementary data line from falling on the high level side.

One circuit (four word lines) of the row decoder R-DCR is shown as a representative, and for example, an n channel that receives address signals 2 to 6.
MOSFETQ32~Q36 and p channel
The word line selection signals for the four lines are formed by a NAND circuit using a CMOS circuit composed of MOSFETs Q37 to Q41.

The output of this NAND circuit is a CMOS inverter.
Inverted by IV1, cut MOSFETQ28~Q3
1 to the gates of MOSFETs Q24 to Q27.

In addition, four word line selection timing signals φx00 to φx11 formed by a combination of the decode signal formed by the address signals a0 and a1 and the timing pulse φx are applied to the MOSFETs Q24 to Q2.
7 to each word line.

Also, between each word line and the ground potential,
MOSFETs Q20 to Q23 are provided, and by applying the output of the NAND circuit to their gates, the word line is fixed at the ground potential when not selected.

The above word line has MOSFETQ for reset.
MOSFETs Q0 to Q4 are provided, and when these MOSFETs Q0 to Q4 are turned on in response to a reset pulse φpw, the selected word line is reset to the ground level.

The column switch C-SW selectively couples the complementary data line D and the common complementary data line CD, like MOSFETs Q42 and Q43 shown as representatives. These MOSFETQ42,
The gate of Q43 has a column decoder C-DCR.
A selection signal is supplied from. In addition, in the same figure,
One complementary data line pair is shown as representative. In order to write/read 9 bits in parallel as described above, the one selection signal is commonly supplied to nine pairs of adjacent complementary data lines.

A precharge MOSFET Q44 similar to the above is provided between the common complementary data lines CD. A pair of input/output nodes of a main amplifier MA having a circuit configuration similar to that of the sense amplifier SA are coupled to this common complementary data line CD.
The input/output circuit I/O is composed of a data input buffer DIB and a data output buffer DOB. The data input buffer DIB operates according to the timing signal φin, and the data output buffer DOB
operates according to the timing output φop.

The other (right side) memory array M-ARY2 and its selection circuit are configured with the same circuit configuration as described above.

Note that the memory array of this embodiment can be reduced to about Vcc/by simply shortening the common complementary data line.
2, the amount of level change is small compared to dynamic RAM, which charges up the data line from 0 volts to the Vcc level, and the gate voltage of the precharge MOSFET is lower than the normal logic level (Vcc). Since it can be turned on in a sufficiently non-saturated state even when used, the precharge operation can be performed at high speed and with low power consumption.

As mentioned above, since the precharge level is set to an intermediate level of approximately Vcc/2,
Even when reading a memory cell, it can be turned on in a sufficiently unsaturated state even if the normal logic level (Vcc) is used as the gate voltage (word line selection voltage) of the memory cell switch MOSFET, so the data line Dynamic type that charges up from 0 volts to Vcc level
It becomes possible to read out the entire charge of the information storage capacitor without using a bootstrap voltage as in RAM.

Further, since the read reference voltage uses the precharge level of one data line in which no memory cell is selected, a dummy cell for forming the read reference voltage is not required.

FIG. 3 shows a timing diagram for explaining the operation of the edge trigger circuit EG.

When the input of the external address signal RAD or CAD changes the address signal ak of any of the address signals a0 to am-1 and a0 to an-1 via the address buffer R-ADB or C-ADB,
By inputting the address signal ak and the delayed signal ak' to the exclusive OR circuit, an edge detection signal having a pulse width according to the delay time is formed. This edge detection signal φ is input to the timing control circuit TG through the OR circuit, thereby forming a series of timing signals necessary for internal memory operation.

In a read operation, the data output buffer
When the timing signal φop that starts DOB rises, multiple data output buffers DOB
starts working. In this embodiment, the edge trigger circuit is activated by the timing φdk formed by an AND circuit that receives the timing signal φop and the delayed signal 'of its inverted signal.
EG is said to be insensitive. Although not particularly limited, a new gate circuit is provided in the OR circuit of the edge trigger circuit EG that sends the detection signal φ to the timing control circuit TG, and the gate is closed by the timing signal φdk.

Therefore, the above multiple data output buffers
Even if there is a malfunction in which an edge detection signal is formed due to noise in the power supply line (power supply voltage line and circuit ground potential line) caused by DOB operating all at once, the edge detection signal will be transferred to the timing control circuit TG. is not transmitted.

〔effect〕

(1) The edge trigger circuit is made insensitive at the start of its operation by using the operation timing signal of the data output buffer DOB, thereby preventing malfunctions in the timing control circuit caused by noise generated in the power supply line. I can do it.

(2) Due to (1) above, the external address signal does not change during the operation timing of the data output buffer, so there is no problem even if the edge trigger circuit is insensitive, and access time will not be sacrificed. This effect can be obtained.
That is, it is possible to suppress the peak value of noise by slightly shifting the operation start timings of the plurality of data output buffers, but in this case, there is a drawback that the access time becomes slower.

(3) By forming the internal timing signal for memory operation in accordance with the change timing of the address signal, it is possible to operate the memory asynchronously, resulting in the effect that an easy-to-handle semiconductor memory device can be obtained.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, the plurality of bits can be variously modified as necessary, such as 4 or 8 bits.

Also, when applied to dynamic RAM,
For reading the memory cell, a dummy cell may be used to form a reference voltage.

[Application field]

Dynamic RAM, which is the application field that forms the background of the invention made by the present inventor.
(Pseudo-static RAM) has been described; however, it is not limited to this; for example, it can be applied to static RAM or programmable ROM (read-only memory).
Even in this case, the present invention can be widely applied to semiconductor memory devices as long as the change timing of the address signal is detected to form the internal operation timing signal, and as described above, at least a signal of multiple bits is read.

[Brief explanation of drawings]

FIG. 1 is an internal configuration block diagram showing one embodiment of this invention, FIG. 2 is a circuit diagram specifically showing one embodiment, and FIG. 3 is a timing diagram for explaining its operation. be. M-ARY1, M-ARY2...Memory array,
PC1, PC2...Precharge circuit, SA1, SA
2...Sense amplifier, R-ADB...Row address buffer, C-SW1, C-SW2...Column switch, C-ADB...Column address buffer, R-DCR...Row address decoder, C-
DCR1, C-DCR2...Column address decoder, MA1, MA2...Main amplifier, TG...
Timing generation circuit, EG...edge trigger circuit,
DOB...Data output buffer, DIB...Data input buffer.

Claims (1)

[Scope of Claims] 1. A detection circuit that detects the change timing of an external address signal, a timing control circuit that forms a timing signal for internal operation based on the detection signal from the detection circuit, and reads out multiple bits of stored information in parallel form. 1. A semiconductor memory device having a plurality of data output buffers, further comprising a gate circuit for inhibiting a detection operation of the detection circuit during the data output buffer operation. 2. The semiconductor memory device according to claim 1, wherein a signal formed using an operation timing signal of the data output buffer and its delay signal is applied to the gate circuit. 3. The semiconductor memory device according to claim 1 or 2, wherein the semiconductor memory device is a RAM.