JPH0327938B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a floating-point multiplication circuit, particularly a floating-point multiplication circuit used in a high-speed digital signal processing processor for real-time processing of data with a wide dynamic range (maximum possible amplitude of data). It is related to.

The floating-point multiplication circuit is composed of a fixed-point multiplier dedicated to mantissa operations and an adder dedicated to exponent operations. In other words, the two numbers to be multiplied are A ₁ = M ₁・
2 ^e1 and A ₂ = M ₂・2 ^e2 , then the multiplication result is A =
A ₁ ·A ₂ =M ₁ ·M ₂ ·2 ^e1+e2 , and multiplication of M ₁ ·M ₂ and addition of e ₁ +e ₂ are performed. Here M ₁ , M ₂
is the mantissa and e ₁ and e ₂ are the exponents. In floating point multiplication, the mantissa parts of the two inputs are normalized to maintain the maximum number of significant digits. When these multiplication circuits are constructed with binary digital circuits, the number of bits in the mantissa and exponent parts is specified for convenience in circuit configuration, so the multiplication result, that is, the product, must also be expressed with a fixed number of bits. As a result, overflow and underflow problems occur.

Also, when normalizing the multiplication result, moving the mantissa and adding or subtracting the exponent by that amount, overflow may occur even when the exponent does not fall within the range represented by the normal number of bits. A problem arises.

Conventionally, when overflow (overflow, underflow) occurs in the mantissa and exponent parts, a flag has been used to detect the occurrence, and the correction has been processed using a program. Therefore, it takes a considerable amount of time to execute a program for handling overflow, and there is a drawback that high-speed calculation cannot be performed. In particular, in devices such as communication devices that require real-time processing, that is, input and output must be performed in the same time relationship, even higher-speed signal processing devices are required, and in particular, multipliers that require time are required to be faster. .

Therefore, an object of the present invention is to realize a floating point multiplication circuit that can process overflow in floating point multiplication at high speed without performing program processing.

Another object of the present invention is to realize a circuit that quickly handles overflow that occurs in floating point multiplication.

In order to achieve the above object, the present invention provides a multiplication circuit for two floating point numbers consisting of a mantissa and an exponent of a fixed number of bits, and provides an overflow detection section for the input or output mantissa or exponent. The present invention is characterized in that the overflow correction circuit for the calculation output is driven by the signal.

The present invention will be described in detail using the drawings. First, before explaining embodiments, the principle of the present invention will be explained. Figure 1 shows two numbers A ₁ to be multiplied,
This shows the bit structure of A ₂ and its product A = A ₁ · A ₂ , where the mantissa of each number is M and the exponent is e.
It is expressed as A ₁ =M ₁ ·2 ^e1 , A ₂ =M ₂ ·2 ^e2 , and A=M·2 ^e (true value). The suffix on each symbol distinguishes each number. In floating point multiplication, two numbers A ₁ ,
The mantissas M ₁ and M ₂ of A ₂ are normalized to maximize the effective number, and when the binary number is expressed in two's complement representation, −2°≦M ₁ or M ₂ <−2 ⁻¹ or 2 ^-1 ≦
M ₁ or M ₂ <2° Also, due to the structure of the multiplication device, the number of bits representing the mantissa M and the exponent e are constant bit numbers m and n, respectively (in the case of A ₁ and A ₂ in Fig. 1, m = 12
n=4). Therefore, two numbers A ₁ ,
_A2 It will look like the illustration. The product of these two numbers A ₁ and A ₂ is expressed by a 23-bit mantissa and a 4- or 5-bit exponent if no restrictions are placed on the bit configuration. but,
Due to the configuration of the circuit and equipment, A ₀ =
In an actual device, it has the same bit configuration as the numbers A ₁ and A ₂ (m bits for the mantissa, n bits for the exponent), such as M ₀ ·2 ^e0 . Therefore, overflow occurs as described below.

(1) Overflow of high-order digits of the exponent The mantissa M ₀ of the product A ₀ of two normalized numbers A ₁ and A ₂ is (a) in an unnormalized state, that is, −2 ^-1 ≦M ₀ ≦−2 ^-2 ( 1) or 2 ^-2 <M ₀ <2 ^-1 (b) Normalized state, i.e. −2°≦M ₀ <−2 ^-1 (2) or 2 ^-1 ≦M ₀ <2° There is a condition.

Therefore, when the index e becomes 2 ^n-1 , the following problem occurs. Generally, in the state (a) where the mantissa is not normalized, it can be normalized by shifting the mantissa M ₀ to the left by 1 bit and subtracting 1 from the specified e ₀ , and when the exponent e ₀ is 2 ^n-1 or more. It is possible to perform complementation that maximizes the absolute value of the product A ₀ regardless of the state of the mantissa M ₀ , but if the mantissa M ₀ is not normalized (a) and the exponent e ₀ is 2 In the case of ^n-1 , if the above correction is performed, a large error will occur due to the correction. For example, if the exponent is n = 4 bits, e ₀
= 2 ^4-1 = 8, mantissa M ₀ = -2 ^-2 (non-normalized example), then the true product A ₀ is A ₀ = (-2 ^-2 ) x 2 ⁸
= −2 ⁶ , and the product after the above correction is
A ₀ ′ becomes A ₀ ′=(−2°)×2 ⁷ =−2 ⁷ , which is an erroneous value that is twice the true value A ₀ .

(2) Overflow of lower digits of the exponent When the true value of the exponent of the product is less than −2 ^n-1 , one possible method of correction is to approximate the exponent to −2 ^n-1 without performing a shift, as overflowing the lower digits. , it is not possible to effectively utilize the dynamic range of the mantissa.

(3) Overflow of mantissa digits When two numbers A ₁ and A ₂ are both -1, regardless of whether the true value of the product is 1, if the calculation is performed using two's complement representation, the product will be 1.0000... It becomes a binary number,
Since the MSB is "1", the value is incorrectly determined as -1.

The floating-point multiplier of the present invention corrects the above-mentioned overflow problem using a circuit that detects each overflow, and a correction circuit that has the following functions when an overflow is detected, without any program processing. It was designed to do so.

If the mantissa part M is not normalized and the exponent part becomes 2 ^n-1 , shift the mantissa part M to the left (carry up), set the exponent part to the maximum value that can be displayed, 2 ^n-1 -1, and e ₀ =
2 ^n-1 and the mantissa is normalized, or when the exponent e ₀ > 2 ^n-1 , the sign of the mantissa is not changed and the absolute value is set to the maximum.

If the exponent part is less than -2 ^n-1 (lower digits of the exponent overflow), the mantissa is equal to the bits obtained by subtracting the true exponent value e from the minimum displayable value of the exponent part -2 ^n-1 (e ₀ - e). Shift the part to the right (lower the digit). By this correction, the dynamic range is expanded by the effective bit length m bits of the mantissa.

When overflow occurs in the mantissa, that is, 2 numbers
When A ₁ and A ₂ are both -1, the first method shifts the mantissa to the right by 1 bit and adds 1 to the exponent.
Further, in the second method, the mantissa part is set to 2°-2 ^-(m-1) , and the exponent part is not corrected. Although the second method includes an error of ^2-15 , it is more advantageous than the first method in circuit configuration because it can be shared with the exponent overflow correction circuit used as another arithmetic circuit.

FIG. 2 is a block diagram showing the structure of an embodiment of a floating point multiplication circuit according to the present invention, which is constructed based on the above principle. This embodiment is composed of a first and a second arithmetic circuit. The first arithmetic circuit detects floating point multiplication and overflow;
This circuit performs exponent correction due to overflow of upper digits of the exponent and correction of the mantissa. The second arithmetic circuit is a circuit that corrects the exponent and mantissa due to overflow of lower digits of the exponent. In this embodiment, the circuit for correcting the overflow of the lower digits of the exponent, that is, the second arithmetic circuit has the output of the first arithmetic circuit and other inputs A ₃ (mantissa l ₉ ,
It also serves as an arithmetic circuit that performs arithmetic operations with an exponent l (consisting of ₁₀ ), and is also capable of performing floating-point multiplication and fixed-point arithmetic operations. The operation of each circuit configuration will be explained below.

In the arithmetic circuit, 12-bit mantissas corresponding to mantissas _M1 and _M2 in FIG. 1 are applied to a multiplication circuit 1 as input signals _l1 and _l2 , respectively, and output a multiplication result _l5 . On the other hand, 4-bit exponents corresponding to exponents e ₁ and e ₂ are respectively applied as input signals l ₃ and l ₄ to the adder circuit 2, and the addition result l ₆ is output. Since these input signals are expressed in 4-bit two's complement representation, there are restrictions such that -8≦l ₃ , l ₄ , l ₆ ≦7.

4 is a circuit for detecting overflow of exponent digits and correcting the exponent when the upper digits of the index are overflowed, including a detection signal C ₈ for detecting when the exponent is 8, a signal C MO representing overflow of the upper digits of the index, and a signal C _MO representing overflow of the lower digits of the index. Signal C _Mu
Output.

Reference numeral 14 switches between floating-point multiplication and fixed-point multiplication in response to control signal B, and is provided so that the circuit of this embodiment can also be used as a fixed-point arithmetic circuit.

FIG. 3 shows the circuit configuration of the adder circuit 2, the exponent overflow detection circuit 4, and the switching circuit 14. In the figure, l ₃ −2 ³ , l ₃ −2 ² , l ₃ −2 ¹ and l ₃ −2° are input
4-bit signal with A ₁ and exponent e ₁ , l ₄ -2 ³ , l ₄ -2 ² , l ₄
−2 ¹ and l ₄ −2° represent the 4-bit signal of index e ₂ of input A ₂ , l ₆ −2 ³ , l ₆ −2 ² , l ₆ −2 ¹ and l ₆ −2 ⁰
is the output ^of adder 2, and _C3 represents ^a carry signal from _l6-22 to _l6-23 . The OR circuit 16 and the AND circuit 17 are circuits that detect that the exponent e of the product is 8 or more, and when l ₃ -2 ³ and l ₄ -2 ³ are "0", the carry signal C ₃ is "1".
When (that is, C _MO = ( ₃ − 2 ³ ) + ( ₄ − 2 ³ )・C ₃
)
Output C _MO becomes “1”. AND circuit 18 and AND circuit 19 are circuits that detect when the exponent e is less than -8, and when l ₃ -2 ³ and l ₄ -2 ³ are "1" and C ₃ is "0"
When , the output C _Mu becomes “1”. AND circuit 20
is a circuit that detects that the index e is 8, and C _MO
is “1” and l ₆ −2 ² , l ₆ −2 ¹ , l ₆ −2 ⁰ are all “0”
(i.e. C _MO・( ₆ −2 ² )・( ₆ −2 ¹ )・₆
−
2 When ⁰ is “1”) Outputs “1”. The AND circuit 21 and the OR circuits 22, 23, and 24 have an exponent e of 8.
In the above case, the index is corrected to e ₀ =“0111”. The floating point multiplication and fixed point arithmetic switching circuit 14 is
It is used when changing the calculation style, and the control signal B becomes "1" during floating point multiplication.
Turn on the AND circuits 25, 26, and 27,
Passes the signals of C _Mu , C _MO , and C ₈ .

FIG. 4 is a circuit diagram of the mantissa correction circuit 3 shown in FIG ^. 2. As inputs, the signals C _MO and C ₈ shown in _{FIG .}
2 ⁰ , 16-bit signals l ₅ -2 ⁰ , l ₅ -2 ^-1 . . . l ₅ -2 ^-15 , which are the outputs of the mantissa multiplication circuit 1, are added. The logic circuit 29 includes inverters 30, 33, 35, exclusive ORs 31, 39, NAND circuits 32, 37, NOR circuits 34, 38, and an OR circuit 36, and determines various states of the multiplication results, AND gates 41, 4
2,...Turn 44 on and off. OR circuit 51...5
4 takes out the output of the AND gate and sets it as corrected mantissas l ₇ -2 ^-1 , l ₇ -2 ^-2 . . . l ₇ -2 ^-15 . The output l ₇ −2 ⁰ of the inverter 40 becomes the MSB signal of the mantissa.

With the above circuit, multiplication output other than overflowing of the lower digits of the exponent can be obtained. Each case will be explained separately below. When the exponent e is 8 or more, OR circuit 17 in Figure 3
e _{0 (} l ₈ −
2 ³ , l ₈ −2 ² , l ₈ −2 ¹ , l ₈ −2 ⁰ ) is “0111” (+7)
becomes. As for the mantissa part, since C _MO is "1" in FIG. 4, the NAND circuit 37 becomes "1", turning on the AND gates 41-1, 42-1, and 44-1, and MSBl ₅ -2 ⁰ becomes "0". ” or “1”, the value has the maximum absolute value, such as 0.11111...1 or 1.000...0, respectively.

However, if the exponent e is 8 and the mantissa is not normalized, that is, C _MO , C ₈ are “1” and l ₅ −2 ⁰ and l ₅ −
When the signs of 2 ^-1 are the same, the logic circuit 29
AND gates 41-3, 42-3, . . . are turned on, and the mantissa is shifted to the left by one bit.

When the exponent e is −8≦e<7, no overflow occurs, and the output l ₆ of the adder 2 of the exponent part becomes the output l ₈ (l ₈ −
2 ³ , l ₈ -2 ² ... l ₈ -2 ⁰ ), and if the mantissa part is not normalized, normalization processing is performed.

Now, in each of the above cases, when the two input data are both "1.000...0" (-1), an overflow occurs in the mantissa, but this detection is done by the NAND circuit 32 in FIG. (l ₁ −2 ⁰ )・(l ₂ −2 ⁰ )・
When it is detected that (l ₅ −2 ⁰ ) becomes “1”,
^The corrected mantissa ^{outputs l7-20, l7-2-2,...l7-2-15} _{become " 0.1111} ... ^{1 "} (= ^20-215 ). Next, the case of overflowing the lower digits of the exponent will be explained. Correction of the overflow of the lower digits of the exponent is performed in the second arithmetic circuit shown in FIG. 2 during the arithmetic operation with another input _A3 . In FIG. 3, when an overflow of the lower digits of the exponent occurs, C _Mu becomes "1", and the overflow of the lower digits of the exponent of FIG. It is added to the exponent comparison correction circuit 12 when the exponent lower digits overflow, the pre-calculation right shift correction circuit 8 when the exponent lower digit overflow occurs, and the switching circuit 13 for the exponent part calculation input bus.

The mantissa ^l9 of the other input _A3 is applied to the mantissa calculation input bus switching circuit 5, and the exponent _l10 is added to the switching circuit 13, the exponent comparison circuit 11, and the exponent correction circuit 6, respectively, and furthermore, the exponent output _l8 of the calculation circuit (=e ₀ ) is applied to the exponent correction circuit 6. The switching circuit 13 supplies the larger of the two exponents to another arithmetic circuit or an output terminal (not shown). Comparator 11
compares the magnitude of two indices. The exponent comparator circuit 12 corrects the output _l17 of the comparator circuit 11 when the exponent lower digits overflow, generates a control signal _l18 when the exponent lower digit overflow occurs, and outputs the input signal (mantissa) of the input bus switching circuit 5. ) _l7 as an output signal _l14 to the pre-computation right shift circuit 9, and controls the input bus switching circuit 13 to output the input signal _l10 as an output,
Controls the subtraction circuit 7. The exponent correction circuit 6, the subtraction circuit 7, and the right shift correction circuit 8 determine the amount of right shift of the mantissa part, as will be explained in detail in FIG. 15 is a switching circuit between floating point arithmetic and fixed point arithmetic;
This is a 10 fixed point subtraction circuit.

Now let the exponent of the output of the arithmetic circuit be β = {β ₃ β ₂ β ₁ β ₀ }
Let the true value of the exponent part be e. Note that β is the output in the case of overflow of lower digits. Also, let the exponents of other inputs be α={α ₃ , α ₂ , α ₁ , α ₀ } (this signal is represented by l ₁₀ ).

Overflow of lower exponent digits occurs when ₃ ·C _Mu = “1”. At this time, since e<-8 and β≧0 in 4-bit two's complement representation, e<β. Therefore, when C _Mu is 1, β is smaller than e, so the exponent comparison and correction circuit performs complementation. In order to align the exponents of the two inputs, it is necessary to find (α-e), but α-e can be expressed as α-e=α-(-16+β) =(α+8)-(-8+β)...(3) Ru. Here, for α and β, −8≦α≦7 …(4) 0≦β≦7 …(5) 0≦α+8≦15 …(6) −8≦−8+β≦−1 …(7 ), so the following inequality holds true: α+8>-8+β ……(8) 1≦α−e≦23 ……(9) On the other hand, input data 1 to the mantissa right shift circuit 9
3 must be limited by 0≦l ₁₃ ≦15, so the following correction is necessary.

When α-e<16, l ₁₃ = α-e...(10) When α-e<16, l ₁₃ = 15...(11) Expressing the above equation in logical symbols for the circuit configuration, (3)
The formulas (α+8) and (-8+β) are (α+8) = {(α ₃ 1) α ₂ α ₁ α ₀ } = {(α ₃ C _Mu ) α ₂ α ₁ α ₀ } ...(12) (- 8 + β) = {(1 + 0) β ₂ β ₁ β ₀ } = {(β ₃ +C _Mu ) β ₂ β ₁ β ₀ } ...(13) Also, if we find the condition C for equations (10) and (11), x = (C _Mu + α ₃ ) = ₃ ... (14) y = ( _Mu + ₃ ) = 0 ... (15) Then C = {x・y+(xy)・C ₂ }・C _Mu ...( 16) =x・C ₂・C _Mu ...(17)

FIG. 5 shows an example of an exponent overflow circuit for floating-point multiplication constructed based on the above principle, and blocks 6, 7, 8, 12, and 15 correspond to the parts with the same numbers in FIG. 2. . In the figure, the signal
l ₈ −2 ³ , l ₈ −2 ² , l ₈ −2 ¹ , l ₈ −2 ⁰ are the above β ₃ , β ₂ , β ₁
，
In addition to β ₀ , l ₁₀ −2 ³ , l ₁₀ −2 ² , l ₁₀ −2 ¹ , and l ₁₀ −2 ⁰ correspond to the above α ₃ , α ₂ , α ₁ , and α ₀ . The exclusive OR circuit 55 executes α ₃ C _Mu in equation (12), and the OR circuit 56 executes β ₃ +C _Mu in equation (14). Comparison correction circuit 12
When C _Mu is “1”, turn on switch S ₁ ,
_S2 is turned off and the signal _l18 is set to "0". When C _Mu is "0", this is reversed and l ₁₈ becomes l ₁₇ . The subtraction circuit 7 outputs α−e, but in the right shift correction circuit 8, the AND circuit 57 outputs the above (17).
Condition C of the expression is judged, and if the shift is greater than 16, "1" is output. Therefore α−e is ≧16
In this case, set 15 as shift signal l ₁₃ , and set α−
When e<16, α-e is set as _l3 .

The following explanation deals with the case where the correction of the overflow of the lower digits of the exponent is performed during addition and subtraction with other input data _A3 , but the multiplication result of two input data _A1 and _A2 is
If it is desired to directly take out the output of the arithmetic circuit, the data of the mantissa part _l9 of the other input signal _A3 should be set to 0, and the data of the exponent part _l10 should be set to -8. That is, (00...0)×2 ^-8 = 0, which is the output obtained by adding 0, and the product A ₀ of the two inputs A ₁ and A ₂ is found.

[Brief explanation of drawings]

FIG. 1 is a bit configuration diagram of input data in floating point multiplication, FIG. 2 is a block diagram showing the configuration of an embodiment of a floating point multiplication circuit according to the present invention, and FIG. 3 is an adder circuit 2 and an exponent in the above embodiment. Figure 4 is a circuit diagram of the overflow detection circuit 4 and switching circuit 14, Figure 4 is a circuit diagram of the mantissa correction circuit 3 in Figure 1, and Figure 5 is a circuit diagram of blocks 6, 7, 8, and 15 in Figure 1. be. 1... Multiplication circuit, 2... Addition circuit, 3... Mantissa correction circuit, 4... Exponent overflow detection circuit, 5...
...Mantissa calculation input bus switching circuit, 6...Exponent correction circuit, 7...Subtraction circuit, 8...Right shift correction circuit, 9...Right shift circuit, 10...Fixed point addition/subtraction circuit, 11...Exponent comparison circuit, 12...comparison correction circuit, 13...exponential calculation input bus switching circuit,
14, 15...Floating point arithmetic and fixed point arithmetic switching circuit.

Claims (1)

[Claims] 1. First and second floating point representations expressed in two's complement
a first circuit having a mantissa multiplier circuit that multiplies the mantissa parts of input data; and an exponent adder circuit that adds the exponent parts of the first and second input data; A floating point multiplication circuit comprising a second circuit that adds third input data in point representation and outputs of the mantissa multiplication circuit and the exponent addition circuit, the first circuit comprising: a first detection circuit that detects overflow in the output of the exponent addition circuit; and a first detection circuit that is connected to the exponent addition circuit and transmits the output of the exponent addition circuit in the detected overflow state to the second circuit. a first correction circuit that corrects the output before supply; a second detection circuit that detects overflow of the output to the mantissa multiplication circuit; and a second detection circuit that is connected to the mantissa multiplication circuit and detects the overflow of the mantissa. and a second correction circuit that corrects the output of the multiplication circuit before supplying it to the second circuit, and the number of bits representing the exponent part of the first and second input data is n bits. In this case, when the first detection circuit detects that the output of the exponent addition circuit becomes 2 ^n-1 ,
The correction circuit converts the output of the exponent addition circuit into 2 ^n-1 −
1, and when the first detection circuit detects that the output of the mantissa multiplication circuit is not normalized and the output of the exponent addition circuit is 2n ^-1 , the second A floating point multiplication circuit characterized in that the correction circuit shifts the output of the mantissa multiplication circuit to the left by one bit. 2. A third correction circuit that performs, as part of the addition operation of the second circuit, an operation of correcting the output of the exponent part addition circuit with overflow detected in response to the output of the first detection circuit. 2. The floating point multiplication circuit according to claim 1, wherein said second circuit comprises: