JPH0332228B2 - - Google Patents
Info
- Publication number
- JPH0332228B2 JPH0332228B2 JP56070939A JP7093981A JPH0332228B2 JP H0332228 B2 JPH0332228 B2 JP H0332228B2 JP 56070939 A JP56070939 A JP 56070939A JP 7093981 A JP7093981 A JP 7093981A JP H0332228 B2 JPH0332228 B2 JP H0332228B2
- Authority
- JP
- Japan
- Prior art keywords
- electrically
- layer
- state
- diffusion layer
- conductive state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
- H10W20/491—Antifuses, i.e. interconnections changeable from non-conductive to conductive
Landscapes
- Read Only Memory (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
従来電気的に書き込み可能な読み出し専用記憶
装置としては、第１図に示す如くSi基板１上に形
成されたSiO2等からなる絶縁膜２上に多結晶Si
よりなる抵抗体配線層３を形成し、層間絶縁膜と
してのCVD・SiO2膜等からなる膜４等を介して
Al等からなる電極配線５を形成し、電極配線５
の間に電流を流すことにより、多結晶Si層３を熔
融して切断し、初期のSi抵抗体層３を通しての導
通状態と、熔断後の不導通状態とを情報の“０”
と“１”に対応させて電気的に書き込可能な読み
出し専用記憶装置となしていた。DETAILED DESCRIPTION OF THE INVENTION Conventionally, as shown in FIG. 1, electrically writable read-only storage devices include a polycrystalline silicon film on an insulating film 2 made of SiO 2 or the like formed on a Si substrate 1.
A resistor wiring layer 3 made of
The electrode wiring 5 made of Al etc. is formed, and the electrode wiring 5
By passing a current between them, the polycrystalline Si layer 3 is melted and cut, and the initial conductive state through the Si resistor layer 3 and the non-conductive state after melting are changed to "0" of information.
and "1", making it an electrically writable read-only storage device.
しかしながら、前記従来技術では抵抗体の熔断
膜の飛散粒が再付着して、熔断が不完全になつた
り、飛散粒が他の配線層に付着して短絡状態とな
したりして、その信頼性にも充分でないという欠
点があつた。 However, in the conventional technology, the scattered grains of the melted film of the resistor re-deposit, resulting in incomplete fusing, or the scattered grains adhere to other wiring layers, causing a short circuit, resulting in poor reliability. The problem was that it was not sufficient.
本発明はかかる従来技術の欠点のない電気的に
書き込み可能な読み出し専用記憶装置を提供しよ
うとするものであり、その目的とするところは、
熔断式の書き込み方式を改め、導通式の書き込み
方式となし、信頼度の高い電気的書き込み可能な
読み出し専用記憶装置を提供することにする。 The present invention seeks to provide an electrically writable read-only storage device that does not have the disadvantages of the prior art, and its purpose is to:
We decided to change the fusing type writing method to a conductive type writing method and provide a highly reliable electrically writable read-only storage device.
かかる目的を達成するための本発明の要旨とす
るところは、半導体材料において導通型決定不純
物を含み且つイオン打込み層等からなる電気不良
導通体部を形成し、該電気不良導通体に電流を通
過せしめることにより、電気不良導通状態から電
気良導通状態とを情報の“０”と“１”状態に対
応させた電気的に書き込み可能な読み出し専用記
憶装置とする事を特徴とする。 The gist of the present invention to achieve such an object is to form an electrically defective conductor portion containing conduction type determining impurities and consisting of an ion-implanted layer or the like in a semiconductor material, and to pass a current through the electrically defective conductor. By this, an electrically writable read-only storage device is produced in which a state of electrically poor conduction to a state of good electrical conduction corresponds to "0" and "1" states of information.
以下、実施例にそつて本発明を具体的に説明す
る。 The present invention will be specifically described below with reference to Examples.
第２図は本発明の一実施例を示し、１１はSi基
板、１２はSiO2等からなる絶縁膜、１３は導通
決定不純物（Ｐ、Ｂ、As、等）を含む多結晶Si
層、１４は前記多結晶Si層にArイオン打込み等
によりアモルフアス化を部分的に行ない、且つ初
期状態で一時的に高抵抗に不良導通体とした層、
１５は層間絶縁膜としてのCVD、SiO2膜、１６
はAl電極配線層である。 FIG. 2 shows an embodiment of the present invention, in which 11 is a Si substrate, 12 is an insulating film made of SiO 2 etc., and 13 is a polycrystalline Si substrate containing conductivity-determining impurities (P, B, As, etc.).
Layer 14 is a layer in which the polycrystalline Si layer is partially amorphized by Ar ion implantation or the like, and is temporarily made into a high resistance and poor conductor in the initial state;
15 is CVD as an interlayer insulating film, SiO 2 film, 16
is the Al electrode wiring layer.
このように電気の不良導通層１４に、Al電極
１６間に電圧を印加し、多結晶Si層を介して電流
を通すと、不良導通層１４は加熱され、アニール
された状態となり、多結晶Si層に含まれた導電型
決定不純物が活性化され、更に当初乱れた結晶構
造が再配列し、より結晶性が向上し、電気的に良
導通体となり、初期にその抵抗値が100Kオーム
以上であつたものが300オーム程度と抵抗値が下
がる。アモルフアスSiの場合この状態は逆方向バ
イアス印加によつて可逆ではない。この様に抵抗
値の初期の高抵抗状態を“０”、電気アニール後
の低抵抗状態を“１”状態とした情報の書き込み
が行なえる。この様に電気的に書き込みを行なう
場合に、材料の融断によらず、抵抗値の変化とな
すことにより、融断の場合における飛散粒の発生
による融断不完全、あるいは他の配線の短絡状態
の発生等は全くなく、信頼度の高い電気的書き込
みが可能となる。 In this way, when a voltage is applied between the Al electrodes 16 and a current is passed through the polycrystalline Si layer to the electrically defective conductive layer 14, the defective electrically conductive layer 14 is heated and becomes an annealed state, and the polycrystalline Si The conductivity type-determining impurities contained in the layer are activated, and the initially disordered crystal structure is rearranged, improving crystallinity and becoming a good electrical conductor, with an initial resistance value of 100K ohms or more. When heated, the resistance value decreases to around 300 ohms. In the case of amorphous Si, this state is not reversible by applying a reverse bias. In this way, information can be written in which the initial high resistance state of the resistance value is set to "0" and the low resistance state after electrical annealing is set to the "1" state. When writing electrically in this way, the change in resistance value does not occur due to melting of the material, which may result in incomplete cutting due to the generation of scattered particles in the case of melting, or short circuits in other wiring. There is no occurrence of any state, and highly reliable electrical writing is possible.
本実施例では導電型決定不純物を予め含有した
多結晶半導体層への不活性ガスのイオン打込みを
施した場合を例にしたが、イオン打込み種は導電
型決定不純物でも良い。 In this embodiment, an example is given in which ions of an inert gas are implanted into a polycrystalline semiconductor layer containing a conductivity type determining impurity in advance, but the ion implantation species may be a conductivity type determining impurity.
又、本実施例ではイオン打込みによる不良導通
層１４の形成を例にとつたが、スパツタリング
等、蒸着や、CVDによる導電決定不純物を含有
した半導体層であつてもよい。 Furthermore, although this embodiment takes as an example the formation of the defective conductive layer 14 by ion implantation, it may be a semiconductor layer containing conductivity-determining impurities by sputtering, vapor deposition, or CVD.
かかる本発明は電圧の印加により不良導通体を
良導通体状態に不可逆的に転換させ読み出し専用
記憶装置として用いるものであり、絶縁材上に形
成した半導体材料層内に導電型不純物を含む第１
と第２の拡散層とその間に結晶構造の乱れた電気
不良導体部とを横に並べて配置形成するものであ
り、拡散層部と電気不良導通部の各々の部分が１
回の薄膜形成により得られるので製造が簡略化さ
れ、特に不良導通体部両側にある拡散層部との界
面を各々均一につくることが容易にでき電気特性
の安定した記憶装置とすることができる。また、
導通部となる拡散層部と電気不良導通体部とが重
なることなく平面的に並んでいるので、拡散層に
接続される配線層からの原子のつき抜けといつた
問題がなく常に安定した記憶装置の特性が得られ
るメリツトをもつ。 The present invention is used as a read-only storage device by irreversibly converting a bad conductor into a good conductor state by applying a voltage.
and a second diffusion layer, and an electrically defective conductor portion with a disordered crystal structure are arranged side by side between them, and each portion of the diffusion layer portion and the electrically defective conductor portion is one layer.
Since it is obtained by multiple thin film formations, manufacturing is simplified, and in particular, it is easy to create uniform interfaces with the diffusion layer portions on both sides of the defective conductor portion, resulting in a memory device with stable electrical characteristics. . Also,
Since the diffusion layer part that becomes the conductive part and the electrically defective conductor part are arranged in a plane without overlapping, there is no problem such as penetration of atoms from the wiring layer connected to the diffusion layer, and the memory is always stable. It has the advantage of providing the characteristics of the device.
さらに、不良導通層１４から発する熱の放散の
ために、抵抗層の周辺、あるいはその上面や下面
に絶縁膜等を介して熱伝導の良いAl等の放熱層
を形成すると一層信頼度の向上が計れる。 Furthermore, in order to dissipate the heat emitted from the defective conductive layer 14, reliability can be further improved by forming a heat dissipation layer such as Al, which has good thermal conductivity, around the resistor layer or on its upper and lower surfaces via an insulating film, etc. It can be measured.
第１図は従来技術の概要を示す縦断面図、第２
図は本発明の概要を示す縦断面図である。
１，１１…半導体基板、２，１２…絶縁膜、
３，１３…多結晶Si層、４，１５…層間絶縁膜、
５，１６…電極配線層、１４…不良導通層。
Figure 1 is a vertical cross-sectional view showing an overview of the conventional technology;
The figure is a longitudinal sectional view showing an outline of the present invention. 1, 11... Semiconductor substrate, 2, 12... Insulating film,
3, 13... Polycrystalline Si layer, 4, 15... Interlayer insulating film,
5, 16... Electrode wiring layer, 14... Defective conduction layer.
Claims (1)
型決定不純物を含む第１と第２の拡散層部と該第
１と第２の拡散層部の間に結晶構造の乱れた電気
不良導通体部とを形成し、前記半導体材料層上に
前記第１と第２の拡散層部と対向する部分に開口
部を備えた層間絶縁膜を形成し、且つ前記層間絶
縁膜上に一部が前記開口部を介して前記第１と第
２の拡散層に接続される配線層を形成してなり、
前記電気不良導通体に電流を通過せしめることに
より結晶性を向上させ電気不良導通状態から電気
良導通状態に不可逆的になし、この不良導通状態
と良導通状態とを情報の“０”、“１”状態に対応
させた電気的に書き込み可能な読み出し専用記憶
装置とすることを特徴とする半導体記憶装置。1. First and second diffusion layer portions containing conductivity type determining impurities in a semiconductor material layer formed on the upper surface of an insulating material, and an electrically defective conductor with a disordered crystal structure between the first and second diffusion layer portions. forming an interlayer insulating film having an opening in a portion facing the first and second diffusion layer portions on the semiconductor material layer; forming a wiring layer connected to the first and second diffusion layers through an opening,
By passing a current through the electrically poor conductor, the crystallinity is improved and the electrically poor conductive state is irreversibly changed from the electrically poor conductive state to the electrically good electrically conductive state. ``A semiconductor memory device characterized by being an electrically writable read-only memory device that corresponds to a state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7093981A JPS57186356A (en) | 1981-05-12 | 1981-05-12 | Semiconductor memory storage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7093981A JPS57186356A (en) | 1981-05-12 | 1981-05-12 | Semiconductor memory storage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57186356A JPS57186356A (en) | 1982-11-16 |
| JPH0332228B2 true JPH0332228B2 (en) | 1991-05-10 |
Family
ID=13445967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7093981A Granted JPS57186356A (en) | 1981-05-12 | 1981-05-12 | Semiconductor memory storage |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57186356A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62188243A (en) * | 1985-10-18 | 1987-08-17 | レヴイ ガ−ズバ−グ | Method and structure for connecting electric circuit elements selectively |
| WO1992007380A1 (en) * | 1990-10-15 | 1992-04-30 | Seiko Epson Corporation | Semiconductor device having switching circuit to be switched by light and its fabrication process |
| GB2382220A (en) * | 2001-11-20 | 2003-05-21 | Zarlink Semiconductor Ltd | Polysilicon diode antifuse |
| JP2007230643A (en) * | 2006-03-03 | 2007-09-13 | Dainippon Printing Co Ltd | Cup-shaped container with non-contact IC tag |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5061730U (en) * | 1973-10-09 | 1975-06-06 |
-
1981
- 1981-05-12 JP JP7093981A patent/JPS57186356A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57186356A (en) | 1982-11-16 |
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