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JPH0337734B2 - - Google Patents
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JPH0337734B2 - - Google Patents

Info

Publication number
JPH0337734B2
JPH0337734B2 JP10379383A JP10379383A JPH0337734B2 JP H0337734 B2 JPH0337734 B2 JP H0337734B2 JP 10379383 A JP10379383 A JP 10379383A JP 10379383 A JP10379383 A JP 10379383A JP H0337734 B2 JPH0337734 B2 JP H0337734B2
Authority
JP
Japan
Prior art keywords
interlayer insulating
electrode
insulating layer
stepped portion
layer electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10379383A
Other languages
Japanese (ja)
Other versions
JPS59228736A (en
Inventor
Sadazumi Shiraishi
Yukio Motoyoshi
Katsuaki Saida
Seiji Kuwabara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP10379383A priority Critical patent/JPS59228736A/en
Publication of JPS59228736A publication Critical patent/JPS59228736A/en
Publication of JPH0337734B2 publication Critical patent/JPH0337734B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 本発明は感光性ポリイミド樹脂によつて形成さ
れた層間絶縁層をもつ多層配線において、該層間
絶縁層の段差部における上層電極の断線を防止す
ることを目的としたものである。
DETAILED DESCRIPTION OF THE INVENTION The object of the present invention is to prevent disconnection of upper layer electrodes at stepped portions of the interlayer insulating layer in multilayer wiring having an interlayer insulating layer formed of photosensitive polyimide resin. It is.

従来の方法では感光性ポリイミド樹脂を層間絶
縁層として用いる場合、フオトリン工程によつて
層間絶縁層パターンを形成しスルーホールなどを
設けるが、その際層間絶縁層パターンの段差部が
必要とする層間絶縁層の厚み以上に盛り上がるた
め、上層電極形成時に段差部分で上層電極の断線
が生じやすいという欠点がある。この欠点を図面
に基づいて説明する。第1図は感光性ポリイミド
樹脂を層間絶縁層とした場合の従来の多層配線構
造の例を示す断面および平面図である。層間絶縁
層1においてスルーホール2を形成する場合には
フオトリソ工程によるわけであるが、その際該ス
ルーホール2の段差部分3は必要とする厚み以上
に盛り上がつてしまうことが避けられない。この
盛り上がりが鋭いために第2図に示すように上層
電極4を蒸着する際に、該上層電極4が該層間絶
縁層1の該段差部分3において断線してしまう。
あるいは第3図のように、蒸着時に断線しなくと
も該上層電極4をフオトリソ工程によつて形成す
る場合、該段差部分3におけるフオトレジスト層
7が薄いため該段差部分3において該上層電極4
がエツチング液によつて侵食され断線してしま
う。このように感光性ポリイミド樹脂を用いた場
合の従来の多層配線構造では、層間絶縁層の段差
部での鋭い盛り上がりに起因する上層電極の断線
が発生しやすい。
In the conventional method, when photosensitive polyimide resin is used as an interlayer insulation layer, an interlayer insulation layer pattern is formed by a photorin process and through holes etc. are provided. Since the rise exceeds the thickness of the layer, there is a drawback that the upper layer electrode is likely to be disconnected at the step portion when forming the upper layer electrode. This drawback will be explained based on the drawings. FIG. 1 is a cross-sectional and plan view showing an example of a conventional multilayer wiring structure in which a photosensitive polyimide resin is used as an interlayer insulating layer. When forming the through hole 2 in the interlayer insulating layer 1, a photolithography process is used, but in this case, it is inevitable that the stepped portion 3 of the through hole 2 will be raised to a thickness greater than the required thickness. Because this bulge is sharp, as shown in FIG. 2, when the upper layer electrode 4 is deposited, the upper layer electrode 4 is disconnected at the stepped portion 3 of the interlayer insulating layer 1.
Alternatively, as shown in FIG. 3, when the upper layer electrode 4 is formed by a photolithography process even if there is no disconnection during vapor deposition, since the photoresist layer 7 at the stepped portion 3 is thin, the upper layer electrode 4 is formed at the stepped portion 3.
is eroded by the etching solution and breaks. As described above, in the conventional multilayer wiring structure using photosensitive polyimide resin, disconnection of the upper layer electrode is likely to occur due to sharp bulges at the stepped portions of the interlayer insulating layer.

本発明はこのような層間絶縁層段差部分におけ
る上層電極の断線を防止することを目的としたも
のであり、段差部分下層に下層電極配線パターン
に加えて疑似電極を設けることを特徴としてい
る。この方法は第1図に示したように、感光性ポ
リイミド樹脂を用いた層間絶縁層が下層電極配線
パターンによる段差をそのまま反映して形成され
ることを積極的に利用するものである。
The present invention is aimed at preventing disconnection of the upper layer electrode at such a stepped portion of the interlayer insulating layer, and is characterized by providing a pseudo electrode in addition to the lower layer electrode wiring pattern below the stepped portion. As shown in FIG. 1, this method actively utilizes the fact that the interlayer insulating layer made of photosensitive polyimide resin is formed by directly reflecting the step difference caused by the lower layer electrode wiring pattern.

以下に本発明を図面に基づいて詳細に説明す
る。第4図および第5図は本発明の好適な応用例
を示す図である。第4図に示すようにスルーホー
ル2を介して上層電極4と導通する下層電極6に
隣接して疑似電極8を設ける。段差部分3におけ
る層間絶縁層1の盛り上がりはこの場合も避けら
れないが、同時に該擬似電極8による段差もある
ため該段差部分3は従来のような鋭い盛り上がり
をもたず、全体として該段差部分3を平担にする
ことができる。あるいは第5図に示すように該下
層電極6に隣接する下層電極5の、該スルーホー
ル2と平行な部分の幅を該スルーホール2の側に
広げることによつても同様の効果をもたせること
ができる。
The present invention will be explained in detail below based on the drawings. FIGS. 4 and 5 are diagrams showing preferred application examples of the present invention. As shown in FIG. 4, a pseudo electrode 8 is provided adjacent to the lower layer electrode 6 which is electrically connected to the upper layer electrode 4 via the through hole 2. Although the swell of the interlayer insulating layer 1 at the stepped portion 3 is unavoidable in this case as well, since there is also a step due to the pseudo electrode 8, the stepped portion 3 does not have a sharp bulge as in the conventional case, and the stepped portion as a whole is 3 can be flattened. Alternatively, as shown in FIG. 5, the same effect can be achieved by widening the width of the portion of the lower layer electrode 5 adjacent to the lower layer electrode 6 that is parallel to the through hole 2 toward the through hole 2 side. Can be done.

以上のように本発明によつて、層間絶縁層段差
部分における鋭い盛り上がりを下層に設けた疑似
電極による段差を利用して緩和することができ、
感光性ポリイミド樹脂を層間絶縁層として用いた
場合に生じやすい上層電極の層間絶縁層段差部分
における断線を防止することができる。
As described above, according to the present invention, sharp bulges in the step portion of the interlayer insulating layer can be alleviated by using the step formed by the pseudo electrode provided in the lower layer.
It is possible to prevent wire breakage at the stepped portion of the interlayer insulating layer of the upper electrode, which is likely to occur when a photosensitive polyimide resin is used as the interlayer insulating layer.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はポリイミド樹脂を層間絶縁層とする場
合の従来の多層配線構造の例を示す図、第2図お
よび第3図は従来の方法による欠点を示す図、第
4図および第5図は本発明の好適な応用例を示す
図である。 1……ポリイミド樹脂を用いた層間絶縁層、2
……スルーホール、3……層間絶縁層の段差部
分、4……上層電極、5……下層電極、6……ス
ルーホールのある下層電極、7……フオトレジス
ト層、8……擬似電極。
Figure 1 is a diagram showing an example of a conventional multilayer wiring structure when polyimide resin is used as an interlayer insulation layer, Figures 2 and 3 are diagrams showing drawbacks of the conventional method, and Figures 4 and 5 are FIG. 3 is a diagram showing a preferred application example of the present invention. 1... Interlayer insulation layer using polyimide resin, 2
. . . Through hole, 3 . . . Stepped portion of interlayer insulating layer, 4 . . . Upper layer electrode, 5 .

Claims (1)

【特許請求の範囲】[Claims] 1 下層電極配線パターンと、感光性ポリイミド
樹脂によつて形成された層間絶縁層と、上層電極
配線パターンとから成る多層配線構造において、
該層間絶縁層の段差部分の下層に該下層電極配線
パターンに加えて疑似電極を設けたことを特徴と
する多層配線構造。
1. In a multilayer wiring structure consisting of a lower layer electrode wiring pattern, an interlayer insulating layer formed of a photosensitive polyimide resin, and an upper layer electrode wiring pattern,
A multilayer wiring structure characterized in that, in addition to the lower layer electrode wiring pattern, a pseudo electrode is provided below the stepped portion of the interlayer insulating layer.
JP10379383A 1983-06-10 1983-06-10 Multilayer interconnection method Granted JPS59228736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10379383A JPS59228736A (en) 1983-06-10 1983-06-10 Multilayer interconnection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10379383A JPS59228736A (en) 1983-06-10 1983-06-10 Multilayer interconnection method

Publications (2)

Publication Number Publication Date
JPS59228736A JPS59228736A (en) 1984-12-22
JPH0337734B2 true JPH0337734B2 (en) 1991-06-06

Family

ID=14363274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10379383A Granted JPS59228736A (en) 1983-06-10 1983-06-10 Multilayer interconnection method

Country Status (1)

Country Link
JP (1) JPS59228736A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61193454A (en) * 1985-02-20 1986-08-27 Mitsubishi Electric Corp Semiconductor device
JPH079937B2 (en) * 1987-07-07 1995-02-01 日本電気株式会社 Wiring structure of semiconductor device
JPH0543565U (en) * 1991-11-13 1993-06-11 三洋電機株式会社 Multi-beam semiconductor laser device

Also Published As

Publication number Publication date
JPS59228736A (en) 1984-12-22

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