JPH0344502B2 - - Google Patents
Info
- Publication number
- JPH0344502B2 JPH0344502B2 JP57171438A JP17143882A JPH0344502B2 JP H0344502 B2 JPH0344502 B2 JP H0344502B2 JP 57171438 A JP57171438 A JP 57171438A JP 17143882 A JP17143882 A JP 17143882A JP H0344502 B2 JPH0344502 B2 JP H0344502B2
- Authority
- JP
- Japan
- Prior art keywords
- gto
- switch
- gate
- power supply
- auxiliary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000002457 bidirectional effect Effects 0.000 claims description 13
- 230000003321 amplification Effects 0.000 claims description 7
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
- H02M1/096—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices the power supply of the control circuit being connected in parallel to the main switching element
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
- Thyristor Switches And Gates (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】
本発明は、増幅ゲート構造のGTO（ゲートター
ンオフサイリスタ）のターンオン，ターンオフ制
御に用いるゲートドライブ回路に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate drive circuit used for turn-on and turn-off control of a GTO (gate turn-off thyristor) having an amplification gate structure.
GTOは、通常のサイリスタに比べてゲート点
弧電流が大きく、ゲートドライブ回路が大型とな
る。これを改善するものとして増幅ゲート構造の
GTOがある。この種GTOは、通常の増幅ゲート
形サイリスタの場合と動作原理は同じで、ただ一
般的に補助サイリスタと称される部分もGTO構
造となつている点が異なる。 GTO has a larger gate firing current than a normal thyristor, and the gate drive circuit is larger. To improve this, an amplification gate structure is proposed.
There is GTO. This type of GTO has the same operating principle as a normal amplification gate type thyristor, except that the part generally called the auxiliary thyristor also has a GTO structure.
第１図は増幅ゲート形GTOのドライブ回路の
一例を示すもので、Qmは主GTO，Qaは補助
GTOであり、GTOのカソード（主GTO Qmの
カソード）とオンゲート電極（補助GTO Qaの
ゲート）の間にオン電源E10がオンスイツチS1を
介して接続されるとともに、オフ電源E20がオフ
スイツチS2を介して図示極性に接続されている。
また、補助GTO Qaのゲート，カソード間にダ
イオードD1が接続されている。このダイオード
D1の電圧降下分が補助GTO Qaのゲート，カソ
ード間に逆バイアス電圧として加わり、ターンオ
フする。 Figure 1 shows an example of the drive circuit of an amplified gate type GTO, where Qm is the main GTO and Qa is the auxiliary GTO.
GTO, the on power supply E 10 is connected between the cathode of the GTO (cathode of the main GTO Qm) and the on gate electrode (the gate of the auxiliary GTO Qa) via the on switch S 1 , and the off power supply E 20 is connected via the off switch S 2 connected to the polarity shown.
Furthermore, a diode D1 is connected between the gate and cathode of the auxiliary GTO Qa. this diode
The voltage drop of D1 is applied as a reverse bias voltage between the gate and cathode of auxiliary GTO Qa, turning it off.
ところで、一般に補助GTO部分の点弧感度を
高めて行くとダイオード１個分の逆バイアスでは
不足するため、ダイオードを複数個直列に接続し
たり、第２図に示すようにツエナーダイオード
ZD1とダイオードD1を組み合わせてバイアス電圧
を大きくする方法がとられる。 By the way, in general, when increasing the ignition sensitivity of the auxiliary GTO part, the reverse bias of one diode is insufficient, so it is necessary to connect multiple diodes in series or use a Zener diode as shown in Figure 2.
A method is used to increase the bias voltage by combining ZD 1 and diode D 1 .
この場合、ダイオードD1はオンゲート電流が
直接主GTO Qmのゲートに流れ込むのを阻止す
る働きをする。 In this case, diode D 1 serves to prevent the on-gate current from flowing directly into the gate of main GTO Qm.
しかし、このような方法では、オフゲート電流
の大部分が逆バイアス用の素子、つまりツエナー
ダイオードZD1に流れるため、その損失が増大す
るという欠点がある。 However, this method has the disadvantage that most of the off-gate current flows through the reverse bias element, that is, the Zener diode ZD 1 , resulting in increased loss.
第３図は増幅ゲート形GTOのドライブ回路の
他の例を示すもので、主GTO Qmと補助GTO
Qaをターンオフさせるために別個のオフ電源
E21，E22を備えている。主GTO用のオフ電源E21
と補助GTO用のオフ電源E22とはオフスイツチ
S2，S′2を直列に介して接続され、両スイツチS2，
S2′の接続点が補助GTO Qaのカソード（主GTO
Qmのゲート）に接続されている。なお、カソー
ドとオンゲート電極の間にオン電源E10がオンス
イツチS1を介して接続されていることは第１図，
第２図と同様である。 Figure 3 shows another example of the drive circuit for an amplified gate type GTO, showing the main GTO Qm and the auxiliary GTO.
Separate off power supply to turn off Qa
Equipped with E 21 and E 22 . Off power supply E 21 for main GTO
and off power supply for auxiliary GTO E 22 and off switch
S 2 , S′ 2 are connected in series, and both switches S 2 ,
The connection point of S 2 ′ is the cathode of the auxiliary GTO Qa (main GTO
Qm gate). Note that the on-power source E 10 is connected between the cathode and the on-gate electrode via the on-switch S 1 as shown in Figure 1.
It is similar to FIG.
しかし、この回路構成では、第４図に示すよう
に主GTOのゲートと補助GTOのゲートは同一の
Ｐベース上に形成されているため、オフの期間
中、dv／dt耐量を考慮してスイツチを閉路した
ままにするとＰベース層４の横方向抵抗Ｒを通し
て補助GTO用のオフ電源E22により電流が定常的
に流れ、オフ時の定常ロスが増大する。 However, in this circuit configuration, the gate of the main GTO and the gate of the auxiliary GTO are formed on the same P base as shown in Figure 4, so during the off period, the switch is switched in consideration of dv/dt tolerance. If the circuit is left closed, a current steadily flows through the lateral resistance R of the P base layer 4 due to the off-power supply E 22 for the auxiliary GTO, and the steady-state loss during off-time increases.
なお、第４図において、１は補強用タングステ
ン板、２はＰ層（アノードエミツタ）、３はＮ層、
４はＰ層（カソードベース）、５及び６はカソー
ドエミツタ、７及び８はＰ層４に形成された埋込
みゲート層、９はオンゲート電極、１０はカソー
ド電極、１１は補助GTOのカソードと主GTOの
ゲートを接続する電極、Emは主回路電源、Ｚは
負荷である。 In addition, in FIG. 4, 1 is a reinforcing tungsten plate, 2 is a P layer (anode emitter), 3 is an N layer,
4 is a P layer (cathode base), 5 and 6 are cathode emitters, 7 and 8 are buried gate layers formed in the P layer 4, 9 is an on-gate electrode, 10 is a cathode electrode, 11 is an auxiliary GTO cathode and a main The electrode connecting the gate of GTO, Em is the main circuit power supply, and Z is the load.
上記のような定常ロスの増大を避けるため、補
助GTO用オフ電源E22を可変電圧とし、定常状態
ではオフ電源E22の電圧を下げて損失を少なくす
ることが考えられるが、そうすると増幅ゲート部
のdv／dt耐量が低下し、もし点弧すると第４図
に破線で示すように電流が流れて、素子ばかりで
なく、場合によつてはドライブ回路までも破損す
るおそれがある。 In order to avoid the increase in steady-state loss as described above, it is conceivable to make the off-power supply E 22 for the auxiliary GTO a variable voltage and lower the voltage of the off-power supply E 22 in the steady state to reduce the loss. The dv/dt withstand capability of the device decreases, and if the device is ignited, a current will flow as shown by the broken line in FIG. 4, potentially damaging not only the device but also the drive circuit in some cases.
なお、第４図では埋込みゲート形のものを示し
たが、分割カソード形GTOの場合にも全く同様
である。 Although FIG. 4 shows a buried gate type GTO, the same applies to a split cathode type GTO.
本発明は上記のような欠点を除去するためにな
されたもので、主GTO用オフ電源と補助GTO用
オフ電源を直列接続し、その接続点と補助GTO
のカソードの間に双方向スイツチを接続するとと
もに、オフ電源の直列回路にオフスイツチを挿設
することにより、定常ロスの低減が図れ、充分な
dv／dt耐量を確保できる増幅ゲート形GTOのド
ライブ回路を提供することを目的とする。 The present invention was made in order to eliminate the above-mentioned drawbacks, and the main GTO off power supply and the auxiliary GTO off power supply are connected in series, and the connection point and the auxiliary GTO off power supply are connected in series.
By connecting a bidirectional switch between the cathodes of the
The purpose of this invention is to provide a drive circuit for an amplified gate type GTO that can ensure dv/dt tolerance.
以下、本発明を図示の実施例に基づいて詳細に
説明する。 Hereinafter, the present invention will be explained in detail based on illustrated embodiments.
第５図は本発明の一実施例を示すもので、Qm
は主GTO、Qaは補助GTO、E10はオン電源、E21
は主GTO用オフ電源、E22は補助GTO用オフ電
源、S1はオンスイツチ、S2′はオフスイツチ、S3
は双方向スイツチである。前記オン電源E10はオ
ンスイツチS1を介してカソードとオンゲート電極
の間に接続されている。両オフ電源E21，E22はそ
の間にオフスイツチS′2を介して直列に接続され、
オン電源E10と同様にカソードとオンゲート電極
の間に接続されている。そして、主GTO用のオ
フ電源E21の負側が双方向スイツチS3を介して補
助GTO Qaのカソード、つまり主GTO Qmのゲ
ートに接続されている。 FIG. 5 shows an embodiment of the present invention, in which Qm
is the main GTO, Qa is the auxiliary GTO, E 10 is the on power, E 21
is the off power supply for the main GTO, E 22 is the off power supply for the auxiliary GTO, S 1 is the on switch, S 2 ′ is the off switch, S 3
is a two-way switch. The on power source E10 is connected between the cathode and the on gate electrode via the on switch S1 . Both OFF power supplies E 21 and E 22 are connected in series via an OFF switch S′ 2 between them,
The on-power supply E is connected between the cathode and the on-gate electrode in the same way as 10 . The negative side of the off power supply E 21 for the main GTO is connected to the cathode of the auxiliary GTO Qa, that is, the gate of the main GTO Qm, via a bidirectional switch S 3 .
前記双方向スイツチS3は、例えば第６図に示す
ように主GTOのオフゲート電流（Igr1）を流すた
めのサイリスタTHに補助GTOオフゲート電流
（Igr2）を流すためのトランジスタTR及びダイオ
ードD2の直列回路を逆並列となるように接続し
た構成とする。ダイオードD2はトランジスタTR
のコレクターエミツタ間に逆方向電圧が印加され
るのを阻止するためのものである。 The bidirectional switch S3 includes, for example, as shown in FIG. 6, a transistor TR and a diode D2 for passing an auxiliary GTO off-gate current (I gr2 ) through a thyristor TH for causing a main GTO off-gate current (I gr1 ) to flow. The configuration is such that the series circuits are connected in antiparallel. Diode D 2 is transistor TR
This is to prevent a reverse voltage from being applied between the collector and emitter.
次に、動作について述べる。まず、GTOをタ
ーンオンするには、スイツチS′2，S3の開路状態
で、スイツチS1を閉路すると、オン電源E10によ
りオンゲート電流（Igf）が流れ、GTOはターン
オンする。 Next, the operation will be described. First, to turn on the GTO, when switches S' 2 and S 3 are open, switch S 1 is closed, and the on-gate current (I gf ) flows from the on-state power source E 10 , turning on the GTO.
一方、GTOをターンオフさせるには、スイツ
チS1を開路し、スイツチS2′，S3を閉路すると、
オフ電源E21，E22によりオフゲート電流（Igr1），
（Igr2）が各々主GTO Qmのカソード，ゲート間
と、補助GTO Qaのカソード，ゲート間に流れ、
主GTO Qm及び補助GTO Qaはオフ状態とな
る。そして、主GTO Qmのゲート，カソード間
接合が完全に回復してオフゲート電流Igr1が流れ
なくなつたならば（通常のGTOでは約10μs後）、
スイツチS3を開路する。オフスイツチS2′はオフ
期間中閉路状態に維持する。 On the other hand, to turn off the GTO, open switch S 1 and close switches S 2 ′ and S 3 .
Off-gate current (I gr1 ) due to off-power supplies E 21 and E 22 ,
(I gr2 ) flows between the cathode and gate of the main GTO Qm and between the cathode and gate of the auxiliary GTO Qa, respectively.
The main GTO Qm and the auxiliary GTO Qa are turned off. Then, once the gate-cathode junction of the main GTO Qm has completely recovered and the off-gate current I gr1 no longer flows (after about 10 μs in a normal GTO),
Open switch S3 . The off switch S 2 ' remains closed during the off period.
この結果、主GTO Qmのゲート，カソード接
合には両オフ電源E21，E22の和電圧が逆バイアス
電圧として印加され、主GTO Qmのdv／dt耐量
が確保される。一方、補助GTO Qaのゲート，
カソード間には逆バイアス電圧が印加されない
が、スイツチS3が開路しているため、第４図の破
線のような電流ループは形成されない。また、主
GTO Qmと補助GTO Qaのゲートが同一のＰベ
ース上に形成されていることから、補助GTO用
オフ電源E22よりＰベースの横方向抵抗を通して
オフ期間中に電流が流れることもなくなる。従つ
て、定常ロスは大幅に低減される。 As a result, the sum voltage of both OFF power supplies E 21 and E 22 is applied as a reverse bias voltage to the gate and cathode junction of the main GTO Qm, and the dv/dt withstand capability of the main GTO Qm is ensured. Meanwhile, the gate of auxiliary GTO Qa,
Although no reverse bias voltage is applied between the cathodes, switch S3 is open, so a current loop as shown by the broken line in FIG. 4 is not formed. Also, the main
Since the gates of GTO Qm and auxiliary GTO Qa are formed on the same P base, no current flows from the auxiliary GTO off power supply E 22 through the lateral resistance of the P base during the off period. Therefore, steady-state losses are significantly reduced.
前記実施例ではオフスイツチS′2を両オフ電源
E21，E22の直列回路における双方向スイツチS3の
接続点より補助GTO用オフ電源E22側に位置させ
たが、第７図に示すように双方向スイツチS3の接
続点より主GTO用オフ電源E21側に位置させても
よい。ただし、一般に主GTOのオフゲート電流
（Igr1）は補助GTOのオフゲート電流（Igr2）より
何倍も大きいため、第５図の位置とした方がスイ
ツチS′2は容量の小さいものですむ。 In the above embodiment, the off switch S'2 is connected to both off power supplies.
In the series circuit of E 21 and E 22 , the auxiliary GTO off power supply E 22 is located from the connection point of the bidirectional switch S 3 , but as shown in Figure 7, the connection point of the bidirectional switch S 3 is connected to the main GTO. It may be located on the off power supply E21 side. However, since the off-gate current (I gr1 ) of the main GTO is generally many times larger than the off-gate current (I gr2 ) of the auxiliary GTO, the switch S' 2 needs to have a smaller capacitance when placed in the position shown in Figure 5.
以上のように本発明によれば、オフ電源を主
GTO用と補助GTO用の２個とし、これらを直列
接続してその接続点と補助GTOのカソードの間
に双方向スイツチを接続し、オフ電源の直列回路
にオフスイツチを挿設したので、オフゲート電流
が流れる経路に損失発生の原因となる逆バイアス
用デバイスが存在せず、主GTOのゲート，カソ
ード接合の回復後の双方向スイツチの開路により
補助GTO用オフ電源からＰベースの横方向抵抗
を通る電流路が遮断されることと相俟つて定常ロ
スが大幅に低減するとともに、補助GTO用オフ
電源の小容量化が可能となる。また、オフ期間中
dv／dt等により補助GTOが誤点弧しても、主
GTO用オフ電源を通り、主回路の電源を通るル
ープ（第４図の破線）が形成されないという利点
がある。更に、主GTOが完全にターンオフ状態
になつた後、双方向スイツチを開いても、オフ期
間中オフ電源直列回路のオフスイツチが閉路して
いるため、主GTOのゲート，カソード間にはＰ
ベースの横方向抵抗を通して両オフ電源の和電圧
が逆バイアス電圧として印加されており、充分な
dv／dt耐量を確保できる。 As described above, according to the present invention, the main power supply is
There are two switches, one for GTO and one for auxiliary GTO, and they are connected in series, and a bidirectional switch is connected between the connection point and the cathode of auxiliary GTO, and an off switch is inserted in the series circuit of the off power supply, so the off-gate current There is no reverse bias device in the flow path that would cause loss, and after the main GTO gate and cathode junctions have recovered, the bidirectional switch is opened, allowing the flow to flow from the auxiliary GTO off power supply through the P-based lateral resistance. Together with the current path being cut off, steady-state loss is significantly reduced, and the capacity of the auxiliary GTO off-power supply can be reduced. Also, during the off period
Even if the auxiliary GTO fires incorrectly due to dv/dt, etc., the main
This has the advantage that a loop (broken line in Figure 4) that passes through the GTO off power supply and the main circuit power supply is not formed. Furthermore, even if the bidirectional switch is opened after the main GTO is completely turned off, the off switch of the off power supply series circuit is closed during the off period, so there is a P between the gate and cathode of the main GTO.
The sum voltage of both OFF power supplies is applied as a reverse bias voltage through the lateral resistance of the base, and a sufficient
DV/DT capacity can be secured.
第１図〜第３図は増幅ゲート構造のGTOのド
ライブ回路の従来例を示す接続図、第４図は第３
図の回路例における定常ロスの増大を説明するた
めの構成図、第５図は本発明に係る増幅ゲート形
GTOのドライブ回路の一実施例を示す接続図、
第６図は同実施例における双方向スイツチの具体
的構成を示す接続図、第７図は本発明の他の実施
例を示す接続図である。
Qm…主GTO、Qa…補助GTO、E10…オン電
源、E21…主GTO用オフ電源、E22…補助GTO用
オフ電源、S1…オンスイツチ、S2′…オフスイツ
チ、S3…双方向スイツチ。
Figures 1 to 3 are connection diagrams showing conventional examples of GTO drive circuits with amplification gate structure.
A configuration diagram for explaining the increase in steady-state loss in the circuit example shown in the figure, FIG. 5 is an amplification gate type according to the present invention.
A connection diagram showing an example of the GTO drive circuit,
FIG. 6 is a connection diagram showing a specific configuration of the bidirectional switch in the same embodiment, and FIG. 7 is a connection diagram showing another embodiment of the present invention. Qm…Main GTO, Qa…Auxiliary GTO, E 10 …On power, E 21 …Off power for main GTO, E 22 …Off power for auxiliary GTO, S 1 …On switch, S 2 ′…Off switch, S 3 …Bidirectional Switch.
Claims (1)
ート電極の間にオン電源をオンスイツチを介して
接続するとともに、主GTO用，補助GTO用の２
個のオフ電源の直列回路を接続した増幅ゲート形
GTOのドライブ回路において、直列接続した前
記両オフ電源の接続点と補助GTOのカソードの
間に双方向スイツチを接続し、また主GTO用の
オフ電源の正あるいは負側にオフスイツチを挿設
し、ターンオフ時に双方向スイツチ及びオフスイ
ツチを閉路し、一定時間後に双方向スイツチを開
路し、オフスイツチはオフ期間の間閉路状態を維
持するように制御することを特徴とする増幅ゲー
ト形GTOのドライブ回路。1 Connect the on-power supply between the cathode of the GTO with the amplification gate structure and the on-gate electrode via the on-switch, and connect the two
Amplification gate type with several off-power supply connected in series
In the GTO drive circuit, a bidirectional switch is connected between the connection point of the two series-connected OFF power supplies and the cathode of the auxiliary GTO, and an OFF switch is inserted on the positive or negative side of the OFF power supply for the main GTO, A drive circuit for an amplified gate type GTO, characterized in that a bidirectional switch and an off switch are closed during turn-off, the bidirectional switch is opened after a certain period of time, and the off switch is controlled so as to maintain a closed state during the off period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57171438A JPS5961465A (en) | 1982-09-30 | 1982-09-30 | Drive circuit for amplifying gate type gto |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57171438A JPS5961465A (en) | 1982-09-30 | 1982-09-30 | Drive circuit for amplifying gate type gto |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5961465A JPS5961465A (en) | 1984-04-07 |
| JPH0344502B2 true JPH0344502B2 (en) | 1991-07-08 |
Family
ID=15923120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57171438A Granted JPS5961465A (en) | 1982-09-30 | 1982-09-30 | Drive circuit for amplifying gate type gto |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5961465A (en) |
-
1982
- 1982-09-30 JP JP57171438A patent/JPS5961465A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5961465A (en) | 1984-04-07 |
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