JPH0347777B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to GaAs logic integrated circuits. [Technical background of the invention and its problems] Conventional GaAs logic integrated circuit (hereinafter abbreviated as GaAsIC)
As a circuit configuration method, BFL (Buffered FET
Logic), SDFL (Schottky Diode FET Logic)
Alternatively, something called DCFL (Direct Coupled FET Logic) is known, and vigorous research and development is being carried out in various places. Components of the circuit include FETs, diodes, resistors, etc. Among these, Schottky gate type FETs (MESFETs) are used as the most important FETs for realizing GaAsICs, but they can be roughly divided into two types. In other words, normally on type
FET and normally-off type FET. The former is in a conductive state between the drain and source when the gate voltage is zero with respect to the source electrode, and is also called a depletion type, and the latter is in a non-conductive state when the gate voltage is zero, and is also called an enhancement type. below,
Normally-on type FET to DFET, normally-off type
FET is called EFET. Circuits that use DFET as the basic FET are BFL and SDFL, and circuits that use EFET as the basic FET are DCFL. Figure 1 shows the circuit configuration of the BFL, Figure 2 the SDFL, and Figure 3 the DCFL. In the BFL shown in Figure 1, it becomes the driver.
DFET 11 , 11 ₁ to 11 ₄ and DFET 1 as a load
2 in series to invert the input signal V _IN . This inverted signal level is used by the next stage input gate.
Since it is composed of DFET, it cannot be used as is and requires level shifting. Therefore, a level shift circuit consisting of a source follower DFET 13, Schottky diodes ₁₄ , 141 to ₁₄₃ , and a DFET 15 as a current source is provided at the output stage. A current always flows through this level shift circuit by the DFET 15 as a current source, so power consumption is large. In the SDFL shown in FIG. 2, an inverter is configured with the DFET 21 as a driver and the DFET 22 as a load, and the level shift of the input signal is performed at the input section of the inverter. That is, shot key diodes 23, 23 ₁ , 23 ₂ for logic gates, shot key diode 24 for level shift, and DFET 2 for current source.
5 constitutes an input level shift circuit to obtain a signal level for operating the inverter driver EFET 21. This is because there is no FET equivalent to the source follower FET of the BFL, and because the Schottky diode 23 is used as a logic gate instead of the FET group 11 like the BFL, the power consumption is lower than that of the BFL. However, power must still be consumed for level shifting. In the DCFL shown in Figure 3, the driver
EFET31 is used and DFET32 is used for the load.
Therefore, the level of the output signal V _OUT can operate the gate of the next stage, and can be made level compatible with the input signal V _IN . Therefore,
It does not require a level shift circuit like BFL or SDFL, and can operate with lower power consumption. On the other hand, since an EFET is used as a driver, in order to output a low level, a DFET with a smaller current capacity than the driver must be used as the load DFET, which affects the drive capacity and slows down the operation speed. There is. FIG. 4 shows the relationship between delay time per gate and power consumption of various logic integrated circuits that have been reported to date. It is clear that DCFL has the lowest power consumption in GaAs, but BFL using DFET and
The operating speed tends to be slightly slower than SDFL. In terms of power consumption, GaAs is similar to Si.
Because it is difficult to realize a MOS structure, a CMOS circuit cannot be obtained, and even DCFL is more than an order of magnitude larger than Si-CMOS. By the way, when considering high integration of GaAsIC, the IC
Considering the heat dissipation conditions, the practical upper limit is about 1W per chip. This is a direct application of the SiIC example; in the case of GaAs, the thermal conductivity is lower than that of Si, so the upper limit may be lower than that of Si. Therefore, the number
In order to realize a GaAs LSI with more than 1000 gates, the power consumption per gate needs to be less than several 100 μW. It is impossible to achieve this with BFL or SDFL, and even if DCFL is used, it is expected to be difficult. Further, in the case of DCFL, there is a problem in that the operating speed becomes slower due to the increased load as the degree of integration increases. This is due to the small drive capacity of DCFL. Therefore, the load dependence of the propagation delay time τpd per gate is large in the case of DCFL. This poses another problem for higher integration of ICs. That is, LSI
Since the length of wiring to transmit signals from one logic gate to the next reaches several millimeters on average, the capacitance between it and the ground plane becomes a large load, and multilayer wiring The capacity of the crossover section also becomes a load. Furthermore, the output of one logic gate generally needs to be connected to the inputs of several logic gates due to the circuit configuration, and the input capacitance of the next stage also becomes a large load. These capacitive loads are 100 to 200fF/mm, 4μm x 4μm, with a 4μm width wiring.
It is estimated that 5 to 10 fF per crossover and 100 to 200 fF per fanout.If the average wiring length in the IC is 3 mm, the average fanout is 3, and the average crossover is 20, one logic gate The output capacitance incurred by In the case of a DCFL logic gate composed of an FET with a gate length of 1 μm and a gate width of about 10 to 20 μm, this corresponds to a τpd of several 100 psec, assuming a current drive capacity of several mA. Furthermore,
Considering the interface with the external circuit of the IC,
The output circuit is required to drive a load that is one order of magnitude larger than the capacitive load of the internal circuit. In order not to impair the speed of the IC in this output circuit, the drive current of the FET in the output circuit needs to be several tens of mA or more, and even if the power supply voltage is 1 to 3 V, the number of outputs of the IC is 10 to 20.
Even with just one unit, the power consumption of the output circuit alone is about 1W. As described above, it is clear that trying to achieve LSI-level integration with GaAsIC while maintaining low power consumption and high speed will be extremely difficult with currently known circuit configurations. [Object of the Invention] The present invention has been made in view of these drawbacks of conventional GaAsIC circuit configurations, and provides a basic gate circuit configuration with low power consumption per gate and high drive ability that can withstand increased loads. The purpose is to [Summary of the invention] The present invention uses an EFET as a driver and an EFET as a load.
Based on an inverter circuit using DFET, the load DFET is controlled by an input signal to turn on and off.
Turn off and perform pseudo-complementary operation. Specifically, EFET as a driver (first GaAsFET)
An inverter is constructed in which one or more level-shifting Schottky GaAs diodes are interposed between the input signal and the DFET (second GaAs FET) as a load, and a predetermined control power source is controlled by an input signal to be transferred to the second GaAs FET.
DFET that selectively supplies the gate of GaAsFET
(third GaAsFET) and a second
DFET with the gate and source commonly connected between the drain and gate of GaAsFET (fourth GaAsFET)
intervene. By setting the characteristics of each element and the potential relationship of each part, when the input signal is high and the first GaAsFET is turned on, the third GaAsFET is turned on and the second GaAsFET is connected between its gate and source. Applying a control voltage such that the voltage is below the pinch-off voltage, the second
Turn off GaAsFET. For example, the third
The saturation drain current (drain current when the gate-source voltage is zero) of GaAsFET is determined by the fourth
If it is made larger than that of the GaAsFET, the control power supply can be applied almost directly to the gate of the second GaAsFET to turn it off. Also, when the input signal is low level and the first GaAsFET is turned off, the third GaAsFET is turned off and the fourth GaAsFET is turned off.
The main power supply voltage is applied to the gate of the second GaAsFET via the GaAsFET to turn it on. [Effects of the Invention] The circuit according to the present invention has a driver as described above.
Load FET is off when FET is on, driver
Complementary operation is performed in which the load FET is on when the FET is off. As a result, no through current flows even when the driver FET is on. Also
Unlike a DCFL, the current capacity of the load FET can be increased, so when the driver FET is off, it can have the drive ability to supply sufficient load current to the next stage. Also, the third one for controlling the load FET,
Since the circuit portion of the fourth GaAsFET uses only the load FET as a load, high speed performance is not impaired even if it is a low power consumption structure with a small driving capacity. Therefore, according to the present invention, it is possible to realize a GaAsLSI that has low power consumption and is capable of high-speed operation. [Examples of the Invention] Next, the present invention will be described in detail by showing examples. FIG. 5 shows a circuit of one embodiment. The EFET (first GaAsFET) 51 serving as a driver and the DFET (second GaAsFET) 52 serving as a load are connected to the main power supply V _DD
Basically, an inverter is constructed by connecting the power and the ground in series. Drain of EFET51 and DFET5
There is a shot key for level shifting between the two sources.
GaAs diodes 54, 54 ₁ and 54 ₂ are provided. The gate of DFET52 as a load is DFET
It is connected to the control power supply V _SS through the (third GaAsFET) 53, and connected to the drain, that is, the main power supply V _DD through the DFET (fourth GaAsFET) 55 whose gate and source are commonly connected. . here
DFET53 has a saturation drain current of DFET55
is set to be larger than that of . Also, the control power supply V _SS is 0<V _SS < with respect to the main power supply V _DD .
It is set to a predetermined value called V _DD . input signal
At the same time, V _IN is supplied to the gate of EFET 51 via Schottky GaAs diode 56.
It is also designed to be directly supplied to the gate of DFET53. The output signal V _OUT is taken out from the drain of EFET 51. The operation of this circuit can be explained as follows. First, when the input signal V _IN is at a high level V _H , the driver EFET 51 and DFET 53 are turned on (conductive state). The condition is expressed as V _H > V _SS +V _P2 V _H −V _D > V _th , where V _P2 is the pinch-off voltage of DFET 53 and V _th is the threshold voltage of EFET 51. However, V _P2 is negative, V _th is positive,
Further, V _D is the voltage across the diode 56 (approximately the rising voltage). At this time, since the DFET 53 is on and its saturated drain current is larger than that of the DFET 55, the drain potential of the DFET 53 becomes approximately V _SS , which is applied to the gate of the DFET 52 as a load. On the other hand, since EFET51 is on, if
If DFET52 is on, the main power supply V _DD to DFET
Current flows through 52 → diodes 54 ₁ , 54 ₂ → EFET 51 to ground. At this time, assuming that the output end potential is V _OUT1 and the voltage drop across the diodes 54 ₁ and 54 ₂ is 2×V _D , the source potential of the DFET 52 is V _OUT1 +2×V _D. DFET52 pinch-off voltage V _P1 (negative)
Then, when V _SS <V _OUT1 +2×V _D +V _P1 is satisfied, the DFET 52 becomes off (non-conductive state). A sufficient condition for this is that V _OUT is 0, so V _SS <2×V _D +V _P1 '. Thus, by satisfying the condition ~', when the input signal V _IN is at the high level V _H , regardless of the past state of the DFET 52, the EFET 5
1 is on and DFET52 is off. Next, when the input signal V _IN is at a low level V _L ,
DFET53 and EFET51 are turned off. The condition is expressed as V _L <V _SS +V _P2 V _L −V _D <V _th . At this time, since the DFET 53 is turned off, its drain potential becomes approximately the main power supply V _DD potential, which is applied to the gate of the DFET 52 .
As a result, the DFET 52 is turned on and its source potential becomes approximately _VDD . Therefore, the output signal V _OUT2 becomes V _OUT2 =V _DD -2×V _D. As described above, when the input is at a high level _VH , the output is approximately 0 (ground potential), and when the input is at a low level _VL , the output is at the high level expressed by the formula. To summarize the conditions for the above operation, V _H >V _SS +V _P2 V _H −V _D >V _th V _SS <2×V _D +V _P1 ′ V _L <V _SS +V _P2 V _L −V _D <V _th V _H ≡V _OUT2 = V _DD −2×V _D V _L ≡V _OUT1 0. In the above formula, it is assumed that a potential equivalent to the rising voltage in the forward direction of the diode is generated in the circuit, but it is sufficient that a small current flows through the diode to satisfy this requirement. In this embodiment, EFET 51 and DFET 52 are such that when one is on, the other is off, and the main power supply V _DD
→DFET52 →Diode 54 ₁ , 54 ₂ →EFET
52 → There is almost no current flowing between the earth and ground. In other words
Since the EFET 51 and DFET 52 operate in a complementary manner, the power consumption here is extremely small. Also, to increase the drive capacity of the output section, DFET52 and EFET51
However, even if the drive capacity is increased, the increase in power consumption in this part is small because complementary operation is performed as described above. On the other hand, main power supply V _DD →DFET55→DFET53→
The circuit section of the control power supply V _SS basically performs inversion operation and level shift operation, but its load is
Since it is only the gate of DFET52, high speed performance is not impaired even if it is a low power consumption structure with a small driving capacity. The next thing to consider is power consumption due to current flowing in from the previous stage (equivalent to current flowing out to the next stage). This is only a problem when the input signal V _IN is at a high level V _H . Regarding this point, if the clamp voltage of the EFET51 (voltage between the gate and source when current flows from the gate to the source) is V _CL , by satisfying V _H < V _D + V _CL , no current flows and power consumption is reduced. can be eliminated. As described above, it has become clear that the circuit of this example has the characteristics of large driving capacity and low power consumption. Specifically, for example, by setting V _P1 = −0.5V V _P2 = −0.5V V _th = 0.2V V _D = 0.8V V _CL = 0.7V V _DD = 3V V _SS = 1V, all of the equations ~ can be satisfied. Therefore, the inverter operation of the circuit of this embodiment is performed normally. Next, considering the above operating conditions, we prototyped an inverter circuit and a ring oscillator circuit using it.
When a load capacitance is applied, the propagation delay time and power consumption per gate are measured.For comparison, a ring oscillator circuit using the E/D type DCFL shown in Figure 3 is prototyped and its characteristics are measured. did.
The data will be explained below. The active layers for the FET and Schottky diode were formed by direct ion implantation of ²⁸ Si ⁺ into a Cr-doped semi-insulating GaAs substrate. The injection conditions are as shown in Table 1. The device dimensions of the example circuit are shown in Table 2.
The device dimensions of the comparative example circuits are shown in Table 3. In order to obtain the desired FET and Schottky diode characteristics, a capsule annealing was then performed at 850° C. for 15 minutes in an atmosphere of AsH ₃ (1%) + Ar. Next, an AuGe ohmic electrode is formed and then used as the short key gate electrode of the FET and the short key electrode of the short key diode.
The pinch-off voltage and threshold voltage of the FET are controlled by depositing Pt and using sintering at 400°C.
0.2V, and the DFET pinch-off voltage was set to −0.5V. [Table] [Table] [Table] The ring oscillator circuit has 15 stages, and a square Schottky diode with a side of 50 μm is inserted between the output line and the ground terminal as a capacitive load in each stage.
The circuit diagram is shown in FIG. Measure the ring oscillator oscillation waveform and determine the propagation delay time τpd, power consumption Pd, and logic amplitude ΔV per stage.
Table 4 shows the results. [Table] The load capacitance of each stage of the ring oscillator is several pF ~
It is approximately 10pF, which is close to the internal circuit load and external circuit load conditions expected in highly integrated GaAsLSIs, and the measurement results in Table 4 are based on actual GaAsLSIs.
It can be thought of as showing the characteristics inside. The circuit of this embodiment has an E/D ratio of τpd/pd product.
It has become clear that the circuit is less than 1/5 that of the type DCFL, and has excellent high speed and low power consumption. Moreover, the logic amplitude is large at 1.41V, which is 2.5 times that of DCFL. Naturally, it is presumed that the noise margin is large, but when the DC transfer curve of the circuit of this embodiment was measured, it was as shown in FIG. As is clear from the figure, the characteristics are extremely good, and the noise margin is 0.6V or more on the low level side.
0.5V or more can be expected on the high level side. In the circuit of this example, EFET51 and DFET
Although the DFET 55 is not essential for the complementary operation of the DFET 52, it is of great significance in speeding up the operation when the DFET 52 is turned on from off. Also, Schottky diode 56
Similarly, although it is not essential, since the logic amplitude is large, if it is not present, the clamp effect of the EFET 51 will cause current to flow when the input signal level exceeds the clamp voltage of the EFET, resulting in increased power consumption. Therefore, the Schottky diode 56 functions effectively in achieving a low power consumption structure. Furthermore, as is clear from FIG. 5, the circuit of this embodiment uses only one EFET, which is difficult to control in manufacturing process, and all the others are DFETs, which are easy to manufacture. As a result, the manufacturing yield of the circuit of this embodiment can be considered to be basically at the same level as that of the E/D type DCFL, and the performance/price ratio of the IC is high. The reason why quasi-complementary operation can be achieved with just one EFET, which has a low manufacturing yield, is due to the presence of the diode 54 and the supply of the control power supply V _SS .
The need for a controlled power supply V _SS does not diminish the advantages of the present invention. This is because the control power supply V _SS always has a relationship of 0 < V _SS < V _DD with respect to the main power supply V _DD , and the IC
This is because the control power supply V _SS can be obtained internally by reducing the voltage of the main power supply V _DD using, for example, a Schottky diode, and the IC can be operated from the outside as a single power supply operation. The circuit of the present invention has the power supply voltages V _DD and V _SS , the number of Schottky diodes 54 and 56, the reverse saturation current (this depends on the diode junction area),
The logic amplitude can also be increased by changing the pinch-off voltage of the DFET and the threshold voltage of the EFET. Therefore, it is possible to operate at a TTL compatible level, and the problem of the interface method between GaAsIC and other circuits can be solved. Furthermore, when it is desired to increase the drive capability for line drive, etc., it is sufficient to increase the gate widths of the EFET 51 and DFET 52, and the advantage is that the power consumption does not increase due to complementary operation. As detailed above, according to the present invention, the conventional
With the same number of devices as BFLs and SDFLs and the same process technology as DCFLs, it is possible to achieve significantly superior high speed, large drive capacity, and low power consumption compared to these circuits, and the role it will play in the conversion of GaAsIC to LSI. Extremely large. Note that although the above explanation has focused on examples using GaAsIC, since MES FETs are used as constituent FETs, the present invention can also be applied to cases where other semiconductor materials such as InP, Si, etc. are used. It is possible. Also, in Figure 5, DFET55 is DFET53
Since it has the role of a load, the same effect can be obtained even if it is replaced with a resistor.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a logic gate circuit using GaAs MES FETs called BFL, Figure 2 is a circuit diagram of a logic gate circuit using GaAs MES FETs called SDFL, and Figure 3 is a circuit diagram of a logic gate circuit using GaAs MES FETs called DCFL.
A circuit diagram of a logic gate circuit using MES FETs, Fig. 4 is a diagram showing the speed and power consumption range of various conventional logic circuits, and Fig. 5 is a diagram of an embodiment of the present invention.
A circuit diagram of the basic logic circuit for GaAsIC. Figure 6 is a diagram showing a ring oscillator prototyped using the circuit in Figure 5. Figure 7 is the input-output characteristics measured by actually prototyping the circuit in Figure 5. FIG. 51...EFET (first GaAsFET), 52...
DFET (second GaAsFET), 53...DFET (third
GaAsFET), 55...DFET (fourth
GaAsFET), 54 ₁ , 54 ₂ , 56... Schottky GaAs diode, V _DD ... main power supply, V _SS ... control power supply.

Claims (1)

[Claims] 1. A first normally-off GaAsFET serving as a driver of an inverter circuit, a second normally-on GaAsFET serving as a load, and a level shift interposed between these first and second GaAsFETs. a GaAs diode for the second GaAs FET, and its drain side connected to the gate of the second GaAsFET.
A third normally-on type GaAsFET whose gate is controlled by an input signal supplied to the gate of the GaAsFET and selectively supplies a predetermined controlled power source to the gate of the second GaAsFET, and a common connection between the gate and the source. and a normally-on type fourth transistor interposed between the drain and gate of the second GaAsFET.
GaAsFETs are integrated, and the first
The output terminal of the inverter circuit is provided at the connection between the GaAsFET and the GaAs diode for level shifting, and when the input signal is at a high level, the first and third GaAsFETs are turned on and the second GaAsFET is turned on.
A GaAs logic integrated circuit characterized in that the potential relationship of each part is set so that when the GaAsFET is turned off and the input signal is at a low level, the first and third GaAsFETs are turned off and the second GaAsFET is turned on. . 2. The GaAs FET according to claim 1, wherein the third GaAsFET has a saturation drain current set to be larger than that of the fourth GaAsFET.
Logic integrated circuit.