JPH0347778B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to GaAs logic integrated circuits. [Technical background of the invention and its problems] Conventional GaAs logic integrated circuit (hereinafter abbreviated as GaAsIC)
As a circuit configuration method, BFL (Buffered FET
Logic), SDFL (Schottky Diode FET Logic)
Alternatively, something called DCFL (Direct Coupled FET Logic) is known, and vigorous research and development is being carried out in various places. Components of the circuit include FETs, diodes, resistors, etc. Among these, Schottky gate type FETs (MESFETs) are used as the most important FETs for realizing GaAsICs, but they can be roughly divided into two types. That is, normally-on type FET and normally-off type FET. The former is in a conductive state between the drain and source when the gate voltage is zero with respect to the source electrode, and is also called a depletion type, and the latter is in a non-conductive state when the gate voltage is zero, and is also called an enhancement type. Below, normally-on type FET is called DFET, and normally-off type FET is called DFET.
It is called EFET. A circuit that uses DFET as a basic FET
It is DCFL. BEL in Figure 1, SDFL in Figure 2,
Figure 3 shows the circuit configuration of the DCFL. In the BFL shown in Figure 1, it becomes the driver.
DFET 11 (11 ₁ to 11 ₄ ) and DFET as load
12 in series to invert the input signal V _IN .
This inverted signal level is used by the next stage input gate.
Since it is composed of DFET, it cannot be used as is and requires level shifting. Therefore, a level shift circuit consisting of a source follower DFET 13, Schottky diodes 14 (14 ₁ to 14 ₃ ), and a DFET 15 as a current source is provided at the output stage. A current always flows through this level shift circuit by the DFET 15 as a current source, so power consumption is large. In the SDFL shown in FIG. 2, an inverter is configured with the DFET 21 as a driver and the DFET 22 as a load, and the level shift of the input signal is performed at the input section of the inverter. That is, the Schottky diode 23 (23 ₁ , 23 ₂ ) for the logic gate, the Schottky diode 24 for the level shift, and the Schottky diode 24 for the current source.
The DFET 25 constitutes an input level shift circuit to obtain a signal level for operating the inverter driver EFET 21. This is because there is no FET equivalent to the source follower FET of the BFL, and because the Schottky diode 23 is used as a logic gate instead of the FET group 11 like the BFL, the power consumption is lower than that of the BFL. ,
However, power must still be consumed for level shifting. In the DCFL shown in Figure 3, the driver
EFET31 is used and DFET32 is used for the load.
Therefore, the level of the output signal V _OUT can operate the gate of the next stage, and can be made level compatible with the input signal V _IN . Therefore,
It does not require a level shift circuit like BFL or SDFL, and can operate with lower power consumption. On the other hand, since an EFET is used as a driver, in order to output a low level, it is necessary to use a load DFET with a smaller current capacity than the driver, which affects the drive capacity and slows down the operation speed. There is. FIG. 4 shows the relationship between delay time per gate and power consumption of various logic integrated circuits that have been reported to date. It is clear that DCFL has the lowest power consumption in GaAs, but BFL using DFET and
The operating speed tends to be slightly slower than SDFL. In terms of power consumption, GaAs is similar to Si.
CMOS because it is difficult to realize FET with MOS structure
The circuit cannot be obtained and even DCFL is 1 lower than Si-CMOS.
It has grown by more than an order of magnitude. By the way, when considering high integration of GaAsIC, the IC
Considering the heat dissipation conditions, the practical upper limit is about 1W per chip. This is a direct application of the SiIC example; in the case of GaAs, the thermal conductivity is lower than that of Si, so the upper limit may be lower than that of Si. Therefore, the number
In order to realize a GaAs LSI with more than 1000 gates, the power consumption per gate needs to be less than several 100 μW. It is impossible to achieve this with BFL or SDFL, and even if DCFL is used, it is expected to be difficult. Further, in the case of DCFL, there is a problem in that the operating speed becomes slower due to the increased load as the degree of integration increases. This is due to the small drive capacity of DCFL. Therefore, the load dependence of the propagation delay time τpd per gate is large in the case of DCFL. This poses another problem for higher integration of ICs. That is, LSI
Since the length of wiring to transmit signals from one logic gate to the next reaches several millimeters on average, the capacitance between it and the ground plane becomes a large load, and multilayer wiring The capacity of the crossover section also becomes a load. Furthermore, the output of one logic gate generally needs to be connected to the inputs of several logic gates due to the circuit configuration, and the input capacitance of the next stage also becomes a large load. These capacitive loads are 100 to 200fF/mm, 4μm/4μm with 4μm width wiring.
It is estimated to be 5 to 10 fF/piece for a crossover of
The average wiring length inside is 3mm, the average fanout is 3,
If the average number of crossovers is 20, the load capacitance carried by one logic gate is 0.7 to 1.4 pF. In the case of a DCFL logic gate composed of an FET with a gate length of 1 μm and a gate width of about 10 to 20 μm, this corresponds to a τpd of several 100 psec, assuming a current drive capacity of several mA. Furthermore, when considering the interface with the external circuit of the IC, the output circuit needs to drive a load that is at least one order of magnitude larger than the capacitive load of the internal circuit. If we do not lose the speed of the IC in this output circuit,
The drive current of the FET in the output circuit is required to be several tens of mA or more, and even if the power supply voltage is 1 to 3 V, the number of outputs of the IC is 10.
Even with ~20 units, the power consumption of the output circuit alone will be about 1W. As described above, it is clear that trying to achieve LSI-level integration with GaAsIC while maintaining low power consumption and high speed will be extremely difficult with currently known circuit configurations. [Object of the Invention] The present invention has been made in view of these drawbacks of conventional GaAsIC circuit configurations, and provides a basic gate circuit configuration with low power consumption per gate and high drive ability that can withstand increased loads. The purpose is to [Summary of the invention] The present invention uses an EFET as a driver and an EFET as a load.
Based on an inverter circuit using a DFET, the load DFET is controlled by an input signal to turn on and off.
Turn off and perform pseudo-complementary operation. Specifically, EFET as a driver (first
GaAsFET) and DFET as load (second
An inverter is configured in which one or more level-shifting shot-key GaAs diodes are interposed between the DFET (GaAsFET) and one or more level-shifting shot-key GaAs diodes are interposed between the DFET (second In addition, a DFET (fourth GaAsFET) is provided with the gate and source commonly connected between the drain and gate of the second GaAsFET.
GaAsFET). In addition, prepare a DFET (fifth GaAsFET) whose gate and source are commonly connected, and connect its source to the gate of the first GaAsFET and its drain to the signal input terminal, and further DFET whose gate and source are commonly connected. (6th
GaAsFET) and its source as a third
Connect the gate and drain of the GaAsFET to the signal input terminal. By setting the characteristics of each element and the potential relationship of each part, when the input signal is at a high level and the first GaAsFET is turned on, the third GaAsFET is
Turn on the second GaAsFET, apply a control voltage to the second GaAsFET so that its gate-source voltage is below the pinch-off voltage, and turn on the second GaAsFET.
Turn off. For example, if the saturation drain current (drain current when the gate-source voltage is zero) of the third GaAsFET is made larger than that of the fourth GaAsFET, the control power supply can be applied almost directly to the gate of the second GaAsFET. You can turn this off by giving: Also, when the input signal is low level and the first GaAsFET is turned off, the third GaAsFET is turned off.
The GaAsFET is turned off and the main power supply voltage is applied to the gate of the second GaAsFET via the fourth GaAsFET to turn it on. [Effects of the Invention] The circuit according to the present invention has a driver as described above.
Load FET is off when FET is on, driver
Complementary operation is performed in which the load FET is on when the FET is off. As a result, no through current flows even when the driver FET is on. Also
Unlike a DCFL, the current capacity of the load FET can be increased, so when the driver FET is off, it can have the drive ability to supply sufficient load current to the next stage. In addition, the third and fourth
Since the GaAsFET circuit uses only the load FET as a load, high speed performance is not compromised even when the drive capacity is low and the power consumption is low. Further, fifth and sixth GaAsFETs are connected between the gates of the first and third GaAsFETs and the signal input terminals, respectively.
By interposing the gate, it is possible to effectively suppress the flow of current from the gates of the first and third GaAsFETs even when the input signal level is higher than the clamp voltage of the first and third GaAsFETs, and also to reduce the main power supply voltage level. When the voltage is increased, it is possible to prevent the low level output from rising and to perform stable inverter operation. Therefore, according to the present invention, it is possible to realize a GaAsLSI that has low power consumption and is capable of high-speed operation. [Examples of the Invention] Next, the present invention will be specifically described with reference to Examples. FIG. 5 shows a circuit of one embodiment. The EFET (first GaAsFET) 51 serving as a driver and the DFET (second GaAsFET) 52 serving as a load are connected to the main power supply.
Basically, an inverter is configured by connecting in series between V _DD and ground. EFET51 drain and
Level shifting shot key GaAs diodes 54, 54 ₁ and 54 ₂ are provided between the sources of the DFET 52. The gate of DFET52 as a load is
It is connected to the control power supply V _SS through a DFET (third GaAsFET) 53, and connected to the drain, that is, the main power supply V _DD , through a DFET (fourth GaAsFET) 55 whose gate and source are commonly connected. There is.
Here, the saturated drain current of DFET53 is
It is set to be larger than that of DFET55. Further, the control power supply V _SS is set to a predetermined value such that 0<V _SS <V _DD with respect to the main power supply V _DD .
The input signal V _IN is input through a DFET (fifth GaAsFET) 56a whose gate and source are commonly connected.
At the same time that it is supplied to the gate of EFET51, another
DFET with two gates and sources commonly connected
(6th GaAsFET) DFET53 via 56b
It is also being supplied to the gates of The output signal V _OUT is taken out from the drain of EFET 51. The operation of this circuit can be explained as follows. First, when the input signal V _IN is at a high level (V _H ),
The driver EFET 51 and DFET 53 are turned on (conducting). The condition is expressed as V _H −V _FETb > V _SS +V _P2 V _H −V _FETa > V _th , where V _P2 is the pinch-off voltage of DFET 53 and V _th is the threshold voltage of EFET 51. However, V _FETa is the drain-source voltage of the DFET 56a, and V _FETb is the drain-source voltage of the DFET 56b. these two
When the input signal applied to the gates of EFET51 and DFET53 exceeds the clamp voltage between the gate and source, and current begins to flow from the gate to the source, the DFET56a and 56b close their own drains.
Increase the potential difference between sources, EFET51, DFET
It operates as a limiter so that a current exceeding a certain level does not flow through the gate of 53. Its threshold current is equal to the saturated drain current of DFETs 56a and 56b. Therefore, this saturation current value is EFET51,
_{The DFET56a , _}
DFET56b should be designed in advance so that the input signal is
When the voltage is below the clamp voltage of EFET 51 and DFET 53, it is applied almost directly to each gate, and when it exceeds the clamp voltage, each gate voltage is held at the clamp voltage and the current flowing into the gate does not increase any further. The clamp voltage is naturally larger than V _th and V _P2 and does not affect the on/off operations of EFET 51 and DFET 53. Therefore, the equation can be considered in the case where the gate voltage is less than the clamp voltage and can be rewritten as V _H > V _SS +V _P2 ′ V _H > V _th ′. At this time, since DFET 53 is on and its saturated drain current is larger than that of DFET 55, the drain current of DFET 53 becomes approximately V _SS , which is applied to the gate of DFET 52 as a load. On the other hand, since EFET51 is on, if
If DFET52 is on, the main power supply V _DD to DFET
Current flows through 52 → diodes 54 ₁ , 54 ₂ → EFET 51 to ground. At this time, assuming that the output end potential is V _OUT1 and the voltage drop across the diodes 54 ₁ and 54 ₂ is 2×V _D , the source potential of the DFET 52 is V _OUT1 +2×V _D. DFET52 pinch-off voltage V _P1 (negative)
Then, when V _SS <V _OUT1 +2×V _D +V _P1 is satisfied, the DFET 52 becomes off (non-conductive state). A sufficient condition for this is that V _OUT is 0, so V _SS <2×V _D +V _P1 '. Thus, by satisfying the condition ~', when the input signal V _IN is at the high level V _H , regardless of the past state of the DFET 52, the EFET 5
1 is on and DFET52 is off. Next, when the input signal V _IN is at a low level V _L ,
DFET53 and EFET51 are turned off. The condition is expressed as V _L <V _SS +V _P2 V _L <V _th . At this time, since the DFET 53 is turned off, its drain potential becomes approximately the main power supply V _DD potential, which is applied to the gate of the DFET 52 .
As a result, the DFET 52 is turned on and its source potential becomes approximately _VDD . Therefore, the output signal V _OUT2 becomes V _OUT2 =V _DD -2×V _D. As described above, when the input is at a high level _VH , the output is approximately 0 (ground potential), and when the input is at a low level _VL , the output is at the high level expressed by the formula. To summarize the conditions for the above operation, V _H ＞V _SS +V _P2 ′ V _H ＞V _th ′ V _SS ＜2×V _D ＋V _P1 ′ V _L ＜V _SS +V _P2 V _L ＜V _th V _H ≡V _OUT2 =V _DD -2×V _D V _L ≡V _OUT1 0. In the above formula, it is assumed that a potential equivalent to the rising voltage in the forward direction of the diode is generated in the circuit, but it is sufficient that a small current flows through the diode to satisfy this requirement. In this embodiment, EFET 51 and DFET 52 are such that when one is on, the other is off, and the main power supply V _DD
→ DFET52 → Diodes 54 ₁ , 54 ₂ → Almost no current flows with the ground. In other words, with EFET51
Since the DFET 52 performs pseudo-complementary operation, the power consumption here is extremely small. In addition, to increase the drive capacity of the output section, it is possible to increase the current drive capacity of DFET52 and EFET51, but even if the drive capacity is increased, the increase in power consumption in this part is small because complementary operation is performed as described above. be. On the other hand, main power supply V _DD →DFET55→DFET53→
The circuit section of the control power supply V _SS basically performs inversion operation and level shift operation, but its load is only on the gate of DFET52, so even if it is a low power consumption structure with small drive capacity, high speed performance will be impaired. There is no. The next thing to consider is power consumption due to current flowing in from the previous stage (equivalent to current flowing out to the next stage). This is a problem only when the input signal V _IN is at a high level V _H . Generally MESFET
In a circuit using FET, the input signal is applied to the gate of the FET, but since the gate is of the Schottky junction type, current suddenly begins to flow when the gate-source voltage exceeds the forward rising voltage of the Schottky junction. Therefore, when the input signal exceeds a certain value, power is consumed accordingly. However, in this embodiment circuit, DFET56a, DEF
By adding 56b to the gate portions of EFET 51 and DFET 53, the gate voltage will not rise any further even if the input voltage exceeds the forward rising voltage, and the gate current will not be suddenly generated. Therefore, there is almost no power consumption due to the flow of gate current as in logic circuits using conventional MESFETs. One of the features of this embodiment is that the existence of these DFETs 56a and 56b further enhances the low power consumption achieved by the complementary operation in the circuit of this embodiment. The presence of DFET 56a and DFET 56b has another effect of easing operating conditions.
FIG. 7 shows the input/output transfer characteristics (marked with ◯) of the circuit of this embodiment shown in FIG. 5, and the input/output transfer characteristics (marked with x) of the circuit excluding the DFETs 56a and 56b. According to the circuit of this embodiment, there is no rise in the output voltage even if the input voltage increases by 1V or more. DFET56a, 56
In the circuit without b, there is a rise, so V _DD
There is a limit to the voltage that can be set as 1V. However, according to the circuit of this embodiment, DFET56
Due to the functions of a and 56b, the inverter has the great advantage of being able to operate stably as an inverter even when V _DD is set to 1V or more. As described above, it has become clear that the circuit of this example has the characteristics of large drive capacity and low power consumption, and also has a wide power supply voltage range in which normal operation can be performed. Specifically, for example, by setting V _P1 = -0.5V V _P2 = -0.5V V _th = 0.2V V _D = 0.8V V _CL = 0.7V V _DD = 3V V _SS = 1V, all the equations can be satisfied. , the inverter operation of the circuit of this embodiment is performed normally. Next, considering the above operating conditions, we prototyped an inverter circuit and a ring oscillator circuit using it.
When a load capacitance is applied, the propagation delay time and power consumption per gate are measured.For comparison, a ring oscillator circuit using the E/D type DCFL shown in Figure 3 is prototyped and its characteristics are measured. did.
The data will be explained below. The active layers for the FET and Schottky diode were formed by direct ion implantation of ²⁸ Si ⁺ into a Cr-doped semi-insulating GaAs substrate. The injection conditions are as shown in Table 1. In addition, the device dimensions of the example circuit are
The device dimensions of the table and the comparative example circuit are shown in Table 3, respectively. In order to obtain the desired FET and Schottky diode characteristics, a capsule annealing was then performed at 850° C. for 15 minutes in an atmosphere of AsH ₃ (1%) + Ar. Next, an AuGe ohmic electrode is formed, and then Pt is used as the short-key gate electrode of the FET and the short-key electrode of the short-key diode.
The pinch-off voltage and threshold voltage of the FET were controlled using sintering at 400℃, and the threshold voltage of the EFET was set to 0.2V.
The pinch-off voltage of the DFET was set to −0.5V. The ring oscillator circuit had 15 stages, and a square Schottky diode with a side of 50 μm was inserted between the output line and the ground terminal as a capacitive load in each stage.
The circuit diagram is shown in FIG. Measure the ring oscillator oscillation waveform and determine the propagation delay time τpd, power consumption Pd, and logic amplitude ΔV per stage.
Table 4 shows the results. [Table] [Table] [Table] [Table] The load capacitance of each stage of the ring oscillator is several pF ~
It is approximately 10pF, which is close to the internal circuit load and external circuit load conditions expected in highly integrated GaAsLSIs, and the measurement results in Table 4 are based on actual GaAsLSIs.
It can be thought of as showing the characteristics inside. The circuit of this embodiment has an E/D ratio of τpd/pd product.
It has become clear that the circuit is less than 1/7 that of the type DCFL, and has excellent high speed and low power consumption. Moreover, the logic amplitude is large at 2.5V, which is 4.5 times that of DCFL. In the circuit of this example, EFET51 and DFET
Although the DFET 55 is not essential for the pseudo-complementary operation of the DFET 52, it is of great significance in speeding up the operation when the DFET 52 is turned on from off. Furthermore, as is clear from FIG. 5, the circuit of this embodiment uses only one EFET, which is difficult to control in manufacturing process, and all the others are DFETs, which are easy to manufacture. As a result, the manufacturing yield of the circuit of this embodiment can be considered to be basically at the same level as that of the E/D type DFET, and the performance/price ratio of the IC is high. The reason why quasi-complementary operation can be achieved with just one EFET, which has a low manufacturing yield, is due to the presence of the diode 54 and the supply of the control power supply V _SS .
The need for a controlled power supply V _SS does not diminish the advantages of the present invention. This is because the control power supply V _SS always has a relationship of 0 < V _SS < V _DD with respect to the main power supply V _DD , and the IC
This is because the control power supply V _SS can be obtained internally by reducing the voltage of the main power supply V _DD using, for example, a Schottky diode, and the IC can be operated from the outside as a single power supply operation. The circuit of the present invention can achieve this by changing the power supply voltages V _DD , V _SS , the number of Schottky diodes 54, the reverse saturation current (this depends on the diode junction area), the pinch-off voltage of the DFET, the threshold voltage of the EFET, etc. Logic amplitude can be increased. Moreover, the circuit of the present invention has DFET56a,
Since the DFET 56b prevents a clamping phenomenon from occurring at the gate of the FET, there is a large degree of freedom in changing each part to increase the logic amplitude. Therefore, the circuit of the present invention can easily be operated at a TTL compatible level.
It also solves the problem of interface methods between GaAsIC and other circuits. Also, when building a system using only GaAs ICs, noise resistance measures are important for signal transmission between IC chips, and one way to do this is to make the logic amplitude larger outside the IC than inside the IC. , the circuit of the present invention is effective for this purpose as well. Furthermore, when it is desired to increase the drive capability for line drive, etc., the gate widths of the EFET 51 and DFET 52 can be increased, and the advantage is that the power consumption does not increase due to complementary operation. As detailed above, according to the present invention, the conventional
With the number of devices comparable to BFLs and SDFLs and the process technology comparable to DCFLs, it is possible to achieve significantly superior high speed, large drive capacity, and low power consumption compared to these circuits, and GaAsIC will play an extremely important role in the development of LSI. big. Although the above explanation has focused on examples using GaAsIC, since MESFET is used as the constituent FET, the present invention can also be applied to cases where other semiconductor materials such as InP, Si, etc. are used. It is.
Furthermore, since the DFET 55 in FIG. 5 serves as a load for the DFET 53, the same effect can be obtained even if it is replaced with a resistor.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a logic gate circuit using GaAs MESFETs called BFL, Figure 2 is a circuit diagram of a logic gate circuit using GaAs MESFETs called SDFL, and Figure 3 is a circuit diagram of a logic gate circuit using GaAs MESFETs called SDFL.
A circuit diagram of a logic gate circuit using GaAs MESFET. Fig. 4 is a diagram showing the speed-power consumption range of various conventional logic circuits. Fig. 5 is a diagram of a basic logic circuit for GaAs IC according to an embodiment of the present invention. The circuit diagram, FIG. 6 is a diagram showing a ring oscillator prototyped using the circuit of FIG. 5, and FIG. 7 is the same example circuit of FIG. 5,
6 is a diagram showing input-output characteristics measured by actually fabricating a comparative example circuit excluding the DFETs 56a and 56b of FIG. 5. FIG. 51...EFET (first GaAsFET), 52...
DFET (second GaAsFET), 53...DFET (third
), 54 ₁ , 54 ₂ ... shot key
GaAs diode, 55...DFET (fourth
GaAsFET), 56a...DFET (fifth
GaAsFET), 56b...DFET (sixth
GaAsFET), V _DD …main power supply, V _SS …control power supply.

Claims (1)

[Claims] 1. A first normally-off GaAsFET serving as a driver of an inverter circuit, a second normally-on GaAsFET serving as a load, and a level shift interposed between the first and second GaAsFETs. a GaAs diode for the second GaAs FET, and its drain side connected to the gate of the second GaAsFET.
A normally-on type third GaAsFET whose gate is controlled by an input signal supplied to the gate of the GaAsFET and selectively supplies a predetermined controlled power source to the gate of the second GaAsFET is commonly connected between the gate and the source. and the drain of the second GaAsFET.
A normally-on type fourth interposed between the gates.
GaAsFET and a fifth normally-on type GaAsFET whose gate and source are commonly connected, the source side is connected to the gate of the first GaAsFET, and the drain side is connected to the signal input terminal, and the gate and source are commonly connected. and a normally-on type sixth GaAsFET whose source side is connected to the gate of the third GaAsFET and whose drain side is connected to the signal input terminal, and the first GaAsFET and a GaAs diode for level shifting are integrated. An output terminal of the inverter circuit is provided at a connection point between the first and third inverter circuits when the input signal is at a high level.
The potential relationship of each part is set so that the GaAsFET is on and the second GaAsFET is off, and when the input signal is at a low level, the first and third GaAsFETs are off and the second GaAsFET is on. Features of GaAs logic integrated circuit. 2. The GaAs FET according to claim 1, wherein the third GaAsFET has a saturation drain current set to be larger than that of the fourth GaAsFET.
Logic integrated circuit. 3 The fifth GaAsFET is set such that its saturation drain current is smaller than the current corresponding to the forward rising voltage in the gate-source diode characteristic of the first GaAsFET, and the sixth GaAsFET is 2. The GaAs logic integrated circuit according to claim 1, wherein the saturated drain current is set to be smaller than the current corresponding to the forward rising voltage in the gate-source diode characteristic of the third GaAs FET.