JPH035674B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a nonvolatile semiconductor memory device in which memory cells having floating gates and control gates are integrated in a matrix on a semiconductor substrate. The present invention relates to a nonvolatile semiconductor memory device that is selectively rewritable.

[Technical background of the invention and its problems]

Conventionally, a non-volatile semiconductor memory device having a floating gate is composed of a MOS field effect transistor having an electrically insulated floating gate and a control gate above the floating gate. A memory device having multiple storage capacities is constructed by arranging the memory elements in a matrix, with control gates commonly connected for each row to form word lines, and drains commonly connected for each column to form bit lines. .

FIG. 1 shows the main structure of a conventionally used nonvolatile semiconductor memory device having a floating gate. Figure 1 a is a plan view, b is its A-A' cross section,
Similarly, c shows the BB' cross section. Basically, it is a MOS type field effect transistor with an insulated floating gate 16 and a control gate 17.
11 is a p-type Si substrate, 12 and 13 are each n ⁺
14 and 15 are gate insulating films, and 18 is a field insulating film. Writing is performed by applying a high voltage to the control gate 17 and the drain 13 and injecting hot electrons generated near the drain into the floating gate 16. For reading, an appropriate potential is applied to the control gate 17 and the drain 13, and the drain 13 and source 1 are
This is done by detecting whether or not current flows between the two. Further, erasing is performed by, for example, irradiating ultraviolet rays or the like to release the charges accumulated in the floating gate 16.

In the structure shown in Figure 1, ultraviolet rays or the like must be used to erase information as described above, and in this case, all memory elements arranged in a matrix will be erased at the same time, allowing selective erasure. The drawback was that I couldn't do it.

In response to this, nonvolatile semiconductor memory devices that enable electrical writing and erasing have also been proposed. On the other hand, in conventional nonvolatile semiconductor memory devices, the sources of a plurality of memory elements are commonly connected by a wiring made of the same impurity diffusion layer. However, as the number of integrated memory devices increases, diffusion layer wiring
The conventional configuration in which the sources are commonly connected has a problem in that wiring resistance cannot be ignored and high-speed operation cannot be performed.

[Purpose of the invention]

An object of the present invention is to provide a nonvolatile semiconductor memory device that enables high-speed operation by arranging nonvolatile semiconductor memory elements having floating gates and control gates in a matrix.

[Summary of the invention]

In the nonvolatile semiconductor memory device according to the present invention, a plurality of memory elements each having a floating gate and a control gate are arranged in a matrix, and the sources and drains of the plurality of memory cell elements are arranged in a first direction in a predetermined direction.
It is characterized in that it is commonly connected to the layer metal wiring and the second layer metal wiring.

〔Effect of the invention〕

According to the present invention, not only the drain, which is the data terminal of the memory element, but also the source are commonly connected to the metal wiring, so the source wiring resistance is lower than that of the conventional method in which the sources are commonly connected by a diffusion layer. Therefore, a great effect can be obtained especially in performing high-speed operation in a large-scale memory device.

[Embodiments of the invention]

FIG. 2 shows the main structure of a memory device according to an embodiment of the present invention, in which a is a plan view, b, c, and d.
are the A-A', B-B' and C-C' cross sections of a, respectively. An n ⁺ type source 22 on a p-type Si substrate 21,
A drain 23 is provided, a floating gate 25 made of polycrystalline silicon is provided on the channel region between these two regions with a gate insulating film 24 interposed therebetween, and a first floating gate made of polycrystalline silicon is provided on top of the floating gate 25 made of polycrystalline silicon with a gate insulating film 26 interposed therebetween. The basic structure in which the control gate 27 is provided remains unchanged from the conventional one. In this embodiment, in addition to the above-mentioned basic structure, an area for writing and erasing information is provided separately. That is, an n-type layer 28 formed continuously with the source 22 is provided as a third control gate adjacent to the channel region, and the floating gate 25 is formed on this n-type layer 28 with a thin gate insulating film 29 interposed therebetween. Extend. Separately from the first control gate 27, a second control gate 31 made of polycrystalline silicon is provided which is insulated by the gate insulating films 26 and 30 and capacitively coupled to the floating gate 25. What is also important is that, as is clear from a and b, the floating gate 25 has an offset gate structure with respect to the source 22 and drain 23, that is, it does not cover the entire channel region, and the remaining portion is 1 control gate 27 is closed. In other words, a portion of the first control gate 27 and the floating gate 25 serve as gate electrodes for the read operation.

For example, the gate insulating films 24, 26 and 30 have a thickness of about
The gate insulating film 29 in the region where writing and erasing operations are performed is a thermal oxide film having a thickness of 800 Å, for example, about 200 Å thick. Furthermore, when arranging these elements in a matrix to form an array, the source 22 and the first control gate 27 are commonly disposed in the row direction, and the second control gate 31 is commonly disposed in the column direction. Note that the source 22, together with the drain 23, includes a floating gate 25 made of polycrystalline silicon, first and second
The n-type layer in the substrate region under the rewrite region and the second control gate 31 for making the source conductive is formed by high concentration ion implantation after forming the control gates 27 and 31. Therefore, the sources of each memory element are commonly connected through a relatively high diffusion layer resistance. Therefore, the source 22 of each memory element is formed not only by the diffusion layer but also by the first Al wiring 3 arranged in the row direction.
2 is commonly connected to each row. The drains 23 are further connected in common to each column by a second Al wiring 34 arranged in the column direction via an insulating film 33.

Next, the operation of this memory element will be explained. A drain potential V _D , a source potential V _S , a substrate potential V _sub , a first control gate potential V _CG1 , and a second control gate potential V _CG2 are applied to this memory element from the outside. Since this memory element is shown in the equivalent circuit of FIG. 3, the potential V _FG of the floating gate 25 is generally expressed by the following equation.

V _FG =C _CF1・V _CG1 +C _CF2・V _CG2 +C _S・V _S +C _D・V _D
+C _Sub・V _sub /C _CF1 +C _CF2 +C _S +C _D +C _sub However, C _CF1 and C _CF2 are the coupling capacitances between the first and second control gates 27 and 31 and the floating gate 25, respectively, and C _D , C _sub and C _S are drain 23, respectively
This is the coupling capacitance between the substrate 21, the source 22 (ie, the n-type layer 28), and the floating gate 25. C _CF1 and C _CF2 are approximately equal, and C _S is set smaller than this. From the above equation, when the drain potential V _D , substrate potential V _sub , and source potential V _S are fixed, the potential level of the floating gate 25 can take on three states using the first control gate 27 and the second control gate 31. I know what I'm getting. That is, (i) when the first control gate 27 and the second control gate 31 are both at a high potential, (ii) when either the first control gate 27 or the second control gate 31 is at a high potential and the other is at a high potential. The potential of the floating gate 25 is determined depending on the following three cases: (iii) when the first control gate 27 and the second control gate 31 are both at low potential; Therefore, if in state (i) and the source potential V _S is low, and if in state (iii) and the source potential
The film thickness of this gate insulating film 29 is set so that a tunnel current flows through the gate insulating film 29 under the floating gate 25 in the region of the n-type layer 28 only when V _S is at a high potential, and does not flow in other conditions. Depending on the selection, selective writing or erasing can be performed in this area.

In reality, the memory element shown in FIG. 2 constitutes a one element/cell memory array integrated in a matrix on a substrate as described above. For example, consider a matrix of four memory elements M ₁ to _{M 4} as shown in FIG. Source S ₁ of M ₁ and M ₂ is common, M ₃ and M ₄
Source S ₂ is also common. Similarly, the first control gate CG ₁₁ is common to M ₁ and M ₂ ;
CG ₁₂ is common to M ₃ and M ₄ . Also drain D ¹
and the second control gate CG ₂₁ is common to M ₁ and M ₃ ;
The drain D ₂ and the second control gate CG ₂₂ are M ₂ ,
Common to _M4 . In the initial state, no charge is accumulated in the floating gate of each memory element, and this state is set to, for example, "1". To write data to the memory element M ₁ , +20V is applied to the first control gate CG ₁₁ and the second control gate CG ₂₁ , and all other terminals, namely drains D ₁ , D ₂ and source S ₁ , S ₂ , the first control gate CG ₁₂ , and the second control gate CG ₂₂ are
Set to 0V. In this way, the floating gate 25 of the memory element M ₁ has a high potential, and electrons are transferred from the n-type layer 28 to the floating gate through the gate insulating film 29 in the area where the first and second control gates CG ₁₁ and CG ₂₁ intersect. 25. As a result, the threshold value of the memory element _M1 moves in the positive direction and becomes the write state "0".

Next, when erasing the contents of memory element _M1 ,
+20V is applied to the sources S ₁ and S ₂ , and the drains D ₁ and
D ₂ is open (or +20V), the first control gate CG ₁₁ and the second control gate CG ₂₁ are set to 0V, and the first control gate CG ₁₂ and the second control gate CG ₂₂ are set to +20V.
shall be. As a result, only the floating gate 25 of the memory element _M1 has a low potential, and the electrons accumulated in the floating gate 25 are emitted by the tunnel current to the n-type layer 28, that is, the source, and become "1".
Return to state.

When reading the contents of the memory element _M1 , a read potential (for example, +5V) is applied to the drain _D1 , a selection potential (for example, +5V) is applied to the first control gate _CG11 , and everything else is set to 0V. As a result, when the memory element _M1 is "1", a channel current flows, and when it is "0", no channel current flows, so that it is possible to distinguish between "1" and "0".

By the way, in the above erasing operation, the threshold value does not change to the initial state, but changes even further in a negative direction than the initial state. This situation can be seen in Chapter 5.
As shown in the figure. That is, the threshold value V _t0 (>
0), the threshold value is V _t1 larger than V _t0 in the write state "0", and both are E type, but in the erase state, the threshold value becomes D type with V _t0 '(<0).
In such an erased state, if the memory element has a normal gate structure, a channel current will flow even to the memory element in the non-selected state where the gate voltage is 0V during a read operation, making selective reading impossible. However, in the memory element of this embodiment, as shown in FIG. 2b, the floating gate 25 has an offset structure, and the first control gate 27 functions as a gate electrode for the remaining channel region. Therefore, even if the area under the floating gate 25 becomes D type due to the erase operation, the threshold value of the entire memory element is the initial state threshold determined by the area under the first control gate 27.
V does not go below _t0 . In other words, the memory element always operates in the E type region, and no channel current flows to unselected memory elements with the first control gate 27 set to 0V. That is, the fifth
As shown in the figure, by applying the selection potential V _R to the first control gate of the selected row and setting the other first control gates to 0V, selective reading is reliably performed.

In addition, in this embodiment, the source 2 of each memory element
2. The drains 23 are commonly connected in directions perpendicular to each other by multilayer Al wiring. source 22
In principle, they are commonly connected in the row direction only by the diffusion layer in the substrate, but as mentioned above, the n-type layer 28 formed in advance under the second control gate 31 is not connected in excess to cause a tunnel effect. A high concentration cannot be achieved, and therefore, with this alone, the source is connected through a relatively high diffusion resistance, and high-speed operation cannot be achieved. In this regard, in this embodiment, the sources are commonly connected through the first Al wiring 32, so that a high-speed read operation is possible.

Furthermore, the memory element in FIG. 2 has a coupling capacitance between the first and second control gates 27, 31 and the floating gate 25.
C _CF1 and C _CF2 are approximately equal, and the coupling capacitance C _S between the n-type layer 28 (ie, the source 22) and the floating gate 25 is configured to be smaller than this. This provides a high operating margin. That is, C _CF1 , C _CF2
This is because the on/off ratio decreases when the variation in is large, and the on/off ratio also decreases when C _S increases.

Another embodiment of the invention is shown in Figures 6a-c. a
is a plan view, and b and c are A-A' and B- of a, respectively.
B′ cross-sectional view. The same reference numerals are given to the parts corresponding to the embodiment in FIG. 2, and the explanation will be omitted.To explain the different parts, in this embodiment, the n-type layer formed as the third control gate in the previous embodiment is used. 28 is not provided. That is, in this embodiment, the substrate 21 itself functions as the third control gate. Furthermore, in this embodiment, since charges are exchanged between the second control gate 31 and the floating gate 25, the gate insulating film 26 between them is made thick enough to produce a tunnel effect.

As in the previous embodiment, selective write, erase, and read operations of memory elements arranged in a matrix will be explained as follows. First, in the case of writing, the source 22, drain 23, and substrate 21 are all set to a high potential (for example, +20V). and the first
The control gate 27 sets the selected row at a high potential and the rest at a low potential (for example, 0V), and the second control gate 31 sets the selected column at a low potential and the rest at a high potential. As a result, only in the selected memory cell, the floating gate 25 is at a sufficiently high potential and the second
The potential of the control gate 31 becomes low, and electrons are injected from the second control gate 31 into the floating gate 25 by a tunnel current through the gate insulating film 26, resulting in a write state of "0". Next, in the case of erasing, the source 22, drain 23 and substrate 21
are all at low potential. and the first control gate 2
7 sets the selected row to a low potential and the rest to a high potential,
The second control gate 31 connects the selected column to a high potential.
The rest is at low potential. As a result, only in the selected memory cell, the floating gate 25 has a sufficiently low potential and the second control gate 31 has a high potential, and electrons are emitted from the floating gate 25 to the second control gate 31 by a tunnel current. is,
The erase state becomes "1". The read operation is similar to the previous embodiment.

It is clear that this embodiment also provides the same effects as the previous embodiment.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, the sources of each memory element are commonly connected to the Al wiring 32 arranged in the row direction, but as shown in FIG. The first Al wiring may be integrated by disposing the second Al wiring over the entire surface of the chip with a window formed in the region 72 where the second Al wiring contacts the drain. In addition, by shifting the position of the source contact hole in the above embodiment, the drain of each memory cell is connected in common in the column direction.
A first Al wiring that commonly connects the Al wiring and the source may be arranged in parallel. Further, for the write operation, a method of injecting hot electrons from the channel region can be used as in the conventional method.
Furthermore, the source and drain of the memory element may be considered in the opposite manner to the above embodiment, or a p-channel memory element may be used. Furthermore, the arrangement of the floating gate and the first control gate with respect to the channel region may be designed so that the floating gate covers the peripheral part of the channel region and the first control gate covers the central part, contrary to the above embodiment. good. Of course, it is also possible to reverse the first and second control gates to those in the above embodiment.

[Brief explanation of the drawing]

FIGS. 1a to 1c are diagrams showing the main structure of a conventional nonvolatile semiconductor memory device, FIGS. 2a to d are diagrams showing the main structure of a memory device according to an embodiment of the present invention, and FIG. Equivalent circuit diagram of the memory element, No. 4
FIG. 5 is a diagram showing the operating characteristics of the memory device, and FIGS. 6 a to 6 c are diagrams showing the main structure of the memory device of another embodiment. FIG. 7 is a diagram showing a deformed pattern of Al wiring. 21...p-type Si substrate, 22...n ⁺ type source, 2
3...n ⁺ type drain, 24, 26, 29, 30
...Gate insulating film, 25...Floating gate, 27...
...first control gate, 28...n-type layer (third control gate), 31...second control gate, 32...
...first Al wiring, 34...second Al wiring.

Claims (1)

[Claims] 1. In a nonvolatile semiconductor memory device in which memory elements each having a floating gate and a control gate capacitively coupled thereto are integrated in a matrix on a semiconductor substrate, the source of each memory element is arranged in the row direction. are commonly connected to each other by a diffusion layer wiring, and a first layer metal wiring that contacts this diffusion layer wiring at a predetermined location is arranged in an overlapping manner, and the drain of each memory element is commonly connected to a second layer metal wiring in the column direction. A nonvolatile semiconductor memory device characterized by: 2. The first layer metal wiring is disposed on the entire surface of the chip with a window opened in the region where the second layer metal wiring contacts the drain.
The non-volatile semiconductor memory device described in 2.