JPH037169B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a signal synchronization circuit for a wired or wireless confidential communication system.

In wired or wireless communication, there is a problem in that the contents of the communication can be intercepted by anyone if an appropriate receiving device is used. Therefore, special signal processing is applied to the transmitted signal so that even if it is intercepted, the content cannot be understood, so that only a specific receiver who has the means to reproduce the processed signal can receive it. Circuit schemes are used as needed. The present invention provides a signal synchronization circuit for this confidential communication system.

(b) Prior art Conventionally, as shown in Fig. 1, a base unit (B; Base) 1
A cordless telephone 1'' consists of a handset (P; Portable) 1' and a cordless telephone 1'' in which the base unit 1 is connected to
via the central office exchange (Ex; Exchanger) 4
At the same time, wireless communication is performed between the base unit and the portable handset, that is, the handset 1'.
The telephone line l is connected by the transmitter and handset of handset 1'.
This allows you to talk to a desired destination connected to the phone, and by carrying the handset, you can make cordless calls from any desired location.

In this cordless telephone, if the frequency of the carrier wave used for communication between the base unit and the slave unit is the same as that of a cordless telephone owned by a third party, problems of attempted theft and missed calls (lack of confidentiality) occur. The usable frequency band is restricted due to the connection with other wireless devices, and it is practically difficult to change the carrier frequency for each cordless telephone. In reality, only five types of carrier waves are used, and the above-mentioned problem is likely to occur.

Now, as shown in Fig. 2, when Party A sends a message to Party B's cordless telephone 2 by using the handset of handset 1', the cordless telephone 3 of a third party (C) and the carrier If the frequencies are the same, operate the base unit of C. In this case,
This problem does not exist if C's base unit 3 is outside the usable range (communicable distance; usually within 100 to 200 m) of A's cordless phone.

Now, when C's base unit 3 works, C's phone line
A situation has arisen where Party A and Party B can talk through
The problem of billing for telephone usage arises. Cordless telephones transmit a pilot signal superimposed on the outgoing voice signal, and the base unit detects this pilot signal and turns on a relay to establish a connection with the telephone line (this relay is used for general standard telephones). (equivalent to a telephone switch that connects to a telephone line when you pick up the handset). Therefore, as a measure to prevent plagiarism, which poses the problem of billing, it is sufficient to key code the frequency and waveform of this pilot signal.

However, even in this case, there remains a problem regarding guaranteeing so-called confidentiality against leakage of telephone calls.
Even if C's base unit 3 does not operate due to A's handset 1', since the audio signal is being sent from A's base unit 1 while A and B are talking, this is C's base unit 3'. It is possible to receive by. That is, in addition to the received signal from Party B, the voice signal from Party A includes information on the outgoing signal from Party A, called sidetone, and Party C can eavesdrop on the entire contents of the call.

An effective way to prevent such eavesdropping and maintain confidentiality is to scramble the audio in the transmitter and restore it in the receiver. According to this method, a third party (C) who is not equipped with a restoration circuit and a third party (C) who is equipped with a restoration circuit but whose key code is different
The contents of the call cannot be understood.

Conventionally, balance modulator type circuit elements are generally commercially available as confidential communication circuits for such purposes. In this method, the frequency of the audio signal is inverted before being transmitted, and the frequency is restored upon reception. Although this method is effective for third parties that do not have a restoration circuit, it has the disadvantage that it is not effective against third parties that have the same type of restoration circuit because key codes cannot be multiplied.

Therefore, the present applicant previously proposed Japanese Patent Application No. 57-164763 entitled ``Secret Communication Method and Apparatus'' dated September 20, 1981. That is, we have proposed a method for compressing and expanding the time axis of an audio signal and transmitting it as a method that has a relatively simple circuit scale and high confidential speech performance. Furthermore, on October 20, 1981, he proposed Patent Application No. 184916 ``Clock circuit for confidential communication system''.
The confidential communication method of the applicant's earlier application can use a large number of key codes.

(c) Purpose The present invention provides a signal synchronization circuit for a confidential communication system that is a more specific improvement on the technology of the prior application.

(d) Configuration First, the basic circuit of the circuit of the present invention will be explained with reference to FIG. FIG. 3 shows an example of a scrambling circuit and a restoring circuit. That is, a case is shown in which a scrambled audio signal is transmitted from the base unit (Bage) side 1 in FIG.

The basic configuration of the base unit 1 in Figure 3a is BBD
A delay circuit 5 consisting of a Bucket Brigade Device, a selection circuit 6 for clock pulses 1 and 2, a counter 7 that controls the selection circuit, a sync.signal generator 8, and a synthesis circuit. (Adder) 9, Modulation Circuit
10, and a transmitter 11. Further, the slave device 1' in FIG. 3b includes a receiving section 12 consisting of a high frequency amplification stage, a local oscillation stage, a mixing stage, and an intermediate frequency amplification stage, a demodulation circuit 13, and a filter circuit 14. , a selection circuit 15 for clock pulses 1 and 2, and a BBD delay circuit 16.

The basic operation of the circuit shown in FIG. 3 will be explained below. In this method, two types 1 and 2 are used as the frequency of the clock pulse (CP) for controlling the BBD5, and the clock pulse selection circuit 6 selects 1 every time the control counter clocks N=(number of delay stages of the BBD)/2. Switch 2.

Next, why is the maximum count value N of control counter 7?
We will explain how to reduce the number of delay stages to 1/2 of BBD5.

In this secret speech circuit, the audio signal input to the variable delay circuit is delayed by N stages (N clocks are input), and then
When output, the frequency of the clock is switched every N clocks. In this case, the audio signal input to the variable delay circuit with a frequency of 1 will have a frequency of 1 after being delayed by N stages.
2, so the frequency of the audio signal is 2/1
It is output after changing twice (see Fig. 13).

Here, when a BBD is used as a variable delay circuit, and the number of delay stages of the BBD is k, the audio signal input to the BBD is output after k/2 stages (k/2 clocks are input). The reason is as follows. That is, as shown in FIG. 14 which qualitatively shows the operation, BBD consists of two delay elements A and B as a pair.
constitutes one delay element, and when clock q is input, _elements B _{1 ,} . . .
₂ ,... becomes lower, and the information _C1 , _C2 ... stored in elements _A1 , _A2 ... is transferred to elements _B1 , _B2 .... In FIG. 14a, elements B ₁ , B ₂ , and B ₃ have no charge. In addition, in FIG. 1B, the charge is transferred from element A to B, so elements A ₁ , A ₂ , and A ₃ do not have charge. Next, when clock Q (inversion of clock q) is input, the levels of elements B ₁ , B ₂ . . . become higher, as shown in FIG _.
C ₂ ... moves (shifts) to elements A ₂ , A ₃ .... In C of the same figure, charges are transferred from elements B ₁ , B ₂ . . . to A ₂ , A _{3 .} . . , and B ₁ , B _{2 .} . . have no charge. This situation resembles a bucket brigade. Every time one clock is input here, the information C is shifted from (Aj) to (Aj+1).
Also, since clock Q is the inverse of q, it is not included in the number of input clocks. In BBD, the number of delay stages is displayed including both elements A and B, so the net number of delays is 1/1 of the number of delay stages. It becomes 2.

The information shifting operation inside the BBD is the 14th
As shown in the figure, the input/output operations of the BBD are as follows. In other words, the input signal written to the BBD by a clock with a frequency of 1 is shifted for each clock input (shifted by 2 stages in a bucket brigade style as described above), and N = (number of delay stages of BBD/
2) When the +1st clock is input, it is output from the BBD, but the frequency of the clock changes every N clocks, so the clock with frequency 2 is output. Also, an audio signal input with a clock with a frequency of 2 will be output with a frequency of 1.

The audio signal that is now input to the BBD circuit 5 of the base unit
In is sampled at frequency 1 and memorized to BBD5. After the clock pulse (frequency 1) is counted N by the control counter 7, this signal becomes
Output from BBD. At this time, the clock pulse
The frequency of CP1 has been switched to 2, and at this timing the signal memorized in BBD5 is
Output from BBD. Therefore, the audio signal has a frequency
Since it is memorized in step 1 and outputted in step 2, the frequency of the audio signal is subjected to time axis conversion, and the frequency of the audio signal output from BBD is m compared to the original audio signal.
= converted to 2/1 times. Conversely, if the signal is memorized at 2 and output at 1, the frequency is converted to 1/m times. Therefore, conversion operations of m times the frequency and 1/m times the frequency are performed periodically, so that, for example, the output signal of the BBD 5 of the base unit has the waveform shown in FIG. 4 in response to a sine wave input signal. If the synchronization signal for the switching timing of the clock pulse frequency on the base unit 1 is sent to the slave unit 1' to synchronize the switching operation of the slave unit with the base unit, the slave unit will also do the same by m times and 1/m. Repeat double frequency conversion. In this case, as shown in Figure 5, the audio signal is delayed by N clocks by the BBD5, so the signal converted by m times by the BBD5 of the base unit is converted by exactly 1/m times by the slave unit 1'. is converted to the original frequency. Similarly, what is converted by 1/m in the parent device is converted into m times in the slave device.
In Fig. 5, a is the input original signal In, b is the scrambled signal scrambled by BBD5 of the master unit, C is the restored signal restored by BBD16 of the slave unit, and d is the signal of BBD5 and 16, respectively. Indicates the clock frequency used for processing.

At this time, if the slave unit clock frequencies 1' and 2' differ from the base unit's clock frequencies 1 and 2, the original audio signal will not be restored. Therefore, the key code can be multiplied by a combination of 1 and 2. For example, set the clock frequency to 1 or 2 for case A, and set the clock frequency for case C to 1 or 2.
Even in the case of m=2/1=2'/1' for 1' and 2', experiments have shown that if 1 differs from 1 by 5% or more, a practically sufficient scrambling effect can be obtained. Therefore,
In this case, the frequency used for 1 is approximately per octave.
Since 16 key codes can be used, and the usable clock frequency range of BBD is quite wide from 10KHz to 200KHz, a large number of key codes can be used. Moreover, the number of key codes can be further increased by further changing the value of m. As described above, by using this secret message circuit, not only a third party C who is not equipped with a BBD restoration circuit, but also a large number of key codes can be obtained, so that secret information can be sufficiently retained.

Now, in the case of this confidential circuit system, it is said that it is very important to exactly synchronize the switching of the clock frequency in the slave unit with that of the base unit. The synchronization signal is normally transmitted in a superimposed manner with the audio signal, and it is necessary to separate the audio signal and the synchronization signal in the handset.

The simplest method is to simply superimpose the output of the control counter on the base unit onto the audio signal, detect this signal on the slave unit, and switch the clock frequency, but this method has the following drawbacks: . That is, (a) Since the falling (or rising) characteristic of the control counter 7 of the base unit is steep, the spectrum of this synchronization signal has a wide spectrum at the base, and is therefore superimposed on the spectrum of the audio signal. This component cannot be separated from the audio signal by filter processing in the handset, and deteriorates the reproduced sound quality.

(b) In order to improve the separation from the audio signal, the control counter output can be further processed by a filter so that the spectrum does not overlap with the audio spectrum band, but in this case, a sharp falling (or rising) ) characteristics are not obtained, the synchronization timing is delayed, and the audio signal connection does not go well when restoring the signal or switching.

(c) When noise gets mixed in, it is easily affected by it and synchronization errors occur.

The present invention takes these drawbacks into consideration and provides an improved synchronization method. The present invention will be explained in detail below.

The synchronization method according to the present invention is shown in FIG. Figure a shows the parent unit, and Figure b shows the slave unit. Further, the signal waveform is shown in FIG. A signal obtained by gate-controlling the output of the single frequency oscillator 17 (see FIG. 7b) is further passed through a filter (HPF or BPF) 18 by the output of the clock pulse switching control counter 7 of the BBD 5 (see FIG. 7a). The processed signal is superimposed on the audio signal (after scrambling processing) and transmitted as a synchronizing signal in the synthesis circuit 9 as shown in FIG. The frequency of the oscillator 17 is 5 to 10 KHz, considering the band required for audio reproduction (usually 300 to 3.4 KHz).
Approximately Hz is appropriate. As shown in FIG. 7b, the spectrum of the output signal of the gate-controlled oscillator 17 has its center frequency at the frequency of the oscillator, which is sufficiently high compared to the audio signal, but the tail of the spectrum is superimposed on the audio spectrum. Filter 18 processing is applied to prevent this from occurring. In this case, due to the filter, the envelope of the rising portion is not steep, but has a slightly rounded shape, as shown in FIG. 7c. This figure 7c
A signal as shown in FIG. 1 is superimposed on the audio signal and transmitted as a synchronization signal.

On the other hand, in the handset, after separating the synchronization signal superimposed on the audio signal by the filter 19, when an input signal as shown in FIG. 7d is applied to the input of the comparator 20, a pulse train as shown in FIG. 7e is generated. can get. Further, when this pulse train signal is supplied to the synchronous trigger generation circuit 21, a single pulse synchronized with the rise of the first pulse output from the comparator 20 is obtained. Furthermore, after passing through the AND gate circuit 22, this signal is supplied as a preset input trigger to the control counter 23. At this time, an inverted signal of the output of the control counter 23 is applied to the AND gate circuit 22.

Now, the synchronization signal is processed by filter 18 on the base unit and filter 1 for separation from the audio signal on the slave unit.
9 processing is performed, the first
As shown in Fig. 7e, the rise time of the th pulse or synchronization trigger pulse is slightly delayed (△t) from the fall time of the control transistor 7 on the base unit side (see Fig. 7a). Since the delay can be compensated for by adjusting the preset number P of the control counter 23 on the slave unit, the output side of the control counter 23 on the slave unit [i.e., the clock frequency
CP ₂ switching timing] can be synchronized with the base unit. Next, this operation will be explained in more detail. That is, when the synchronization signal passes through a transmission path with a limited band, it forms an envelope as shown in FIG. 7c, which delays the time at which the synchronization trigger can be detected.
Therefore, as shown in Fig. 15, the value of the number (h) of clocks within the time delay (△t) (h = △t
If the counter 23 is preset, the counter 23 will be h.
Since the synchronization timing is stepped from the point d, it is possible to compensate for a shift in synchronization timing due to a time delay (Δt), as shown in d of the same figure. Incidentally, Figure c shows the situation when the counter 23 is not preset, and is out of synchronization. In addition, the output of the comparator 20 (Fig. 7e)
(Reference) To obtain a preset trigger from the output pulse train, as shown in FIG.

In the above description, an example is described in which the synchronous trigger generation circuit 21 generates a preset pulse signal as shown in FIG. 7f based on the timing of the first rising edge of the pulse train of the output signal of the comparator 20 (FIG. 7e). However, it goes without saying that the same objective can be achieved by using a desired pulse in the pulse train of FIG. 7e.

In addition, in the circuit of the present invention, since a fairly high level is used as the reference voltage _E1 for comparison in the comparator 20, the synchronization signal (see FIG. 7d)
The influence of the noise N superimposed on the image can be eliminated. Furthermore, the time difference (Δt) in the rise timing of the first pulse output from the comparator 20 is also less affected by noise. As described above, the synchronization method of the present invention has a structure that is quite resistant to noise N, and furthermore, even if noise _N1 exceeding the reference voltage of the comparator occurs, it has a structure that includes measures to prevent the influence. It's summery.

Next, its operation will be explained. Figure 9 is the 6th
More specific embodiments are shown in the figures, with FIG. 9a showing the main device side and FIG. 9b showing the child device side.

In order to obtain the preset synchronization trigger pulse [Fig. 7f] from the pulse train that is the comparator output, when the output of the comparator 20 is supplied to the integrating circuit 24 as shown in Fig. 9b, the pulse train is first concatenated into a single A pulse is obtained, and when this signal is further passed through a short pulse generation circuit 28 consisting of an inverting amplifier 25, an integrating circuit 26, and an AND circuit 26, a preset synchronization trigger signal [7th] of the control counter 23 is generated.
Figure f] is obtained. Then, by adjusting the number of presets as described above, the control counter 2 of the slave unit
The output of No. 3 [Fig. 7 g] can be synchronized at the same timing as the main unit [Fig. 7 a].

The synchronization method shown in FIG. 9 is based on the operation of feeding back the output of the control counter 23 on the slave side and selecting a preset signal using the synchronization trigger and the AND logic 22. To further explain the operation in detail, when noise occurs and appears at the output of the comparator 20 [FIG. 8a], this signal is obtained as a trigger signal such as _N1 in FIG. 8C.
In this case, during the _T1 period, the superimposed noise overlaps the pulse train caused by the synchronization signal, and this pulse train
Since the single pulse generation circuit 24 shown in the figure produces a continuous waveform as shown in Fig. 8b, the waveform shown in Fig. 8c
There is no trigger caused by noise during the _T1 period. First, when the handset control counter 23 is preset by the synchronization trigger pulse S, the control counter output becomes O in the _T1 interval. Furthermore, Figures 8 and 9
As shown in the figure, the AND logic 22 with the synchronization trigger generation output is performed on the inverted signal of the control counter output _Q1 , so in this case, the synchronization trigger generation output signal (see Figure 10a) is It passes through and is supplied as a preset signal. In addition, FIG. 10b shows the output of the counter 23, S is a synchronization trigger, and P
indicates preset operation.

Now, the trigger N ₁ due to noise is as mentioned above.
Exists only in the T ₂ period. During this _T2 period, the handset control counter 23 has already reached N counts after the preset, and the output has been switched to "1".
Therefore, in this case, the AND for preset signal selection is
The noise trigger _N1 is cut off by the logic circuit and does not become a preset signal, thus preventing the influence of noise.

Next, when the control counter 23 reaches the 2Nth count, the control counter output has switched from "1" to "0", so during the _T1 period, the synchronization trigger signal is sent to the AND circuit 22 as a preset signal.
pass through.

In this way, the circuit of the present invention can lock synchronization by ANDing the synchronization trigger signal and the control counter on the slave side, and has the effect of preventing the effects of noise. .

Now, when the handset phone circuit is turned on,
It is unknown what state the falling edge (ie, clock frequency switching) timing of the counter output of the slave device is. Therefore, if this initial state is shown in Fig. 11, and if the above-mentioned AND logic is applied, the slave unit control counter output will be "1" at the timing of the synchronous trigger generation, as shown in the figure. , a situation exists in which no preset signal is supplied and therefore the control counter remains completely unsynchronized. Furthermore, the 11th
Figure a shows the output of the synchronous trigger generation circuit 29, and figure b shows the output of the counter 23. As a countermeasure for this, you can manually lock the changeover switch 30,
Alternatively, the lock may be released. If automatic operation is desired, a delay circuit using a capacitor or the like may be added so that the lock is released immediately after the handset telephone circuit is turned on, and the AND circuit is operated after a short delay.

In this case, until the lock is applied, the control counter is preset by the output of the synchronous trigger generation circuit output 29 (including the synchronous trigger and the noise trigger), and operates accordingly. Therefore, it is necessary to consider the operation after locking depending on whether the preset was performed using a synchronization trigger or a noise trigger immediately before locking.

When locked after being preset by a synchronization trigger, the operation is the same as that described above. Next, the 12th case is preset with noise trigger _N1 .
As shown in the figure. Note that a in the figure shows the synchronous trigger generation circuit 29.
, and b shows the output of the counter 23. In the figure, consider the case where the noise trigger _N1 exists in the _T2 period and is locked before entering the _T3 period. and
No noise trigger occurs during the _T1 period.

When preset with T ₂ periods of noise, the first
As shown in Figure 2, at the synchronization trigger time of period _T3 ,
The control counter output is in the "O" state. Therefore, the preset will be updated by this synchronization trigger, and the synchronization will be performed correctly from now on. As described above, it can be seen that the same synchronous operation can be performed no matter what state the lock is applied to.

(e) Effects As described above, by using the synchronization lock method according to the present invention, it is possible to prevent synchronization malfunctions even when noise is mixed. In addition, since the synchronization signal uses filter processing, the influence on the audio signal can be reduced, and the time delay caused by filter processing is compensated for by counter preset processing, which reduces the playback quality due to synchronization errors. Eliminate the problem of deterioration. Furthermore, the present invention is very useful in practice, since it is possible to conduct a telephone call with confidentiality ensured by using a cordless telephone that employs a confidential communication circuit using a delay circuit using the synchronization method according to the present invention.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional cordless telephone, Fig. 2 is a diagram showing the route of missed calls in the same circuit, and Fig. 3 is a block diagram for explaining the basic principle of the synchronous circuit of the confidential communication system of the present invention. , 4th
The figure shows a signal scrambled by the circuit of Fig. 3, Fig. 5 is a drawing for explaining the basic operation of the circuit of Fig. 3, and Fig. 6 shows a signal synchronization circuit of the secure communication system of the present invention. The block circuit diagram shown in FIG. 7 is a diagram showing the signal waveforms of FIG. 6, and FIG.
The figure is an explanatory diagram for explaining the operation of Fig. 9.
The figure shows a specific embodiment of the present invention, and FIGS. 10, 11, and 12 are explanatory diagrams for explaining FIG. 9. FIG. 13 is a drawing showing the writing and reading pulses of the BBD, FIG. 14 is a drawing showing how information is shifted inside the BBD, and FIG. 15 is a drawing for explaining the presetting operation by the counter. 1, 1', 1''...Main unit, 2, 2', 2''...Slave unit, 5, 16...Delay circuit, 6, 15...Clock pulse selection circuit, 7, 22...Control circuit, 8 …
...Synchronizing signal generation circuit, 9...Synthesizing circuit, 10...
Modulation circuit, 11... Transmission circuit, 12... Receiving circuit, 13... Demodulation circuit, 14, 18, 19... Filter circuit, 17... Synchronization signal generation circuit, 20...
... Comparator, 21 ... Synchronous trigger generation circuit,
22...AND circuit, 23...control circuit (counter circuit), 24...integrator circuit, 28...short pulse generation circuit. 29... Synchronous trigger generation circuit, 30...
...Switch.

Claims (1)

[Claims] 1. The transmitter side is equipped with a variable delay circuit for a signal whose delay time can be controlled by a clock, and the variable delay circuit is connected to the first
Then, by controlling the second clock, the time axis of the transmission signal is alternately compressed and expanded in time and transmitted, and the delay circuit on the receiver side also has a variable delay circuit for the signal that can be controlled by the clock. A confidential communication system comprising: a clock control of the variable delay circuit at the same time as the transmitting side, thereby alternately expanding and compressing the time axis of the received signal and restoring the original signal; On the machine side, first and second clock signal generation circuits for clock control of the variable delay circuit, a control circuit for counting clocks corresponding to the maximum number of delay stages of the variable delay circuit, and an output of the control circuit are provided. Said first and second
A clock selection circuit that selects a clock and a synchronization signal generation circuit that generates a synchronization signal of a predetermined frequency are provided, and the output of the synchronization signal frequency oscillation circuit is gate-controlled by the output of the control circuit and superimposed on the transmission signal. On the other hand, on the receiver side, a filter circuit separates the electrical transmission signal and the synchronization signal, generates a pulse train in response to the separated synchronization signal, and synchronizes with the first pulse of the pulse train. generates a trigger signal, and in response to the time difference between the rising or falling edge of the output gate pulse of the transmitter side control circuit and the trigger signal, the control circuit of the receiver side clock selection circuit generates the trigger signal. The switching times of the first and second clock pulses on the transmitter and receiver sides are synchronized by presetting the number of clocks corresponding to 1. A signal synchronization circuit for a confidential communication system, characterized in that a synchronization signal for time synchronization is selected by switching between a second clock pulse and a second clock pulse.