JPH0378658B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an error notification method in a data processing device, and in particular to a system for notifying an error when an error occurs in a subordinate device such as a peripheral control device coupled to a CPU.
Concerning error notification method to CPU.

[Conventional technology]

Conventionally, in devices that are peripheral control devices or auxiliary processing devices such as channel devices that operate under the CPU and have an internal interrupt mask, when an error occurs, a method is used to send a device error interrupt signal to the CPU through the interrupt mask. was taken.

Figure 2 is a configuration diagram for explaining the conventional interrupt method. 1 is the CPU, 2 is the SVP of the service processor, 3 is the channel device CHU, 4 is the interrupt register IRTR, and 5 is the mask register.
MSKR, 6 is an interrupt mask circuit, and 7 is an OR circuit. Also, A, B, and C are interrupt factors, a,
b and c indicate corresponding mask data.

In CHU3, mask register MSKR5 is set with mask data a, b, and c for inhibiting interrupts with a lower priority than the priority of the program currently being executed by the CPU, and on the other hand, interrupt causes A and B are set. , C occurs, it is set in the corresponding bit position of interrupt register IRTR4. The interrupt mask circuit 6 detects that the interrupt cause set in the interrupt register IRTR4 is
When it is permitted by the mask data a, b, and c, a signal is applied to the OR circuit 7, and the OR circuit 7 raises an interrupt request signal to the CPU 1.
When the CPU 1 receives this interrupt request, it checks the cause of the interrupt and performs the corresponding interrupt processing.

An error occurring in the CHU3 is also associated with one of the interrupt factors, for example A, and is set in the interrupt register IRTR4 and masked by the interrupt mask circuit 6 like other interrupt factors.

By the way, when an interrupt request from CHU3 is based on a device error, if you want SVP2 to perform error recovery processing for CHU3 as the interrupt processing, if CHU3 remains in an inoperable state due to an error occurrence, SVP2 cannot perform error recovery processing for CHU3. Therefore
Before issuing a device error interrupt to CPU1,
It was necessary to reset the error cause in CHU3.

[Problem that the invention seeks to solve]

Therefore, SVP2 constantly monitors CHU3,
When detecting that an error has occurred in CHU3, one possible method is to reset CHU3 to erase the error condition and then issue an error interrupt, but when CHU3 is reset, the mask data in mask register MSKR5 is also cleared. Even if the error interrupt factor (A) is set in the interrupt register IRTR4, it will be masked by the interrupt mask circuit 6, so an interrupt request signal cannot be sent to the CPU1. Therefore, it is necessary to restore the mask data, but if an error occurs during the restoration process, there is a problem that the CPU cannot be notified of the device error, and it has not been possible to solve it with a simple method.

[Means for solving problems]

In the present invention, when an error occurs in a subordinate device of the CPU, it is reset by SVP, a forced interrupt is issued to the CPU without masking in the subordinate device, preprocessing is performed to have the CPU restore the mask, and then the subordinate device is reset. This method causes the device to issue a masked error interrupt, and the specific solution is to use the above method in a data processing device that has a CPU, an SVP, and a device under the CPU that can issue an interrupt request to the CPU. The devices under the CPU include an interrupt register, a mask register, an interrupt mask circuit that masks the interrupt cause set in the interrupt register with mask data set in the mask register, a forced interrupt register, the interrupt mask circuit, and a forced interrupt register. Interrupt register output as interrupt request signal
The above SVP is equipped with a means to send data to the CPU.
The operating status of devices under the CPU is constantly monitored, and when an error is detected, the device under the CPU is reset and the above forced interrupt register is set.
Set it to ON to send a forced interrupt request signal to the CPU. In response, the CPU requests the device under the CPU to restore the mask data in the mask register, and the device under the CPU responds to the restoration request. restores the mask data in the mask register, sets the error interrupt cause in the interrupt register, and sends an interrupt request signal to the CPU via the interrupt mask circuit. It is characterized by executing interrupt processing.

〔Example〕

The details of the present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram of one embodiment of the present invention, which is an improved version of the conventional system shown in FIG.
In Figure 1, 1 is CPU, 2 is SVP, 3 is
CHU, 4 is the interrupt register IRTR, 5 is the mask register MSKR, 6 is the interrupt mask circuit, 7 is the OR circuit, 8 is the forced interrupt register
IRTX, 9 is an OR circuit. Further, A, B, and C in IRTR4 are interrupt factors, especially A indicates an error interrupt factor, and a, b, and c in MSKR indicate mask data corresponding to interrupt factors A, B, and C, respectively. Note that the steps in the figure correspond to the operation procedures described below.

The configuration of this embodiment is largely different from the configuration of the conventional example shown in FIG. 2, in that a forced interrupt register IRTX8 is provided separately from the interrupt register IRTR4, and is set to ON by SVP2 when an error occurs. OR without being masked
The point is that a forced interrupt request is made to the CPU 1 via the circuit 9.

,',: SVP2 constantly monitors CHU3, and when it detects that an error has occurred in CHU3, it resets CHU3 and removes the cause of the error.
5. IRTX8 is also cleared.

:SVP2 is then the forced interrupt register.
Set IRTX8 to ON.

,': A forced interrupt signal is raised to CPU1, and CPU1 thereby sends the mask data of CHU3 stored in the CPU to CHU3 and requests restoration processing.

,′,″: CHU3 stores the mask data in the mask register MSKR in response to the restoration processing request.
5, and further sets the error interrupt factor A in the interrupt register IRTR4, and if it ends normally, it will notify the CPU 1 (if it ends abnormally, go to).

:When CPU1 receives the notification of normal termination, it cancels the forced interrupt. This erases the existence of forced interrupts.

,': If the mask data a corresponding to the error interrupt factor is ON, an error interrupt request signal is raised to the CPU 1 immediately after the forced interrupt is canceled.

:CPU1 performs device error interrupt processing,
Notify the software of device errors.

: When an error occurrence is detected in the mask restoration process, CPU 1 identifies mask data a of the error interrupt cause at that time, and if it is ON, sends a forced interrupt request to CHU.
It is regarded as an error interrupt request from 3, performs interrupt processing, and notifies the software of the device error.

〔Effect of the invention〕

As described above, according to the present invention, even if an error occurs in a subordinate device capable of issuing an interrupt request to the CPU, the device error can be reliably notified to the CPU.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. In the figure, 1 is CPU, 2 is SVP, 3 is CHU, 4 is interrupt register IRTR, 5 is mask register MSKR, 6 is interrupt mask circuit, 7 and 9 are OR circuit, 8 is forced interrupt register IRTX
shows.

Claims (1)

[Claims] 1 In a data processing device that has a CPU, an SVP, and a device under the CPU that can issue an interrupt request to the CPU, the device under the CPU has an interrupt register, a mask register, and a device that is set in the interrupt register. An interrupt mask circuit that masks interrupt causes with mask data set in a mask register, a forced interrupt register,
Equipped with means for sending the output of the interrupt mask circuit and forced interrupt register to the CPU as an interrupt request signal, the SVP constantly monitors the operating status of devices under the CPU, and when an error is detected, sends the output of the forced interrupt register to the CPU. Reset the device and set the forced interrupt register above to ON.
Sends a forced interrupt request signal to the CPU,
In response, requests the device under the CPU to restore the mask data of the mask register,
In response to the restoration request, the device under the CPU restores the mask data in the mask register, sets the error interrupt cause in the interrupt register, and sends an interrupt request signal to the CPU via the interrupt mask circuit. An error notification method characterized by executing interrupt processing for an error in a device under a CPU in response to an error.