JPH038103B2 - - Google Patents
Info
- Publication number
- JPH038103B2 JPH038103B2 JP59130033A JP13003384A JPH038103B2 JP H038103 B2 JPH038103 B2 JP H038103B2 JP 59130033 A JP59130033 A JP 59130033A JP 13003384 A JP13003384 A JP 13003384A JP H038103 B2 JPH038103 B2 JP H038103B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- single crystal
- semiconductor device
- crystal
- silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Recrystallisation Techniques (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、単結晶スピネル膜等の単結晶絶縁
膜上にニツケルシリサイド等の単結晶導電膜を形
成して半導体装置を作成する半導体装置の製造方
法に関する。[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a semiconductor device in which a single crystal conductive film such as nickel silicide is formed on a single crystal insulating film such as a single crystal spinel film. Regarding the manufacturing method.
一般に、回路の高密度化、高集積化を図るため
に、積層構造の半導体立体回路素子の開発が進め
られており、この場合、能動層が形成された半導
体層および該半導体層上に絶縁膜、配線用導電膜
を順次積層していくが、特性の優れた半導体立体
回路素子を得るために、各材料を単結晶状態のま
ま積層することが試みられている。
Generally, in order to increase the density and integration of circuits, the development of semiconductor three-dimensional circuit elements with a stacked structure is progressing. Conductive films for wiring are sequentially laminated, but in order to obtain a semiconductor three-dimensional circuit element with excellent characteristics, attempts have been made to laminate each material in a single crystal state.
そして、配線用導電膜として、たとえばエピタ
キシヤルシリサイド膜を形成することが考えられ
ており、従来エピタキシヤルシリサイド膜である
ニツケルシリサイド膜を形成する方法として第１
図ないし第３図に示すようなものがある。 It has been considered to form, for example, an epitaxial silicide film as a conductive film for wiring, and the first method for forming a nickel silicide film, which is an epitaxial silicide film, has been
There are some as shown in Figures 3 to 3.
すなわち、第１図の方法は、たとえばシリコン
からなる基板１上に、分子線エピタキシヤル成長
法（以下MBEという）により、ニツケル〔Ni〕
とシリコン（ケイ素）〔Si〕とが１：２の組成比
になるようにして単結晶のNiシリサイド膜２を
エピタキシヤル成長させるものである。 That is, in the method shown in FIG. 1, nickel (Ni) is grown on a substrate 1 made of silicon, for example, by molecular beam epitaxial growth (hereinafter referred to as MBE).
A single-crystal Ni silicide film 2 is epitaxially grown such that the composition ratio of Ni silicide and silicon (Si) is 1:2.
しかし、MBEの場合、結晶成長速度が遅いた
め、Niシリサイド膜２の形成のスループツトが
低く、実用性にやや欠けるという欠点がある。 However, in the case of MBE, since the crystal growth rate is slow, the throughput for forming the Ni silicide film 2 is low, making it somewhat impractical.
つぎに、第２図の方法は、シリコン基板１上に
Niを蒸着したのち、前記Niの蒸着膜に電気炉、
ランプ加熱等によるアニールを施こし、Niの拡
散により基板１上に単結晶のNiシリサイド膜３
を固相エピタキシヤル成長させるものである。 Next, in the method shown in FIG.
After depositing Ni, an electric furnace is applied to the Ni deposited film.
Annealing is performed using lamp heating, etc., and a single crystal Ni silicide film 3 is formed on the substrate 1 by diffusion of Ni.
is grown by solid-phase epitaxial growth.
ところが、この方法を絶縁膜上のシリサイド形
成に用いる場合、Ni蒸着膜の形成前または形成
後にSiを蒸着しておく必要があるばかりか、アニ
ール時に絶縁膜との界面で相互拡散が生じてしま
い、しかもエピタキシヤル成長しないという欠点
がある。 However, when this method is used to form silicide on an insulating film, it is not only necessary to evaporate Si before or after forming the Ni evaporated film, but also mutual diffusion occurs at the interface with the insulating film during annealing. Moreover, it has the disadvantage that epitaxial growth does not occur.
さらに、第３図の方法は、シリコン基板１上に
Niの蒸着によりNi蒸着膜４を形成したのち、イ
オン注入法により、イオン化したSiすなわちSi+
をイオンエネルギ約100KeVまで加速して蒸着膜
４に打ち込み、基板１上にNiシリサイド膜を形
成させるものである。 Furthermore, the method shown in FIG.
After forming the Ni vapor deposited film 4 by vapor deposition of Ni, ionized Si, that is, Si +
is accelerated to an ion energy of approximately 100 KeV and is implanted into the deposited film 4 to form a Ni silicide film on the substrate 1.
しかしこの場合、前記した第１図、第２図の場
合と異なり、形成されたNiシリサイド膜は単結
晶にならず、しかも非常に高いイオンエネルギを
持つSi+の衝突により、形成されたNiシリサイド
膜に欠陥が生じるため、前記したイオン注入法に
よるNiシリサイド膜により、半導体立体回路素
子の配線層を形成することができないという欠点
がある。 However, in this case, unlike the cases shown in FIGS. 1 and 2, the formed Ni silicide film does not become a single crystal, and moreover, due to the collision of Si + with extremely high ion energy, the Ni silicide film formed Since defects occur in the film, there is a drawback that a wiring layer of a semiconductor three-dimensional circuit element cannot be formed using a Ni silicide film formed by the above-mentioned ion implantation method.
この発明は、前記の諸点に留意してなされたも
のであり、半導体装置を作成する際のスループツ
トの向上を図ることを目的とする。
The present invention has been made with the above-mentioned points in mind, and an object of the present invention is to improve the throughput when manufacturing semiconductor devices.
この発明は、単結晶絶縁膜上に金属膜を蒸着
し、イオンエネルギ数KeVないし数10KeVの半
導体イオンをイオン化蒸着法により前記金属膜に
照射して前記絶縁膜上に単結晶導電膜を形成し、
前記絶縁膜および前記導電膜からなる半導体装置
を作成することを特徴とする半導体装置の製造方
法である。
This invention involves depositing a metal film on a single-crystal insulating film, and irradiating the metal film with semiconductor ions having an ion energy of several KeV to several tens of KeV by ionization vapor deposition to form a single-crystal conductive film on the insulating film. ,
This is a method of manufacturing a semiconductor device, characterized in that a semiconductor device is made of the insulating film and the conductive film.
したがつて、この発明の半導体装置の製造方法
によると、蒸着した金属膜にイオンエネルギ数
KeVないし数10KeVのイオン化蒸着法により半
導体イオンを照射するため、イオンのミキシング
効果により単結晶絶縁膜上の全面にわたつて単結
晶導電膜を成長させることができ、しかも結晶成
長速度がMBEの場合に比べて速いため、単結晶
絶縁膜および単結晶導電膜からなる半導体装置の
スループツトの向上を図ることができるととも
に、イオンエネルギを数KeVないし数10KeVに
したため、イオン注入法の場合のように欠陥が発
生することもなく、特性の優れた半導体装置を作
成することができ、単結晶からなる半導体立体回
路素子の作成技術として応用することが可能とな
り、非常に実用的である。
Therefore, according to the method of manufacturing a semiconductor device of the present invention, the ion energy number is set in the vapor-deposited metal film.
Semiconductor ions are irradiated by ionization vapor deposition at KeV to several tens of KeV, so a single crystal conductive film can be grown over the entire surface of a single crystal insulating film due to the ion mixing effect, and the crystal growth rate is MBE. This makes it possible to improve the throughput of semiconductor devices made of single-crystal insulating films and single-crystal conductive films.In addition, since the ion energy is set to several KeV to several tens of KeV, defects can be avoided as in the case of ion implantation. It is possible to produce a semiconductor device with excellent characteristics without the occurrence of , and it is possible to apply this method as a production technique for a semiconductor three-dimensional circuit element made of a single crystal, which is very practical.
つぎに、この発明を、その１実施例を示した第
４図とともに細に説明する。
Next, this invention will be explained in detail with reference to FIG. 4 showing one embodiment thereof.
まず、第４図ａに示すような単結晶絶縁膜であ
る単結晶スピネル膜５を形成し、熱リン酸により
スピネル膜５の表面をクリーニングしたのち、同
図ｂに示すように、室温、高真空下でスピネル膜
５上に蒸着により金属膜である厚さ約1000Åの
Ni蒸着膜６を形成する。 First, a single-crystal spinel film 5, which is a single-crystal insulating film, as shown in FIG. A metal film with a thickness of approximately 1000 Å is deposited on the spinel film 5 under vacuum.
A Ni vapor deposited film 6 is formed.
つぎに、Siをイオン化率数％にイオン化し、膜
５，６の温度を適当な温度に保ちつつ、イオン化
蒸着法により、第４図ｃに示すように、イオン化
したシリコンすなわちSi+をイオンエネルギ約
5KeVまで加速してNi蒸着膜６の全面に照射する
と、Si+のミキシング効果により、スピネル膜５
上の全面にわたつてNiシリサイド〔NiSi2〕がエ
ピタキシヤル成長し、スピネル膜５上に同図ｄに
示すような単結晶導電膜である単結晶のNiシリ
サイド膜７が形成され、スピネル膜５とNiシリ
サイド膜７からなる半導体装置８が作成される。 Next, Si is ionized to an ionization rate of several percent, and while keeping the temperature of the films 5 and 6 at an appropriate temperature, the ionized silicon, that is, Si about
When the entire surface of the Ni vapor deposited film 6 is irradiated with acceleration up to 5 KeV, the spinel film 5 is heated due to the mixing effect of Si + .
Ni silicide [NiSi 2 ] is epitaxially grown over the entire surface of the spinel film 5, and a single-crystal Ni silicide film 7, which is a single-crystal conductive film, as shown in FIG. A semiconductor device 8 consisting of the Ni silicide film 7 and the Ni silicide film 7 is produced.
なお、このときの結晶成長速度は約1000Å／
minであり、Niシリサイド膜７の形成後のNiと
Siとの組成比が１：２となるようにしている。 Note that the crystal growth rate at this time is approximately 1000 Å/
min, and the Ni after forming the Ni silicide film 7 and
The composition ratio with Si is set to 1:2.
そして、このようにして形成された半導体装置
８を能動領域が形成されたシリコン基板上に積層
して配線用導電層とし、さらに積層したNiシリ
サイド膜７上に単結晶スピネル膜等の単結晶層間
絶縁膜を介在して次層の基板を積層し、これらを
繰り返すことにより、単結晶からなる特性の優れ
た半導体立体回路素子を形成することができる。 The semiconductor device 8 thus formed is laminated on a silicon substrate on which an active region is formed to serve as a conductive layer for wiring, and a single crystal layer such as a single crystal spinel film is further layered on the laminated Ni silicide film 7. By stacking the next layer of substrates with an insulating film interposed therebetween and repeating these steps, it is possible to form a semiconductor three-dimensional circuit element made of single crystal and having excellent characteristics.
したがつて前記実施例によると、イオンのミキ
シング効果によりスピネル膜５の全面にわたつて
Niシリサイド膜７をエピタキシヤル成長させる
ことができ、しかもNiシリサイド膜７の結晶成
長速度がMBEに比べ約10倍速くなるため、半導
体装置８のスループツトの向上を図ることができ
る。 Therefore, according to the embodiment, the ion mixing effect spreads over the entire surface of the spinel film 5.
Since the Ni silicide film 7 can be grown epitaxially and the crystal growth rate of the Ni silicide film 7 is about 10 times faster than that of MBE, the throughput of the semiconductor device 8 can be improved.
また、Si+のイオン化蒸着におけるイオンエネ
ルギを数KeVないし数10KeVにしたため、イオ
ン注入法の場合のように欠陥が発生することもな
く、特性の優れた半導体装置８を作成することが
できる。 Further, since the ion energy in the ionized deposition of Si + is set to several KeV to several tens of KeV, a semiconductor device 8 with excellent characteristics can be produced without generating defects unlike in the case of ion implantation.
さらに、この半導体装置８を半導体立体回路素
子の各配線用導電層に適用することにより、単結
晶からなる特性の優れた半導体立体回路素子を容
易に提供することができ、非常に実用的である。 Furthermore, by applying this semiconductor device 8 to each wiring conductive layer of a semiconductor three-dimensional circuit element, it is possible to easily provide a semiconductor three-dimensional circuit element with excellent characteristics made of a single crystal, which is very practical. .
しかも、Ni蒸着膜６をイオン化蒸着の前に形
成したため、Si+によるチヤージアツプを防止す
ることができ、イオンのミキシング効果を有効に
高めることができる。 Furthermore, since the Ni vapor deposition film 6 is formed before ionization vapor deposition, charge up due to Si + can be prevented, and the ion mixing effect can be effectively enhanced.
なお、単結晶絶縁膜としてスピネル膜５以外
に、サフアイヤ、フツ化カルシウム〔CaF2〕等
の単結晶膜を使用しても、さらに金属膜として
Ni以外にコバルト、パラジウム、白金を使用し
ても、この発明を同様に実施することができる。 Note that even if a single crystal film such as saphire, calcium fluoride [CaF 2 ], etc. is used in addition to the spinel film 5 as a single crystal insulating film, it will not work as a metal film.
This invention can be carried out in the same manner even if cobalt, palladium, or platinum is used in place of Ni.
第１図ないし第３図はそれぞれ従来のNiシリ
サイド膜の形成過程を示す断面図、第４図ａ〜ｄ
はこの発明の半導体装置の製造方法の１実施例を
示し、製造過程を示す断面図である。
５……単結晶スピネル膜、６……Ni蒸着膜、
７……Niシリサイド膜、８……半導体装置。
Figures 1 to 3 are cross-sectional views showing the process of forming a conventional Ni silicide film, and Figures 4 a to d
1A and 1B are cross-sectional views showing one embodiment of a method for manufacturing a semiconductor device according to the present invention, and illustrating a manufacturing process. 5... Single crystal spinel film, 6... Ni vapor deposited film,
7...Ni silicide film, 8...Semiconductor device.
Claims (1)
ネルギ数KeVないし数10KeVの半導体イオンを
イオン化蒸着法により前記金属膜に照射して前記
絶縁膜上に単結晶導電膜を形成し、前記絶縁膜お
よび前記導電膜からなる半導体装置を作成するこ
とを特徴とする半導体装置の製造方法。1. A metal film is deposited on a single crystal insulating film, and the metal film is irradiated with semiconductor ions having an ion energy of several KeV to several tens of KeV by an ionization vapor deposition method to form a single crystal conductive film on the insulating film. 1. A method for manufacturing a semiconductor device, comprising the steps of: manufacturing a semiconductor device comprising a film and the conductive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59130033A JPS6110234A (en) | 1984-06-26 | 1984-06-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59130033A JPS6110234A (en) | 1984-06-26 | 1984-06-26 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6110234A JPS6110234A (en) | 1986-01-17 |
| JPH038103B2 true JPH038103B2 (en) | 1991-02-05 |
Family
ID=15024483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59130033A Granted JPS6110234A (en) | 1984-06-26 | 1984-06-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6110234A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9044671B2 (en) | 2005-08-24 | 2015-06-02 | Nintendo Co., Ltd. | Game controller and game system |
-
1984
- 1984-06-26 JP JP59130033A patent/JPS6110234A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9044671B2 (en) | 2005-08-24 | 2015-06-02 | Nintendo Co., Ltd. | Game controller and game system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6110234A (en) | 1986-01-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |