JPH038584B2 - - Google Patents
Info
- Publication number
- JPH038584B2 JPH038584B2 JP57145335A JP14533582A JPH038584B2 JP H038584 B2 JPH038584 B2 JP H038584B2 JP 57145335 A JP57145335 A JP 57145335A JP 14533582 A JP14533582 A JP 14533582A JP H038584 B2 JPH038584 B2 JP H038584B2
- Authority
- JP
- Japan
- Prior art keywords
- probe
- probe card
- stage
- semiconductor
- stages
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Measuring Leads Or Probes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】
技術分野
この発明は半導体ウエーハに整列して形成され
た多数の半導体素子を個々に特性測定する方法
で、詳しくはプローブカードから突設されたプロ
ーブニードルに可動ステージ上に保持された半導
体ウエーハの半導体素子を1つずつ電気的接触さ
せる方式の特性測定方法の改良に関する。[Detailed Description of the Invention] Technical Field The present invention relates to a method for individually measuring the characteristics of a large number of semiconductor elements formed in alignment on a semiconductor wafer. The present invention relates to an improvement in a method for measuring characteristics in which semiconductor elements of a held semiconductor wafer are brought into electrical contact one by one.
背景技術
通常、トランジスタやICなどの半導体素子の
特性測定は1枚の半導体ウエーハに複数個が一括
して形成された段階で行われている。この種の半
導体素子特性測定は1つの半導体素子の表面電極
群に当接するパターンのプローブニードル群を有
するプローブカードを用いて行う方式が一般的
で、その従来例を第1図及び第2図の具体的装置
でもつて説明する。BACKGROUND ART Characteristics of semiconductor elements such as transistors and ICs are usually measured after a plurality of semiconductor elements are formed on a single semiconductor wafer. This type of semiconductor device characteristic measurement is generally carried out using a probe card that has a pattern of probe needles that come into contact with the surface electrodes of one semiconductor device. A specific device will also be explained.
第1図及び第2図において、1は半導体ウエー
ハ(以下単にウエーハと称す)、2はウエーハ1
に行・列状の配列で形成された複数の半導体素子
(以下単に素子と称す)、3はウエーハ1を上面で
水平に保持する可動式ステージ、4はステージ3
を水平なX、Y方向と垂直なZ方向の上下に適宜
間歇移動させるステージ駆動制御部である。5は
ステージ3の上方定位置に固定配置された水平な
プローブカード、6はプローブカード5を支持し
て外部の特性測定回路を組込んだテスター7に電
気的配線するソケツトである。プローブカード5
は中央部に1つの窓孔8を有し、この窓孔8の周
縁から中央部下方に向けて複数本のプローブニー
ドルからなるプローブニードル群9が突設され
る。1つ1つのプローブニードルは先端が1つの
半導体素子2の表面電極の1つ1つに当接するパ
ターンで形成され、各プローブニードルはプロー
ブカード5とソケツト6を介してテスター7に配
線される。 1 and 2, 1 is a semiconductor wafer (hereinafter simply referred to as a wafer), 2 is a wafer 1
A plurality of semiconductor elements (hereinafter simply referred to as elements) are arranged in rows and columns, 3 is a movable stage that holds the wafer 1 horizontally on its upper surface, and 4 is a stage 3.
This is a stage drive control unit that moves the stage intermittently up and down in the horizontal X and Y directions and the vertical Z direction. 5 is a horizontal probe card fixedly arranged above the stage 3, and 6 is a socket for supporting the probe card 5 and electrically wiring it to a tester 7 incorporating an external characteristic measuring circuit. probe card 5
has one window hole 8 in the center, and a probe needle group 9 consisting of a plurality of probe needles is provided protruding from the periphery of the window hole 8 toward the lower part of the center. Each probe needle is formed in a pattern in which its tip abuts each surface electrode of one semiconductor element 2, and each probe needle is wired to a tester 7 via a probe card 5 and a socket 6.
上記装置による特性測定動作は先ず、ステージ
3上のウエーハ1をプローブカード5に対して目
合せする。次にステージ3をX、Y、Z方向に間
歇移動させてウエーハ1での素子2を1つずつプ
ローブカード5の中央の測定ポジシヨンへ順次に
送り込み、測定ポジシヨンで順次に素子2の表面
電極群をプローブニードル群9に接触させてテス
ター7でもつて特性測定を行う。1つの素子2の
特性測定結果が良と出ると次の素子2の測定動作
へ連続して移行し、特性測定結果が不良と出ると
不良素子表面に不良識別マークを形成させる。こ
の不良識別マークを形成する手段には不良素子表
面にインクを塗布するマーキングペンや、引掻き
傷を付けるピンなどが用いられ、これらペンやピ
ンはプローブカード5の窓孔8上方に待機し、不
良素子がくると下降して不良識別マークを付ける
動作をする。このような不良識別マークは後工程
で素子2を良品と不良品に選別する時に利用され
る。また不良素子に不良識別マークを付ける代り
に不良素子のウエーハ1に対する位置をマイクロ
コンピユータに記憶させて、この記憶内容に基づ
いて後の選別処理を行うことも最近は実行されて
いる。 In the characteristic measuring operation by the above apparatus, first, the wafer 1 on the stage 3 is aligned with the probe card 5. Next, the stage 3 is moved intermittently in the X, Y, and Z directions to sequentially feed the elements 2 on the wafer 1 one by one to the measurement position in the center of the probe card 5, and at the measurement position, the surface electrodes of the elements 2 are sequentially moved. is brought into contact with the probe needle group 9 and the characteristics are measured using the tester 7. When the characteristic measurement result of one element 2 is found to be good, the measurement operation of the next element 2 is successively carried out, and when the characteristic measurement result is found to be poor, a defect identification mark is formed on the surface of the defective element. A marking pen that applies ink to the surface of the defective element or a pin that scratches the surface of the defective element is used as means for forming this defective identification mark. When the element arrives, it moves down and attaches a defect identification mark. Such a defective identification mark is used in a later process when the elements 2 are sorted into good and defective products. Furthermore, instead of attaching a defect identification mark to a defective element, it has recently been practiced to store the position of the defective element with respect to the wafer 1 in a microcomputer, and to perform subsequent selection processing based on the stored contents.
ところで、テスター7が1つの素子2を特性測
定するに要する測定時間をTとすると、上記装置
は第3図に示すタイムチヤートの如く動作を繰返
す。即ち、1つの素子2の測定完了後ステージ3
が定ピツチ下降し、横に定ピツチ移動し、そして
定ピツチ上昇して次の素子2の測定が開始され
る。このステージ移動の間のテスター7は動作せ
ずに待機し、この待ち時間Wは約0.3〜0.5秒程度
必要とされ、これがため1枚のウエーハ1の素子
2の全ての特性測定を完了するまでに長時間を要
し、インデツクス改善が難しかつた。 By the way, if the measurement time required for the tester 7 to measure the characteristics of one element 2 is T, the above-mentioned apparatus repeats the operation as shown in the time chart shown in FIG. That is, after completing the measurement of one element 2, stage 3
is lowered by a fixed pitch, moved laterally by a fixed pitch, and then raised by a fixed pitch, and measurement of the next element 2 is started. During this stage movement, the tester 7 does not operate and waits, and this waiting time W is approximately 0.3 to 0.5 seconds. It took a long time to complete the process, and it was difficult to improve the index.
このような測定時間の無駄を少なくする方式と
して、上記同様なステージとプローブカードの組
を2組並設し、2つのプローブカードを1つのテ
スターに配線しておいて、一方の組で1枚のウエ
ーハの素子の特性測定を行つている間に他の組で
ステージ移動を行うものがある。この方式による
と共用されるテスターはほぼ連続的に動作して待
ち時間が大幅に短縮されるが、2台のステージを
並設するため全体の設置床面積が甚大となるこ
と、2台のステージ上のウエーハとプローブカー
ドとの目合せに大変手間取つて全体の作業時間の
短縮化にあまり効を奏さないことなどの問題があ
つた。 As a method to reduce such wasted measurement time, two sets of stages and probe cards similar to those described above are installed in parallel, and the two probe cards are wired to one tester. While measuring the characteristics of the elements on one wafer, another group moves the stage. According to this method, the shared tester operates almost continuously and the waiting time is greatly reduced, but since the two stages are installed side by side, the total installation floor space becomes extremely large, and the two stages There was a problem that it took a lot of time to align the upper wafer and the probe card, and it was not very effective in shortening the overall working time.
また水平なステージ上方にプローブカードを設
置するもので、不良素子表面に不良識別マークを
付すものであると、不良素子表面へのマーキング
時にインクや引掻き傷による屑が不良素子周辺に
並ぶ素子へと飛散して落下付着し、その素子が良
品であつても不良品とする不都合があり、改善策
が要望されていた。 In addition, if a probe card is installed above a horizontal stage and a defect identification mark is attached to the surface of a defective element, ink and scratches may be deposited on the elements surrounding the defective element when marking the surface of the defective element. There is an inconvenience that the element scatters, falls and adheres to the element, and even if the element is good, it becomes a defective item, and an improvement measure has been desired.
発明の開示
本発明はかかる従来の各問題点に鑑みてなされ
たもので、1枚のプローブカードの両面にプロー
ブニードル群を突設して2枚のウエーハの素子の
特性測定を交互に行うようにした半導体素子特性
測定方法を提供する。DISCLOSURE OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the prior art, and has a structure in which probe needle groups are provided protruding from both sides of one probe card to alternately measure the characteristics of elements on two wafers. A method for measuring semiconductor device characteristics is provided.
本発明は両面にプローブニードル群を有するプ
ローブカードと、このプローブカードの両面に平
行に対向させて計2枚のウエーハを保持する計2
台のステージの三者を平行及び垂直方向に相対的
に間歇移動させることで実行される。プローブカ
ードの2つのプローブニードル群は1つのテスタ
ーに配線され、2台のステージの一方は他方のス
テージのウエーハの素子が1つのプローブニード
ル群に接触して特性測定をされている間に位置移
動し、これによりテスターの待ち時間が短縮化さ
れてインデツクスが大幅に向上する。上記三者の
最も有効な配置は三者共に鉛直な縦配置である
が、水平な横配置であつてもインデツクス的な効
果には変りない。 The present invention includes a probe card having probe needle groups on both sides, and a total of two wafers that hold two wafers parallel to each other on both sides of the probe card.
This is carried out by intermittently moving the three stages of the stand relatively in parallel and perpendicular directions. The two groups of probe needles on the probe card are wired to one tester, and one of the two stages moves while the elements of the wafer on the other stage are in contact with one group of probe needles to measure their characteristics. However, this reduces tester waiting time and significantly improves the index. The most effective arrangement of the above three is a vertical arrangement in which all three are arranged vertically, but even if they are arranged horizontally and horizontally, the indexing effect remains the same.
発明を実施するための最良の形態
上記三者を縦配置した本発明の具体的実施装置
例を第4図に示すと、10は鉛直方向に固定配置
された1つのプローブカード、11及び12はプ
ローブカード10の両面に突設した2つの第1、
第2プローブニードル群、13は第1、第2プロ
ーブニードル群11,12を配線する1つのテス
ターである。14及び15はプローブカード10
の両側に平行に配置された2台の可動式第1、第
2ステージで、各々の内面に1枚ずつウエーハ1
6,17が真空吸着等の手段で保持され、各ウエ
ーハ16,17はプローブカード10の両面に平
行に対向する。18及び19は各ステージ14,
15を独立して鉛直方向及びプローブカード10
と直交する水平方向の上下左右方向に間歇送りし
て各々のウエーハ16,17の各素子20,21
を対応する各プローブニードル群11,12に接
触する測定ポジシヨンに順次に送り込むステージ
駆動制御部である。BEST MODE FOR CARRYING OUT THE INVENTION FIG. 4 shows a specific example of an apparatus for carrying out the present invention in which the above three components are vertically arranged. 10 is one probe card fixedly arranged in the vertical direction; 11 and 12 are Two first ones protruding from both sides of the probe card 10,
The second probe needle group 13 is one tester for wiring the first and second probe needle groups 11 and 12. 14 and 15 are probe cards 10
Two movable first and second stages are arranged parallel to each other on both sides of the
The wafers 6 and 17 are held by means such as vacuum suction, and each wafer 16 and 17 faces both surfaces of the probe card 10 in parallel. 18 and 19 are each stage 14,
15 independently in the vertical direction and the probe card 10
The elements 20 and 21 of each of the wafers 16 and 17 are intermittently fed in the vertical and horizontal directions perpendicular to the horizontal direction.
This is a stage drive control unit that sequentially sends the probe needles to the measurement positions where they come into contact with the corresponding probe needle groups 11 and 12.
この第4図装置は第5図のタイムチヤートの要
領で測定動作を行う。先ず第1、第2ステージ1
4,15にウエーハ16,17をセツトし、ウエ
ーハ16,17をプローブカード10に対して目
合せする。この目合せは両ウエーハ16,17が
プローブカード10の両面に対向しているので同
時且つ容易に行える。測定動作は例えば先ず第1
ステージ14をプローブカード10の方向に定ピ
ツチ送りしてウエーハ16の1つの素子20の表
面電極群を第1プローブニードル群11に接触さ
せてこの素子20の特性測定を行う。測定が完了
して第1ステージ14をプローブカード10から
離すと同時に第2ステージ15をプローブカード
10の方向に定ピツチ送りして別のウエーハ17
の1つの素子21を、第2プローブニードル群1
2に接触させて特性測定を行う。この測定時間の
間に第1ステージ14を次の素子20が第1プロ
ーブニードル11と対向する位置まで移行させて
待機させておく。第2プローブニードル12によ
る素子21の特性測定が完了して第2ステージ1
5がプローブカード10から離れる時点で第1ス
テージ14を再度プローブカード10に近付けて
2個目の素子20の特性測定を行い、この間第2
ステージ15を次の素子21が第2プローブニー
ドル群12に対向する位置まで移行させて待機さ
せておく。以後上記動作を繰り返し、第1、第2
プローブニードル11,12で交互に素子20及
び21の特性測定を行う。このようにするとテス
ター13は待ち時間無く連続して素子の特性測定
を行い、作業能率が最大となる。 The apparatus shown in FIG. 4 performs measurement operations in accordance with the time chart shown in FIG. First, 1st and 2nd stage 1
The wafers 16 and 17 are set on the probe cards 4 and 15, and the wafers 16 and 17 are aligned with the probe card 10. This alignment can be performed simultaneously and easily since both wafers 16 and 17 face both sides of the probe card 10. For example, the measurement operation starts with the first
The stage 14 is moved at a fixed pitch in the direction of the probe card 10 to bring the surface electrode group of one element 20 of the wafer 16 into contact with the first probe needle group 11 to measure the characteristics of this element 20. When the measurement is completed, the first stage 14 is separated from the probe card 10, and at the same time, the second stage 15 is moved in the direction of the probe card 10 by a fixed pitch to transfer another wafer 17.
one element 21 of the second probe needle group 1
2 to measure the characteristics. During this measurement time, the first stage 14 is moved to a position where the next element 20 faces the first probe needle 11 and is kept on standby. After the characteristic measurement of the element 21 by the second probe needle 12 is completed, the second stage 1
5 leaves the probe card 10, the first stage 14 is brought close to the probe card 10 again and the characteristics of the second element 20 are measured.
The stage 15 is moved to a position where the next element 21 faces the second probe needle group 12 and is kept on standby. After that, repeat the above operation, and
The characteristics of the elements 20 and 21 are measured alternately using the probe needles 11 and 12. In this way, the tester 13 continuously measures the characteristics of the elements without waiting time, and the work efficiency is maximized.
上記動作で測定結果が不良と出た素子に対し、
その素子表面に不良識別マークを付す場合を考え
る。この時、インクや引掻き傷によるマーキング
動作でインクや引掻き傷による屑が飛ぶが、これ
はウエーハが鉛直配置のためウエーハ上に落下す
ることなく排除されるので不良素子周辺の良品素
子は安全である。不良識別マークをマーキングす
るペンやピン等のマーカはプローブカードの板厚
を大きくしてその中に収納させればよい。また不
良識別マークを不良素子に付す代りに不良素子の
位置をマイクロコンピユータに記憶させる場合は
プローブカードを十分に薄くすればよい。 For elements whose measurement results are found to be defective in the above operation,
Consider the case where a defect identification mark is attached to the surface of the element. At this time, the ink and scratches fly away due to the marking operation, but since the wafer is arranged vertically, this is removed without falling onto the wafer, so the good devices around the defective devices are safe. . A marker such as a pen or pin for marking a defective identification mark may be housed in a thicker probe card. Furthermore, if the position of the defective element is to be stored in the microcomputer instead of attaching a defective identification mark to the defective element, the probe card may be made sufficiently thin.
上記縦配置構造にすると1つのプローブニード
ル、2台のステージの設置床面積が小さくでき、
また重量の比較的大きいステージの水平方向の移
動制御が容易にできるが、本発明はこの縦配置例
に限らず、第4図のプローブカード10、各ステ
ージ14,15を水平にした横置配置の構造にす
ることも可能である。 By using the above vertical arrangement structure, the installation floor space for one probe needle and two stages can be reduced.
Further, although the horizontal movement of a relatively heavy stage can be easily controlled, the present invention is not limited to this example of vertical arrangement, but the present invention is also applicable to a horizontal arrangement in which the probe card 10 and each stage 14, 15 are horizontally arranged as shown in FIG. It is also possible to have a structure of
また本発明は2台のステージを固定式或いは半
固定式にしてプローブカード側を2つのステージ
間に往復動させる構造にしても実行は可能であ
る。 Further, the present invention can be implemented by using a structure in which two stages are fixed or semi-fixed and the probe card side is moved back and forth between the two stages.
以上のように本発明によればプローブカードの
両面のプローブニードル群が待ち時間無く交互に
素子の特性測定を行うので、特性測定装置の大幅
な稼動率向上が図れ、インデツクス改善が実現で
きる。またプローブカードや各ステージを鉛直配
置することが可能で、このようにすることにより
装置全体の床面積の縮小化が図れ、またマーキン
グ屑のウエーハ上への落下付着防止が図れて歩留
りが向上する。 As described above, according to the present invention, the probe needle groups on both sides of the probe card alternately measure the characteristics of the elements without waiting time, so that the operating rate of the characteristic measuring device can be greatly improved and the index can be improved. In addition, the probe card and each stage can be arranged vertically, which reduces the floor space of the entire device and prevents marking debris from falling onto the wafer, improving yield. .
第1図及び第2図は従来方法による半導体素子
特性測定装置の一例を示す要部平面図及び側面
図、第3図は第1図の装置の動作タイムチヤー
ト、第4図は本発明の方法の具体的実施装置例を
示す要部側面図、第5図は第4図の装置の動作タ
イムチヤートである。
10……プローブカード、11,12……プロ
ーブニードル群、14……第1ステージ、15…
…第2ステージ、16,17……半導体ウエー
ハ、20,21……半導体素子。
1 and 2 are a plan view and a side view of essential parts showing an example of a semiconductor device characteristic measuring device using a conventional method, FIG. 3 is an operation time chart of the device shown in FIG. 1, and FIG. 4 is a method according to the present invention. FIG. 5 is a side view of a main part showing a specific example of the apparatus for implementation, and FIG. 5 is an operation time chart of the apparatus shown in FIG. 10... Probe card, 11, 12... Probe needle group, 14... First stage, 15...
...Second stage, 16, 17... Semiconductor wafer, 20, 21... Semiconductor element.
Claims (1)
子を個々に特性測定する方法であつて、半導体素
子の表面電極に当接するパターンのプローブニー
ドル群を両面に突設した1つのプローブカード
と、プローブカードの両面に対向させて半導体ウ
エーハを保持する2つの第1、第2ステージを配
置し、プローブカードを第1、第2ステージ間を
間歇的に往復移動させて、プローブカード両面の
各プローブニードル群に第1、第2ステージの各
半導体ウエーハを交互に近接させて第1、第2ス
テージの半導体ウエーハにおける半導体素子の特
性測定を連続して行うようにしたことを特徴とす
る半導体素子特性測定方法。1 A method for individually measuring the characteristics of a plurality of semiconductor elements formed on a semiconductor wafer, which uses one probe card with a group of probe needles protruding from both sides in a pattern that contacts the surface electrodes of the semiconductor elements; Two first and second stages that hold a semiconductor wafer are arranged facing each other on both sides, and the probe card is intermittently moved back and forth between the first and second stages to attach each probe needle group on both sides of the probe card. 1. A method for measuring characteristics of a semiconductor device, characterized in that semiconductor wafers of the first and second stages are alternately brought close to each other, and characteristics of semiconductor devices on the semiconductor wafers of the first and second stages are successively measured.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57145335A JPS5934641A (en) | 1982-08-20 | 1982-08-20 | Measuring method for characteristic of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57145335A JPS5934641A (en) | 1982-08-20 | 1982-08-20 | Measuring method for characteristic of semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5934641A JPS5934641A (en) | 1984-02-25 |
| JPH038584B2 true JPH038584B2 (en) | 1991-02-06 |
Family
ID=15382787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57145335A Granted JPS5934641A (en) | 1982-08-20 | 1982-08-20 | Measuring method for characteristic of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5934641A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61234543A (en) * | 1985-04-11 | 1986-10-18 | Nippon Maikuronikusu:Kk | Semiconductor wafer prober |
| JP2580288B2 (en) * | 1988-11-17 | 1997-02-12 | 東京エレクトロン 株式会社 | Wafer prober |
-
1982
- 1982-08-20 JP JP57145335A patent/JPS5934641A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5934641A (en) | 1984-02-25 |
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