JPH0410077B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device that artificially adds reverberation to a music signal, etc., and when generating reverberant sound by superimposing multiple delay data (convolution operation), coefficient calculation is performed. By grouping and executing processing, it is possible to easily set and change coefficient parameters, thereby facilitating the setting operation of reverberation characteristics.

When artificially adding reverberation to music signals, etc., the most direct electronic method is to express it as a superposition of signals with various time delays from the direct sound, corresponding to the impulse response of a virtual room. It's a method. As shown in FIG. 1a, this method uses a delay memory 1 having a multi-tap, and transmits a delayed signal from each tap to an amplitude adjuster 2-1.
2-2, . . . , 2-n by an adder 3. In the apparatus shown in FIG. 1a, a reverberation signal xout= _o 〓 ⁱ⁼¹ x _i ·g _i is obtained as the output x out. where x _i is the input signal
The signal obtained by delaying x _io by time τ _i , g i is the signal obtained by delaying x io by time τ i, and g _i is
This is a gain of 1, 2-2, . . . , 2-n, that is, a coefficient value for each delayed signal x _i . The echo time pattern of the device of FIG. 1a is shown in FIG. 1b.

FIG. 2 shows the simulation results of primary and secondary reflected sounds in a real hall. 1
There were 11 second-order reflections and 24 second-order reflections. If this were simulated artificially using the reverberation adding device shown in Figure 1, 35 taps would be required. Furthermore, since each reflected sound requires a different coefficient, 35 types of gain data settings from g ₁ to _go are required. This is fine if the coefficients are fixed, but there is a demand for changing the reverberation characteristics depending on the situation. When assuming a wide hall, when assuming a narrow hall, or
In order to respond to each case, such as when considering the reflection coefficient of a wall to be large or small,
It becomes necessary to independently reset the 35 coefficient parameters g ₁ to _go . This is quite cumbersome and impractical.

This invention was made in view of the above points,
It is an object of the present invention to provide a reverberation adding device that facilitates the setting and changing of coefficient parameters and facilitates the setting operation of reverberation characteristics.

According to the present invention, the above object is achieved by dividing a plurality of delayed signals into several groups so that coefficients can be set and changed for each group.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

In FIG. 3, the delay memory 5 has n output taps with delay times τ ₁ to τ _o . Delayed signals x ₁ to x _o obtained from each output tap are subjected to coefficient assignment by amplitude adjusters (first coefficient calculation units) 6-1 to 6-n, each having a gain _of g ₁ to go.

The delayed signals g ₁ · x ₁ to go · x _o outputted from the amplitude adjusters 6-1 to 6-n are _divided into three groups (g ₁ · x ₁ to g _a · x _a , g _{a +1} · x _a+1 to g _b・x _b ,
g _b+1・x _b+1 to g _o・x _o ), and the adder 7
Add each group with ~9 (convolution operation)
Then, the adders 7 to 9 output the next signal xout1 to
xout3 is output respectively.

xout1= _a 〓 ⁱ⁼¹ g _i・x _i (1) xout2= _b 〓 ^i=a+1 g _i・x _i (2) xout3= _o 〓 ^i=b+1 g _i・x _i (3) and , the outputs xout1 to xout3 of adders 7 to 9 are
F ₁ to _{F 3} in the second coefficient calculation units 10 to 12, respectively.
The coefficients are added to the second coefficient calculation unit 10.
~12 output the following signals xout1' to xout3', respectively.

xout1′=F ₁・_a 〓 ⁱ⁼¹ g _i・x _i (1′) xout2′=F ₂・_b 〓 ^i=a+1 g _i・x _i (2′) xout3′=F ₃・_o 〓 ^i=b+1 g _i ·x _i (3') These signals xout1' to xout3' are added by an adder 13 and output as a reverberation signal.

According to the above configuration, the basic coefficient is 6-1 to 6
−n gains g ₁ to _{g o} according to the decay characteristics of the reverberation (g ₁ is the maximum, g ₂ ,
g ₃ , . . . ), parameters can be set and changed using only the coefficients F ₁ to F ₃ of the second coefficient calculation units 10 to 12. For example, even when n=40, parameter settings and changes can be made using only three coefficients F ₁ to F ₃ , making it easy to set and change parameters.

It should be noted that the second coefficient calculation units 10 to 12 may be configured to simply perform multiplication (that is, a normal amplitude adjuster), but more effective coefficient assignment can be realized if they are configured with filters. In this case, a low-pass filter is generally suitable as a filter characteristic because natural reverberant sound is attenuated more at higher frequencies. The order of the low-pass filter can be 1st order or higher order than 2nd order, but even about 1st order is sufficiently effective.

FIG. 4 shows an echo pattern obtained by the reverberation adding device shown in FIG. 3. When a signal with a longer delay has a higher attenuation (smaller reflection coefficient) (echo pattern shown by a dashed-dotted line), it feels like a so-called dead state (reverberation time is short), and conversely, a signal with a longer delay has a smaller attenuation (larger reflection coefficient). (echo pattern shown by a solid line), it feels live (a state with a long reverberation time).In this way, liveness control is possible with just a few parameter settings, and it is easy to operate, even for inexperienced users. It has the advantage of being manipulable.

When the second coefficient calculating sections 10 to 12 are constructed of filters, for example, a digital filter (comb filter) as shown in FIG. 5 can be used. This is such that an adder 16 adds the input signal passed through the amplitude adjuster 17 and the signal passed through the amplitude adjuster 18 from the delay circuit 15 that delays the input signal by one sampling. . In such a configuration, the amplitude adjusters 17, 18
By combining the gains A and B, various filter characteristics as shown in FIG. 6 can be obtained. Therefore, if this is used in the second coefficient calculation units 10 to 12 and the coefficients F ₁ to _{F 3} are set independently, the result will be as shown in FIG. 7, and six parameters (A ₁ to A ₃ , B ₁ to B ₃ ) can be set.

Next, a specific example of the configuration of the reverberation adding device shown in FIG. 3 will be explained. Here, a case will be described in which the second coefficient calculating sections 10 to 12 are configured as digital filters as shown in FIG. 7.

In FIG. 8, the data memory 20 includes a memory area for sequentially storing input samples to create a delayed signal, and an accumulator for calculating the digital filter in FIG. 7, as shown in FIG. 29, and a memory area for temporarily storing the delayed signal cumulative values of each group. The latter temporary storage memory area for filter calculation has three addresses for storing cumulative values Xout1 to Xout3 of each group based on grouping based on the write address (hereinafter referred to as current address) m of the current input sample; Cumulative value of each group based on grouping based on write address m-1 of previous input sample [Xout1] ~
It has a total of six addresses for storing [Xout3]. The multiplexer 35 is for switching the input signal of the data memory 23 to the input sample or the output data of the accumulator 29.

As shown in FIG. 10, the parameter memory 20 stores data regarding addresses of the data memory 23: 〓 ₁ /τ ₀ to 〓 _o /τ ₀ (integer), α, β, γ, X, Y, .
Z
and gain data g ₁ to _{g n} , A ₁ to A ₃ , and B ₁ to _{B 3} are stored in pairs. Here, τ ₀ is one sampling period of the input signal, and 〓 ₁ /τ ₀ ~ 〓 _o /
τ ₀ is subtracted by the subtracter 27 from the current address m counted by the counter 24 as delay time data indicating how many samples ago. This subtracted value is then added to the data memory 23 as data indicating the read address of the input sample stored in the data memory 23. α, β, γ are cumulative values of each group based on the current address m
This is data for calculating the position of the address for temporarily storing Xout1 to Xout3. In addition, X, Y, and Z are the accumulated values of each group [Xout1] to the reference address m-1 where the previous sample was written.
This is the address to temporarily store [Xout3] (9th
(see figure). These α, β, γ, X, Y, and Z are relative addresses based on the current address m, and are subtracted by the subtracter 27 from the current address m counted by the counter 24, and are stored in the data memory 23. Each group cumulative value xout1~xout3, [xout1]~
It is added to the data memory 23 as address data indicating the address where [xout3] is stored. Therefore, the values of α, β, γ, X, Y, and Z are the current address m
For example, as shown in Figure 9, the write address (absolute address) of the accumulated value is -6,
-5,...,-1, it should be m-X=-6 m-Y=-5 m-Z=-4 m-α=-3 m-β=-2 m-γ=-1 Therefore, X, Y, Z, α, β, γ
are set as follows.

X=m+6 Y=m+5 Z=m+4 α=m+3 β=m+2 γ=m+1 Writing of each of the above parameters into the parameter memory 20 is performed by the parameter controller 12 based on the operation of the keyboard 21.

As described above, the counter 24 indicates the current address m at which writing is to be performed in the data memory 23, and is incremented every sample period of the input signal.

The counter 25 indicates the read address of the parameter memory 20, and reads each parameter shown in FIG. 10 by going around the addresses of the parameter memory 20 in one sampling period of the input signal.

The multiplexer 26 converts the address data given to the parameter memory 20 into the write address from the parameter controller 22 or the counter 25.
This is to switch to the read address from .

As described above, the subtracter 27 converts the address data (relative address) read from the parameter memory 20 into an absolute address based on the current address m indicated by the count 24,
3 as address data.

The multiplier 28 adds gain data g _{1 to g o read from the parameter memory 20 to the delay signals x 1 to x o read from} the data memory 23, and also adds the cumulative value of each group read from the data memory 23. Add gain data A ₁ to A ₃ , B ₁ to B 3 to xout1 to xout3, [xout1] to [ _xout3] and set the above (1')
This is to find xout1' to xout3' in equations (3') to (3').

The accumulator 29 accumulates (convolution operation) the delayed signal output from the multiplier 28 for each group using a register 35 and an adder 30, and calculates the result as shown in equations (1) to (3) above. Accumulated data xout1~
xout3, and also accumulates each group's accumulated data xout1' to xout3' outputted from the multiplier 28 to finally produce a reverberation signal.
The AND circuit 31 is turned off by the signal C3 to reset the accumulated value to 0 every time the accumulated data of each group and the final reverberation data are created.

The timing controller 32 creates each timing signal C1 to C6 for operating each of the above-mentioned circuits.

Next, the operation of the apparatus shown in FIG. 8 will be explained.

(1) Setting parameters When using the reverberation adding device shown in Fig. 8, delay time data τ ₁ ~τ _o , gain data g ₁ ~ _go , A ₁ ~
Set each parameter of A ₃ , B ₁ to B ₃ . Parameter settings are controlled by a parameter controller 22. That is, in accordance with the operation of the keyboard 21, the parameter memory 20 is switched to the write mode, the multiplexer 26 is switched to the setting mode, and parameters are set.

(2) Creation of reverberant signal After setting the parameters, switch the parameter memory 20 to read mode, switch the multiplexer 26 to the counter 25 side, and read the data memory 20.
3 to create a reverberant signal.

The reverberation signal is created by using one sampling period of the input signal x _io as one unit, and executing the following calculation within that unit. Data memory 23
Writing input signal x _io to. Data memory 23
Read out delay signals x ₁ to x _o corresponding to each delay time τ ₁ to τ _o set from . Each delayed signal read out
Assignment of coefficients g ₁ to _{g o} to x ₁ to x _o . Group-wise accumulation of coefficiented delayed signals. Data memory 2 for cumulative data xout1 to xout3 of each group
Writing to 3. Reading cumulative data xout1 to xout3 of each group and previous cumulative data [xout1] to [xout3] from the data memory 23. Read cumulative data xout1 to xout3, [xout1] to
Assignment of coefficients A ₁ to A ₃ , , B ₁ to _{B 3} to [xout3].
Accumulation of factored cumulative data.

Each step will be explained with reference to the time chart in FIG. 11.

Writing the input signal to the data memory 23 When the clock C1 rises, the clock C4 becomes low level and the counter 25 is cleared. Therefore, the address 0 is specified in the parameter memory 20, and the delay time data 〓i/τ ₀ and the gain data g _i
Both are read as "0" (see FIG. 10). Then, when the next clock C5 rises, the clock C2 also rises, and the data memory 23 enters the write state.
At this time, since the delay time data 〓i/τ ₀ from the parameter memory 20 is "0" as described above,
The output of the subtracter 27 is the output of the counter 24, that is, the current address itself, and the input signal is written to the current address m indicated by the counter 24 in the data memory 23.

Reading the delayed signal from the data memory 23 When writing to the data memory 23 is completed, the data memory 23 enters the read mode. The counter 25 counts the clock C5, adds the counted value to the parameter memory 20, and reads out each parameter of delay time data 〓i/τ ₀ and gain data g _i . For example, when the count value of the counter 25 is "1", the delay time data τ ₁ /τ ₀ and the gain data g _i are read from address 1 of the parameter memory 20. Further, τ ₂ /τ ₀ and g ₂ from address 2, τ _o /τ ₀ and go from address _n are read out in sequence.

The delay time data 〓i/τ ₀ read from the parameter memory 20 is subtracted from the count value of the counter 24 by the subtracter 27, and from the subtracter 27, the count value of the counter 24, that is, the current address m is used as a reference. Delay time data 〓i/τ ₀ The address data in front is output by the distance indicated by 0, and the data memory 2
3, the delay signal x _i stored at the corresponding address is read out.

First coefficient assignment The delayed signal read out from the data memory 23 is x _i
In the multiplier 28, the parameter memory 20
Each corresponding gain data g i read out from the data g _i is provided.

Accumulation The delayed signal g _i ·x _i output from the multiplier 28 is accumulated by the accumulator 29 . Each time the accumulation result for each group is obtained, the accumulator 29 is reset by the clock C3, and the accumulation for the next group is continued.

Writing the accumulation results to the data memory 13 Before the accumulation values xout1 to xout3 of each group are reset, the multiplexer 35 is switched to the accumulator 29 side by the clock C6, and the data memory 23 is set to the write mode by the clock C2. α, from the parameter memory 20
The data of β and γ are output and the data memory 23
is written to a predetermined address (see FIG. 9).
These accumulated values xout1 to xout3 are held until the end of the next sampling period because the previous accumulated value is required in the calculation of the filter shown in FIG.

Reading the current and previous cumulative values from the data memory 23 The cumulative value xout1 of each group is stored in the data memory 23
~xout3 are respectively stored, the data X,
Y, Z, α, β, and γ are sequentially output, and the previous cumulative values [xout1] to [xout3] of each group and the current cumulative values xout1 to xout3 of each group are sequentially read from the data memory 23. .

Adding a second coefficient to each accumulated value From the data memory 23, the accumulated values of each group [xout1] to [xout3], xout1 to
When xout3 is read out, coefficients B ₁ , B ₂ , B ₃ , A ₁ , A ₂ ,
A ₃ is sequentially output, and the multiplier 28 outputs the second
are given coefficients.

Accumulation of Accumulated Data with Second Coefficient Added The data output from the multiplier 28 after the second coefficient has been added is accumulated in the accumulator 29 to finally obtain a reverberant signal. This reverberation signal is then D/A converted and output.

The reverberation characteristics can be easily changed by changing the values of six pieces of gain data A ₁ to _{A 3} and B ₁ to B ₃ stored in the parameter memory 20.

In the above embodiment, the reverberation signal output was made into a single channel, but as shown in FIG. 12, the memory area of the delay memory (data memory) 40 is divided, and each channel has the configuration shown in FIG. 3. By applying this, the same delay memory 40 can be shared and multi-channeled.

Further, the number of delayed signals assigned to each group does not necessarily need to be equal. For example, if we note that reflected sounds with short delay times (low-order reflected sounds) generally have a larger gain (that is, a larger proportion of the reverberant signal), It is preferable to control the delay time as many groups as the delay time is longer, from the viewpoint of not impairing natural reverberation and improving operability. FIG. 13 shows such a configuration. Note that the first
In FIG. 3, the reverberation output of two channels is extracted, similar to that in FIG. 12.

By the way, since this invention is a feed-forward type reverberation device, the reverberation time is limited by the memory capacity, but if a longer reverberation effect is required, a known regression type reverberation device or the like may be used. All you have to do is combine them. FIG. 5 shows an example of such a configuration. The reverberation adding device 50 is the reverberation adding device shown in FIG. 12 to which the present invention is applied. The rear reverberation adding device 51 is a regression type reverberation device, and the input signal is passed through a delay circuit (delay time τ _d ) 52,
By performing regression via an amplitude adjuster (gain gfb) 53 and an adder 54, a long-term reverberation signal is obtained. The input signal to this rear reverberation addition device 31 is the output of a readout cycle added to the delay memory constituting the reverberation addition device 30, and is given the necessary delay time and gain. There is. The rear reverberation adding device 31 calculates the necessary delay time τ _x and gain g _x
A recurrent reverberation signal is created based on the input signal given. Then, this reverberation signal is added to the L channel and R channel reverberation signals from the reverberation addition device 50 by adders 55 and 56 as a continuous rear reverberation signal after the initial reverberation signal from the reverberation addition device 30. be done. FIG. 15 shows the echo time pattern obtained in this way. In the first half, the reverberation adding device 50 according to the present invention works, and in the second half, the rear reverberation adding device 51 works, so that a long-term reverberation effect is obtained.

Note that, in general, the reverberation characteristics are extremely dominated by the initial reverberation signal, so even if the above-mentioned configuration is used as the rear reverberation signal, a sufficiently practical product can be realized.

As explained above, according to the present invention, a plurality of delayed signals for forming a reverberant signal are divided into several groups, and coefficients can be set and changed for each group. Setting and changing operations can be facilitated.

[Brief explanation of drawings]

Fig. 1a is a block diagram showing a conventional reverberation adding device, Fig. 1b is a diagram showing echo time patterns by the reverberation adding device shown in Fig. 1a, and Fig. 2 is a diagram showing primary and secondary echo time patterns in an actual hall. An echo time pattern showing the simulation result of the next reflected sound,
FIG. 3 is a block diagram showing an embodiment of this invention.
Figure 4 is a diagram showing the control status of the echo time pattern by the reverberation adding device in Figure 3, and Figure 5 is a diagram showing the control status of the echo time pattern by the reverberation adding device in Figure 3.
FIG. 6 is a circuit diagram showing a specific example in which the second coefficient calculation units 10 to 12 shown in the figure are configured with filters, and FIG. 6 shows the characteristics of the filter shown in FIG. FIG. 7 is a diagram showing the situation controlled according to the second coefficient calculation units 10 to 1 in FIG. 3.
FIG. 8 is a block diagram showing a specific configuration example of the reverberation adding device shown in FIG. 3, and FIG. 10 is a memory map of the parameter memory 20 in FIG. 8, FIG. 11 is a time chart showing the operation of the reverberation adding device in FIG. 8, and FIG. 12 is an implementation of the present invention in which the reverberation signal output is multi-channeled. Block diagram showing an example,
FIG. 13 is a circuit diagram showing an example of grouping according to the present invention, in which the number of delayed signals assigned to groups is varied depending on the delay time,
Fig. 14 is a block diagram showing a reverberation adding device which is a combination of the embodiment of the present invention shown in Fig. 12 and a regression type reverberation adding device, and Fig. 15 is a line showing an echo time pattern by the reverberation adding device shown in Fig. 14. It is a diagram. 1, 5, 23, 40...delay memory (data memory), 6-1 to 6-n, 6-1' to 6-
n'...First coefficient calculation section, 7-9, 7'-9'...Distribution addition section, 10-12,, 10'-12'...Second coefficient calculation section, 13, 13'...Final addition section .

Claims (1)

[Claims] 1. A delay memory that stores input signal data at a constant sampling period, and a first delay memory that assigns coefficients to a plurality of data stored in the delay memory.
a plurality of distribution adders that distribute and add the calculation results of the first coefficient calculator to a plurality of groups, and a second coefficient calculator that adds a coefficient to the output of each of the distribution adders. and a final addition section that adds the calculation outputs of the second coefficient calculation section and outputs the result as a reverberation signal.