JPH0412157B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, when a pachinko ball flies into a continuous winning opening, a state in which the winning probability of the winning device starts to increase within a predetermined period of time is maintained, and the winning probability of the winning device continues to increase. This invention relates to a pachinko machine in which when a pachinko ball flies into a continuous winning hole again, the state of increasing winning probability is started again from the beginning.

Conventionally, some pachinko machines use winning balls to increase the winning probability of a winning device. An example of this pachinko machine is the pachinko machine disclosed in Japanese Patent Laid-Open No. 60-34479. This pachinko machine sets different conditions for each of a plurality of specific winning holes, increases the winning probability by changing the variable winning device depending on winnings, and further increases the winning probability by setting different conditions for each winning hole. This creates a situation where the probability of winning is increased.

However, the gaming experience obtained by creating the multiple winning probability increasing states described above,
Improvements are desired to further increase it.

In addition, by appropriately adjusting the timing and force of hitting the ball, the player activates the variable winning device under normal conditions to increase the winning probability and aim the pachinko ball at a specific winning opening in order to generate advantageous rights. In addition, when the variable winning device is operated, the pachinko ball is aimed at the continuous winning hole in order to operate the variable winning device continuously, and when the variable winning device is continuously operating, such advantageous In order to exercise the right efficiently, pachinko balls are aimed at locations where a large number of winning balls can be obtained.

In other words, pachinko balls are not always hit at a constant rate, but in order to reduce the number of wasted balls that are hit due to batting timing and batting force that are inappropriate for each game status, the batting timing and batting force are adjusted according to changes in the game status. He changes his batting power accordingly. As a result, there is a desire for a machine that can clearly identify changes in gaming status.

Therefore, in the present invention, when a pachinko ball flies into a predetermined winning hole and while the winning probability increasing state of the winning device is maintained within a predetermined time, when a pachinko ball flies into the predetermined winning hole, Once again, the increased winning probability is maintained from the beginning for a predetermined period of time, and changes in the gaming status are clearly notified to the player, thereby enhancing the gameplay. An object of the present invention is to provide a pachinko machine that can promote playability.

When the winning probability is increased due to the above-mentioned features, the notification means is activated and the gameplay is enhanced.

An embodiment of the present invention will be described below.

In FIG. 1, 1 is a winning device according to the present invention, and in the center of this winning device 1 are pivots 1a, 1b.
Guide vanes 1c and 1d are provided as movable pieces that open in the direction of picking up pachinko balls from the starting point. That is, the guide vane 1c rotates counterclockwise until it becomes as horizontal as possible, and the guide vane 1d rotates clockwise until it becomes as horizontal as possible. The guide vanes 1c, 1d are linked with rods 2c, 2d forming part of solenoids 2a, 2b as electric drive units, as shown in FIG. The guide vanes 1c, 1d are opened by driving the solenoids 2a, 2b.
At the bottom of the winning device 1, partition plates 3, 3 are set up, and between the partition plates 3, 3 is a continuous winning opening 4 as a special winning opening.
is provided with an 18-times operation winning ball switch 5 for performing 18-times operation forming a special state to be described later as a continuous winnings detector. The above special state is formed when the 18-time operation winning ball switch 5 detects a pachinko that has entered the continuous winning hole 4 during a specific state described later. The above specific state continues during the normal gaming state (hereinafter referred to as the normal state).
It is formed when a pachinko ball flies into two different types of specific winning holes (not shown). As shown in FIG. 3, in one specific winning opening, the winning probability is increased for a predetermined period of time by a winning probability increasing control device, which will be described later as a specific winning detector, to form the specific state. A one-time action winning ball switch 6 is provided to perform the turning action, and in the other two specific winning holes, as shown in FIG. 3,
By increasing the winning probability for a predetermined period of time using a winning probability increase control device as a specific winning detector,
A two-time operation winning ball switch 7 is provided to perform the operation twice in order to form the above-mentioned specific state. On the front of the winning device 1, there is a light emitting diode 8a constituting a display means as part of the notification means.
~8g is placed. The above special status is
During the above-mentioned specific state, pachinko balls continue to appear in the winning hole 4
It is formed when it flies into the

FIG. 3 shows a control circuit for the solenoids 2a and 2b, in which 9 is a flip-flop circuit, 10 is an 8-bit binary counter circuit, 11 is a Schmitt circuit, 12 is a delay circuit, 13 is a reset release control circuit which is a control circuit, 14 is a shift register, 1
5 is a reset timing circuit, 16 is a clock oscillation circuit, 17 is a light emitting diode flashing circuit as a notification means, and 18 is a sound effect generation circuit constituting a display means as a notification means. Bit binary counter circuit 10, Schmitt circuit 11, delay circuit 1
2. The shift register 14, the reset timing circuit 15, and the clock oscillation circuit 16 generally constitute a winning probability increase control device.

The configuration and function of each of these circuits will be explained below.

The flip-flop circuit 9 has set terminals S ₀ ,
_S1 , _S2 , _S3 , output terminals _Q0 , _Q1 , _Q2 , _Q3 , reset terminals _R0 , _R1 , _R2 , _R3 , and ground terminal _E0 ,
Here, the set terminal S ₃ , reset terminal R ₃ , and output terminal Q ₃ are not used. The power supply voltage V _DD is connected to the set terminals S ₀ ,
S ₁ and the Schmitt circuit 11 .
The power supply voltage V _DD is on the high potential side, and when the switches ₆ , ₇ , and ₅ are in the open state as shown in FIG. . When the switch 6 is closed, the set terminal _S0 changes from H to L, and the set terminal _S1
is set from H to L when switch 7 is closed, and the set terminal _S2 is set from H to L when switch 5 is closed. Each output terminal
Q ₀ to Q ₂ are L when each set terminal S ₀ to _{S 2} is H.
output, and when each set terminal S ₀ to S ₂ is L, it becomes H.
It is considered an output. 19 and 20 are OR circuits. The OR circuit 19 outputs a high level when at least one of the output terminals Q ₀ to _{Q 2} of the flip-flop 9 is high, and the OR circuit 20 outputs a high level when any one of the output terminals Q ₁ and Q ₂ is high. It outputs
These OR circuits 19 and 20 have the function of inhibiting the output of each component of the reset timing circuit 15. The Schmitt circuit 11 has an OR gate 21, and the reset release control circuit 13 that controls the winning probability increase control device is composed of a NAND gate, and the output of the Schmitt circuit 11 is inputted to one input terminal of the NAND gate 13. A delay circuit 12 is connected to the other input terminal of the NAND gate 13.
The output of the OR circuit 19 is inputted via the OR circuit 19.
The delay circuit 12 is composed of a group of resistive capacitors, and the function of the delay circuit 12 will be explained together with the configuration of the 8-bit binary counter circuit 10.

The 8-bit binary counter circuit 10 has reset terminals Ra, Rb, and output terminals _Q0a to _Q3a , _Q0b to _Q3b.
and input terminals Ea and Eb. input terminal
Ea is connected to a clock oscillation circuit 16 that generates a clock signal as shown in FIG. 4, and each output terminal _Q0a to _Q3a is configured to generate a rectangular signal as shown in FIG. There is.

The output terminal Q _0a has a period twice that of the clock signal, and has a function of outputting when the first clock signal is input, and the output terminal Q _1a has a period twice that of the clock signal.
It has a cycle that is four times the cycle of the clock signal, and has a function of outputting when the second clock signal is input, and the output terminal _Q2a has a cycle that is eight times the cycle of the clock signal. , has the function of outputting when the fourth clock signal is input, and the output terminal
_Q3a has a period 16 times the period of the clock signal, and has a function of outputting when the eighth clock signal is input.

The output of the output terminal Q _3a is input to the input terminal Eb, and the output terminal Q _0b has a period twice that of the rectangular signal from the output terminal Q _3a , as shown in FIG. It has a function to output according to the first output signal of the rectangular signal from terminal Q _3a , and the output terminal
Q _1b is not used here and is the output terminal
Q _2b has a period eight times that of the rectangular signal from output terminal Q _3a , and has the function of outputting when the fourth output signal of the rectangular signals from output terminal Q _3a is input. , output terminal Q _3b has a period 16 times that of the rectangular signal from output terminal Q _3a , and output terminal
It has a function to output when the 8th output signal of the rectangular signal from Q _3a is input, and the output terminal Q _3b
The output of is inputted to the input terminal CP of the shift register 14 via the inverter element 22.

The shift register 14 has the input terminal CP, the reset terminal R, the power supply potential terminal D, the output terminal Q ₀ ,
Q ₁ and Q ₂ , the output from the NAND gate 13 is input to the reset terminal R, and the power supply potential terminal D is connected to the power supply V _DD .

_{As shown} in FIG.
16th period from output terminal Q _3a .
It has the function of outputting when the th rectangular signal is input, but it is not used here, and the output terminal Q ₁ has a period 64 times that of the rectangular signal from the output terminal Q _3a . It has a function of outputting when the 32nd rectangular signal from output terminal Q _3a is input, and output terminal Q ₂ is not used here.

The reset terminal Ra of the 8-bit binary counter circuit 10 is connected to the delay circuit 12, and the output from the OR circuit 19 is input to the reset terminal Ra with a delay of 0.5 seconds.
This reset terminal Ra releases the output from the output terminal _Q0a when its input is L, and inhibits the output of _Q0a when its input is H.

The output of the NAND gate 13 is input to the reset terminal Rb of the 8-bit binary counter 10, and when the input to the reset terminal Rb is H,
Output from the output terminal _Q0b is prohibited, and when the input to the reset terminal Rb is L, the output from the output terminal _Q0b is released. And the reset terminal
The input of Rb is set to go low at the same time as the input of the reset terminal Ra goes high.

The light emitting diode blinking circuit 17 includes two shift registers 23 and 24, an OR circuit group 25, a light emitting diode drive circuit 26, and a light emitting diode group 27.
It is roughly composed of.

The shift register 23 has input terminals D and CP, a reset terminal R, and output terminals _Q0 to _Q3 .
The reset terminal R of the shift register 23 receives the output from the output terminal _Q2 of the flip-flop circuit 9, and the input terminal CP receives the output from the output terminal _Q0a of the 8-bit binary counter circuit 10. ing.

Outputs from the output terminals Q ₀ to _{Q 3} of the shift register 23 are sent to the shift register 2 via a NOR circuit 28.
The output from the output terminal _Q0 is input to the OR circuit 29 and the OR circuit 35, and the output from the output terminal _Q1 is input to the OR circuit 30 and the OR circuit 34, and the output from the output terminal Q0 is input to the OR circuit 30 and the OR circuit 34. The output from terminal _Q3 is input to OR circuit 31 and OR circuit 33,
The output from the output terminal _Q3 is input to the OR circuit 32.

The light emitting diode drive circuit 26 has input terminals _I0 to
_I6 and output terminals _Q0 to _Q6 , the OR circuit 29 controls the output from the output terminal _Q0 , and the OR circuit 30 controls the output from the output terminal _Q1 . and the OR circuit 31 is the output terminal
The OR circuit ₃₂ controls the output from the output terminal Q ₃ , and the OR circuit 33 controls the output from the output terminal Q ₄ . 34 is the output terminal
The OR circuit ₃₅ controls the output from the output terminal Q ₆ , and the light emitting diodes 8 a and 8 g flash by the output from the output terminal Q ₀ of the shift register 23. The light emitting diodes 8b and 8f are controlled to blink by the output from the output terminal _Q1 of the shift register 23, the light emitting diodes 8c and 8e are controlled to blink by the output from the output terminal _Q2 of the shift register 23, and the light emitting diode 8d is shift register 2
Blinking is controlled by the output from output terminal _Q3 of 3,
The light emitting diode group 27 is configured so that each diode row blinks from the top and bottom toward the center, as shown in FIG. It has a function to repeat this process from the beginning once it is completed.

Note that the reset terminal R of the shift register 23 is
When the input is H, the light emitting diode group 27 has a function of inhibiting the output from the output terminals Q ₀ to _{Q 3} of the shift register 23, and the light emitting diode group 27 inhibits the output from the output terminal Q ₂ of the flip-flop circuit 9. When H, all lights are turned off.

The shift register 24 has reset terminals Ra and Rb.
, input terminals Ca, Cb, Db and output terminals Q _0a ~ Q _3a ,
It has Q _0b to Q _2b .

The reset terminals Ra and Rb of the shift register 24 are input with the output of a NOR gate 36, which will be described later, and the output from the output terminal _Q2 of the flip-flop circuit 9 is input into the NOR gate 36. When the output from the output terminal Q ₂ of the NOR gate 36 is L, the output becomes H, and the shift register 24 is reset. When the output from the output terminal Q ₂ of the flip-flop circuit 9 is H, the NOR gate 36 becomes L, and the reset of the shift register 24 is released. Therefore, when the shift register 23 is in the reset release state, the shift register 24
is in the reset state, and when the shift register 23 is in the reset state, the shift register 24 is in the reset state.
is set in a reset release state.

The Schmitt circuit 11 is connected to the input terminals Ca and Cb of the shift register 24 via an inverter element 37.
The output from is input. shift register 2
The output terminals Q _0a to Q _3a and Q _4b to Q _6b of No. 4 are connected to OR circuits 29 to 35 in order, respectively, and the output from the output terminal Q _3a is fed back to the input terminal Db, and the output terminal Q 4 is fed back to the input terminal Db. _4b to Q _6b receive and output the output from this output terminal Q _3a , and the output terminal Q _6b
The output from the Schmitt circuit 11 is inputted to the other input terminal of the OR gate 21 forming a part of the Schmitt circuit 11.

When the output from the output terminal Q _6b of the shift register 24 is L and the input terminal of the OR gate 21 is H, the output of the OR gate 21 becomes H, and the output from the output terminal Q _6b of the shift register 24 becomes H. L, and when one input terminal of the OR gate 21 is L, the output becomes L, and the shift register 24
When the output of the output terminal _Q6b is H, the output becomes H regardless of whether the input to one input terminal of the OR gate 21 is L or H.

ORGATE 21 is the 18th operation winning ball switch 5
When is opened and closed once, the output changes from H to L, and the output terminal Q _0a of the shift register 24 changes from L to H. Along with this, the light emitting diode 8a
is now lit.

When the 18-time operation winning ball switch 5 is repeatedly opened and closed 8 times, the light emitting diodes 8a to 8g are turned on in this order. When all the light emitting diodes 8a to 8g are lit, the output from the output terminal _Q6b of the shift register 24 becomes H, and the inputs of the other input terminals of the OR gate 21 become H, so
18th operation After winning ball switch 5 opens and closes 8 times,
Regardless of whether the 18th operation winning ball switch 5 is opened or closed,
The output of the OR gate 21 becomes H, and the light emitting diode group 27 is prevented from being lit thereafter.

The reset timing circuit 15 is the AND circuit 3
8, a NAND circuit 39, a NOR gate 40, an inverter element 41, a NOR gate 42, an AND circuit 43 as a control circuit, and a NOR circuit 44. The AND circuit 38 includes the output terminal Q _1a of the 8-bit binary counter circuit 10 and the output terminal
The output of Q _3a is input. nand circuit 39
, the output from the AND circuit 38 and the output from the output terminal _Q0b of the 8-bit binary counter circuit 10 are input. The output from the NAND circuit 39 and the output from the OR circuit 20 are input to the NOR gate 40 . The output from the output terminal Q2b of the 8-bit binary counter circuit 10 and the output from the output terminal _Q2 of the flip-flop circuit ₉ are input to the NOR gate 42 via the inverter element 41. The output from the output terminal _Q2b of the 8-bit binary counter circuit 10 and the output from the output terminal _Q1 of the shift register 14 are input to the AND circuit 43, and the NOR circuit 44 receives the NOR gate 40 and the NOR gate 42. The outputs of the AND circuit 43 and the power supply voltage are input. The output from the NOR circuit 44 is input to each reset terminal R ₀ , R ₁ , R ₂ of the flip-flop circuit 9.
When the output from the NOR circuit 44 is L, outputs from the output terminals Q ₀ to _{Q 2} of the flip-flop circuit 9 are prohibited, and when the output from the NOR circuit 44 is H, the output from each output terminal Q ₀ to Q ₂ of the flip-flop circuit 9 is prohibited. The output from is now being released. The Noah circuit 44 is
When the power supply voltage of the NOR gates 40 and 42 and the AND circuit 43 is L, the output becomes H, and the flip-flop circuit 9 is released from reset.

The AND circuit 38, the NAND circuit 39, and the NOR gate 40 are used as a reset timing circuit that operates the solenoids 2a and 2b once, and the inverter element 41 and the NOR gate 42 serve as a reset timing circuit that operates the solenoids 2a and 2b twice. The AND circuit 43 is a reset timing circuit that operates the solenoids 2a and 2b 18 times.

The output of the NOR gate 40 is always L when the outputs of the output terminals Q ₁ and Q ₂ of the flip-flop circuit 9 are H, and the output of the NOR gate 42 is always set to L when the output from the output terminal Q ₂ of the flip-flop circuit 9 is H.
The output is set to L when .

The solenoids 2a and 2b are connected to the switching circuit 4.
5 and 46, respectively, and the switching circuit 4
5 and 46 are connected to OR gates 47 and 48, respectively, and OR gates 47 and 48 are connected to the output terminal _Q0b of the 8-bit binary counter circuit 10. The output terminal _Q0b of this 8-bit binary counter circuit 10 is connected to an AND circuit 49, and the NOR gate 36 and the AND circuit 49 are connected to the flip-flop circuit 9 and the 8-bit binary counter circuit 10.
and OR circuits 19 and 20 constitute a signal generating means. This signal generating means generates game state signals that correspond to any one of the normal state, a specific state, and a special state, and are different from each other, based on the presence or absence of pachinko balls that fly into the specific winning hole and the continuous winning hole 4. , light emitting diodes 8a to 8g, display circuit 5
0 and sound effect generating circuit 18, and has a function of controlling the above-mentioned light emitting diode blinking circuit 17 and sound effect generating circuit 18.
The sound effect generation circuit 18 is the solenoid 2 here.
A sound effect is generated while a and 2b operate 18 times. 50, solenoids 2a and 2b are 18
This is a display circuit that serves as a display means for indicating that rotation is in progress, and is roughly composed of a lamp 52 and an AND circuit 53.

Next, the effect will be explained.

() Winning ball switch 6 that operates once in the normal state;
The 2-time operation winning ball switch 7 and the 18-time operation winning ball switch 5 are all open, the inputs of the set terminals S ₀ , S ₁ , and S ₂ of the flip-flop circuit 9 are H, and the input of one input terminal of the OR gate 21 is in the open state. is H,
When the input of other input terminals is L.

Output terminals Q ₀ to _{Q 2} of flip/lop circuit 9
The output of is L, and the output of OR gate 21 is H, so H is input to one input terminal of NAND gate 13, L is input to the other input terminal, and H is output from NAND gate 13. be done. Therefore, the input to the reset terminal Ra of the 8-bit binary counter circuit 10 is set to L, and the input to the reset terminal Rb of the 8-bit binary counter circuit 10 is set to H. Therefore, the reset of the reset terminal Ra of the 8-bit binary counter circuit 10 is released.
The output from the output terminal Q _0a is released, and the clock signal from the clock oscillation circuit 16 is output from the output terminal Q _0a , and the light emitting diode group 27
As shown in Figure 1, each diode row repeats the blinking state from the top and bottom toward the center.
Normal status can be displayed.

On the other hand, the reset terminal Rb of the 8-bit binary counter circuit 10 is reset, and output from the output terminals Q _0b to Q _3b is prohibited.
Solenoids 2a and 2b are not driven.

() One-time operation winning ball switch 6 from normal state
is closed and the input to the other input terminal of the OR gate 21 is L.

Once the winning ball switch 6 is closed,
The set terminal _S0 of the flip-flop circuit 9 changes from H to L, and the output from the output terminal _Q0 changes from L to H. The output is input to the reset terminal Ra of the 8-bit binary counter circuit 10 via the delay circuit 12, and is also input to the NAND gate 1.
3 is input to the other input terminal. On the other hand, the OR gate 21 is outputting H at this time, and its output is input to one input terminal of the NAND gate 13, and from the NAND gate 13, L is input to the reset terminal Rb of the 8-bit binary counter circuit 10. Ru. Note that the input to the reset terminal Rb is set to L at the same time as the input to the reset terminal Ra is set to H. Therefore, the reset terminal Ra of the 8-bit binary counter circuit 10 is reset for 0.5 seconds, and output from the output terminal _Q0 is prohibited. In addition, 8-bit binary counter circuit 1
The reset terminal Rb of 0 is released from reset, and the output terminals Q _0b to Q _3b output rectangular signals as shown in FIG.

Therefore, the solenoids 2a and 2b are driven, but due to the one-time operation reset timing circuit of the AND circuit 38, NAND circuit 39, and NOR gate 40, when the NAND circuit 39 outputs an H level, the NOR circuit 44 outputs an L level. The reset terminals R ₀ , R ₁ , R ₂ of the flip-flop circuit 9
is reset (see Figure 6).

Therefore, output from the output terminals Q ₀ , Q ₁ , and Q ₂ of the flip-flop circuit 9 is prohibited, and the solenoids 2a and 2b are driven for only 0.5 seconds as shown in FIG. Transition from a state to a specific state. In this case, as described above, the output from the output terminal Q _0a of the 8-bit binary counter circuit 10 to the light emitting diode blinking circuit 17 is prohibited for a predetermined period of time, while the rectangular signal as shown in FIG. 6 is output from the output terminal Q _0b. The signal is output to the sound effect generating circuit 18 for a predetermined period of time.

As a result, the light emitting diode blinking circuit 17 and the sound effect generating circuit 18 notify that the normal state has transitioned to the specific state by displaying content different from the normal state. Moreover, in the 8-bit binary counter 10, the inhibition and output timing of the rectangular signal differ depending on the detection of the one-time operation switch 6 and the two-time operation switch 7.
8 can display two types of specific states.

() The winning ball switch 7 is closed twice,
When the input to the other input terminal of the OR gate 21 is L.

When the two-time operation winning ball switch 7 is closed,
The set terminal _S1 of the flip-flop circuit 9 changes from H to L, and the output from the output terminal _Q1 changes from L to H. The output thereof is inputted to the reset terminal Ra of the 8-bit binary counter circuit 10 via the delay circuit 12, as in the case () above, and is also inputted to the other input terminals of the NAND gate 13. On the other hand, ORGATE 21 is H at this time.
The output is NAND gate 13
is input to one input terminal of the 8-bit binary counter circuit 1 from the NAND gate 13.
L is input to the 0 reset terminal Rb. still,
At this time as well, the input to the reset terminal Rb is set to L at the same time as the input to the reset terminal Ra is set to H.

Therefore, the 8-bit binary counter circuit 1
0 reset terminal Ra is reset for 0.5 seconds,
Output from output terminal Q _0a is prohibited. Also,
The reset terminal Rb of the 8-bit binary counter circuit 10 becomes the output terminal after the reset is released.
A rectangular signal as shown in FIG. 5 is output from Q _0b to Q _3b .

Therefore, the solenoids 2a and 2b are driven, but due to the two-time reset timing circuit of the inverter element 41 and the NOR gate 42, when the NOR gate 42 outputs an H level, the NOR circuit 44 outputs an L level, and the flip-flop circuit The reset terminals R ₀ , R ₁ and R ₂ of 9 are reset (see FIG. 7).

Therefore, output from the output terminals Q ₀ , Q ₁ , and Q ₂ of the flip-flop circuit 9 is prohibited, and the solenoids 2a and 2b are driven only twice for 0.8 seconds each as shown in FIG. Ru. As described above, the one or two operations of the guide vanes 1c and 1d are in the first state.

() Winning ball switch 5 that operates 18 times from a specific state
when is closed.

When the 18th operation winning ball switch 5 is closed,
L is momentarily input to one input terminal of the OR gate 21, and at this time, L is input from the output terminal _Q6b of the shift register 24 to the other input terminal of the OR gate 21, and L is output from the OR gate 21. be done. Its output is NAND gate 13
At this time, if the guide vanes 1c and 1d are in the middle of the first and second operations, H is input to the other input terminal of the NAND gate 13. The output is input to the reset terminal Rb of the 8-bit binary counter circuit 10. Therefore, the reset terminal Rb is instantaneously reset, and the output from the output terminal _Q0b of the 8-bit binary counter circuit 10 is prohibited. Therefore, in the middle of the first and second movements
When the 18th operation winning ball switch 5 is closed, the 1st and 2nd operation immediately ends at that point.
Further, the output from the OR gate 21 is input to the set terminal _S2 of the flip-flop circuit 9, and H is output from the output terminal _Q2 . Its output H
are OR circuit 20, OR circuit 19, delay circuit 1
2, it is inputted to the reset terminal Ra of the 8-bit binary counter circuit 10 as well as to the other input terminals of the NAND gate 13, as in () and () above. On the other hand, at this time, the 18th operation winning ball switch 5 is open, H is input to one input terminal of the OR gate 21, H is output from the OR gate 21, and one input terminal of the NAND gate 13 is H. The L output from the NAND gate 13 is input to the reset terminal Rb of the 8-bit binary counter 10.

In this case, as in () and () above, the input to the reset terminal Rb is set to L at the same time as the input to the reset terminal Ra is set to H.

Therefore, the 8-bit binary counter circuit 1
The reset terminal Ra of 0 is reset, and output from the output terminal _Q0a is prohibited. In addition, the reset terminal of the 8-bit binary counter circuit 10
Rb is released from reset and output terminal Q _0b ~
A rectangular signal as shown in FIG. 5 is output from Q _3b .

Therefore, the solenoids 2a and 2b are driven, but due to the 18-time operation reset timing circuit of the AND circuit 43, when the AND circuit 43 outputs H, the NOR circuit 44 outputs L, and the flip-flop circuit 9 reset terminal
R ₀ , R ₁ and R ₂ are reset (see Figure 8).

Therefore, output from the output terminals Q ₀ , Q ₁ , and Q ₂ of the flip-flop circuit 9 is prohibited, and the solenoids 2a and 2b are driven 18 times for 0.8 seconds each as shown in FIG. Because
Transition from a specific state to a special state. At this time 8
The output from the output terminal _Q0a of the bit binary counter 10 to the light emitting diode blinking circuit 17 is
The user will be prohibited for a specified period of time for 18 movements. On the other hand,
The H signal from the output terminal _Q2 of the flip-flop circuit 9 is input to the sound effect generating circuit 18. As a result, the light emitting diode blinking circuit 17 and the sound effect generating circuit 18 notify the transition from the specific state to the special state using display contents different from those in the normal state and the specific state. In this way, the 18 opening and closing operations of the guide members 1c and 1d are in the second state.

In addition, during the 18 operations of guide vanes 1c and 1d,
The output of the OR circuit 19 is H, and even if there is a win in the 1st or 2nd operation to a specific winning hole during the 18th operation, the output of the OR circuit 19 remains H and does not change. The binary counter circuit 10 is not reset, and the 1st and 2nd time operation by the 1-time winning ball switch 6 and the 2-time winning ball switch 7 is performed.
Signals due to winnings during the 18th round are ignored and the 18th round continues as is.

Since the output from the NOR circuit 44 is input to the reset terminals R ₀ , R ₁ , and R ₂ of the flip-flop circuit 9, it is assumed that there is a win in the 1st and 2nd operation from the specific winning opening during the 18th operation. Also, 18
Output of flip-flop circuit 9 at the end of rotation
Since Q ₀ , Q ₁ , and Q ₂ are all reset, after the 18th operation is completed, the 1st and 2nd operations will not be performed due to winnings of the 1st and 2nd operations during the relevant operation.

Also, while the solenoids 2a and 2b are being driven, 18
When the 18-time winning ball switch 5 is closed again, L is momentarily input to the input terminal of the OR gate 21 due to the closing of the 18-time winning ball switch 5, and the OR gate 21 responds accordingly. L is output momentarily. The output is input to one input terminal of the NAND gate 13, and at this time, since H is input to the other input terminal of the NAND gate 13, H is momentarily output from the NAND gate 13, and the output is 8 bits. It is input to the reset terminal Rb of the binary counter circuit 10. Therefore, the reset terminal Rb is momentarily reset, and the output from the output terminal _Q0b of the 8-bit binary counter circuit 10 is momentarily inhibited (see FIG. 9).

Therefore, the 18-time operation rectangular signal from the output terminal _Q0b of the 8-bit binary counter circuit 10 is restarted from the beginning, as shown in FIG.

The H output from the output terminal Q ₂ of the flip-flop circuit 9 is further input to the reset terminal R of the shift register 23 and also to the NOR gate 3.
6 is input. Therefore, shift register 2
Output from output terminals Q ₀ to _{Q 3} of 3 is prohibited,
While all the light emitting diodes 8a to 8g are turned off, the NOR gate 36 outputs L, and the output is sent to the reset terminal of the shift register 24.
Ra, Rb are input to the reset terminals Ra, Rb.
The reset of Rb is canceled. At this time, the output from the OR gate 21 accompanying the closing of the 18-time winning ball switch 5 is input to the input terminals Ca and Cb of the shift register 24 via the inverter element 37.
H is output from the output terminal Q _0a , and accordingly, the light emitting diode 8a is turned on. Thereafter, when the winning ball switch 5, which operates 18 times, is repeatedly opened and closed 8 times, the light emitting diodes 8b to 8g are lit in this order.

When all the light emitting diodes 8a to 8g are turned on, H is output from the output terminal _Q6b of the shift register 24, and the inputs of the other input terminals of the OR gate 21 are set to H. Therefore, ORGATE 2
After the 18-time winning ball switch 5 is opened and closed 8 times, the output of 1 is set to H regardless of whether the 18-time winning ball switch 5 is opened or closed, and the light emitting diode group 27 is not lit thereafter.

In addition, in the winning probability increasing state, if the prize winning ball switch 5 does not win, the guide blade moves once and twice as described above, and it ends with the 18th movement, but it does not reach the winning area of the winning device. The game may end when a predetermined number of pachinko balls (for example, 10 balls) win.

As is clear from the above description, in the present invention, the notification means is activated in response to the increase in winning probability due to the opening/closing movement of the movable piece, and lights up or blinks the indicator light and generates a sound effect, thereby improving the gameplay. and the desire to play is promoted. Furthermore, the sound effect generating means and the display means can notify the player of any gaming state based on the gaming state signal generated from the signal generating means, so that the player can clearly identify changes in the gaming state. The ball hitting timing can be adjusted by immediately following this change, and the ball hitting force can be adjusted. This reduces the number of wasted balls, so
To suppress a decline in the desire to play due to an increase in the number of wasted balls. In particular, when an advantageous right is generated, such as in a specific state or special state where the probability of winning a prize increases, the player can fully exercise that right by suppressing the number of wasted balls, giving the player a sense of satisfaction. can give.

[Brief explanation of drawings]

FIG. 1 is a schematic front view showing an embodiment of the present invention, FIG. 2 is a schematic perspective view showing an embodiment of the present invention, FIG. 3 is a control circuit diagram used in the present invention, and FIG. 5 is a signal waveform diagram of the clock signal output from the 8-bit binary counter circuit, FIG. 6 is a series of signal waveform diagrams when the solenoid is made to open and close once, and FIG. A series of signal waveform diagrams when the solenoid is made to open and close twice. Figure 8 is a series of signal waveform diagrams when the solenoid is made to open and close 18 times. Figure 9 is a diagram when the solenoid opens and closes 18 times. It is a series of signal waveform diagrams when the winning ball switch is closed during the 18th operation. 1... winning device, 1c, 1d... movable piece, 2
a, 2b...Electric drive unit (solenoid), 4...
Continuous winning opening, 5... Continuous winning detector (18 times operating winning ball switch), 6, 7... Specific winning detector (1
Rotation winning ball switch, double action winning ball switch), {18...Sound effect generation circuit, 23, 24...
Shift register, 25, 26... OR circuit group, light emitting diode drive circuit, 27... light emitting diode group, 50... display circuit} Notification means.

Claims (1)

[Claims] 1 A winning device equipped with an electric drive unit that interlocks a movable piece in the direction of picking up pachinko balls, and a winning device that is activated when a pachinko ball flies into a specific winning opening during a normal state,
a winning probability increase control device that drives the electric drive unit to form a specific state in which the winning probability of the winning device increases for a predetermined time; and during the specific state, pachinko balls are placed in a special winning opening different from the specific winning opening. A special state is formed in which the winning probability is higher than in the specific state when a pachinko ball enters the special winning hole, and when a pachinko ball enters the special winning hole during the special state, the special state is restarted from the beginning. A control circuit for controlling a winning probability increase control device, a sound effect generating means for displaying the specific state or the special state by a sound effect, and a mode in which any of the normal state, the specific state, and the special state is different from each other. and a display means for displaying game state signals corresponding to any one of a normal state, a specific state, and a special state and different from each other based on the presence or absence of pachinko balls flying into the specific winning hole and the special winning hole. A pachinko machine comprising a sound effect generating means and a signal generating means input to a display means.